[deliverable/linux.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * Resource definition for the MXC IrDA
 */
static struct resource mxc_irda_resources[] = {
	[0] = {
		.start   = UART3_BASE_ADDR,
		.end     = UART3_BASE_ADDR + SZ_4K - 1,
		.flags   = IORESOURCE_MEM,
	},
	[1] = {
		.start   = MXC_INT_UART3,
		.end     = MXC_INT_UART3,
		.flags   = IORESOURCE_IRQ,
	},
};

/* Platform Data for MXC IrDA */
struct platform_device mxc_irda_device = {
	.name = "mxc_irda",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_irda_resources),
	.resource = mxc_irda_resources,
};

/*
 * General Purpose Timer
 * - i.MX1: 2 timer (slighly different register handling)
 * - i.MX21: 3 timer
 * - i.MX27: 6 timer
 */

/* We use gpt0 as system timer, so do not add a device for this one */

static struct resource timer1_resources[] = {
	[0] = {
		.start	= GPT2_BASE_ADDR,
		.end	= GPT2_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT2,
		.end     = MXC_INT_GPT2,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt1 = {
	.name = "imx_gpt",
	.id = 1,
	.num_resources = ARRAY_SIZE(timer1_resources),
	.resource = timer1_resources
};

static struct resource timer2_resources[] = {
	[0] = {
		.start	= GPT3_BASE_ADDR,
		.end	= GPT3_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT3,
		.end     = MXC_INT_GPT3,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt2 = {
	.name = "imx_gpt",
	.id = 2,
	.num_resources = ARRAY_SIZE(timer2_resources),
	.resource = timer2_resources
};

#ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = {
	[0] = {
		.start	= GPT4_BASE_ADDR,
		.end	= GPT4_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT4,
		.end     = MXC_INT_GPT4,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt3 = {
	.name = "imx_gpt",
	.id = 3,
	.num_resources = ARRAY_SIZE(timer3_resources),
	.resource = timer3_resources
};

static struct resource timer4_resources[] = {
	[0] = {
		.start	= GPT5_BASE_ADDR,
		.end	= GPT5_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT5,
		.end     = MXC_INT_GPT5,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt4 = {
	.name = "imx_gpt",
	.id = 4,
	.num_resources = ARRAY_SIZE(timer4_resources),
	.resource = timer4_resources
};

static struct resource timer5_resources[] = {
	[0] = {
		.start	= GPT6_BASE_ADDR,
		.end	= GPT6_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_GPT6,
		.end     = MXC_INT_GPT6,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt5 = {
	.name = "imx_gpt",
	.id = 5,
	.num_resources = ARRAY_SIZE(timer5_resources),
	.resource = timer5_resources
};
#endif

/*
 * Watchdog:
 * - i.MX1
 * - i.MX21
 * - i.MX27
 */
static struct resource mxc_wdt_resources[] = {
	{
		.start	= WDOG_BASE_ADDR,
		.end	= WDOG_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "mxc_wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= NFC_BASE_ADDR,
		.end	= NFC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

#ifdef CONFIG_FB_IMX
/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = LCDC_BASE_ADDR,
		.end   = LCDC_BASE_ADDR + 0xFFF,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_LCDC,
		.end   = MXC_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = 0xFFFFFFFF,
	},
};
#endif

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start	= FEC_BASE_ADDR,
		.end	= FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource mxc_i2c_1_resources[] = {
	[0] = {
		.start	= I2C_BASE_ADDR,
		.end	= I2C_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start	= MXC_INT_I2C,
		.end	= MXC_INT_I2C,
		.flags	= IORESOURCE_IRQ
	}
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	.resource = mxc_i2c_1_resources
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = {
	[0] = {
		.start	= I2C2_BASE_ADDR,
		.end	= I2C2_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start	= MXC_INT_I2C2,
		.end	= MXC_INT_I2C2,
		.flags	= IORESOURCE_IRQ
	}
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	.resource = mxc_i2c_2_resources
};
#endif

static struct resource mxc_pwm_resources[] = {
	[0] = {
		.start	= PWM_BASE_ADDR,
		.end	= PWM_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM
	},
	[1] = {
		.start   = MXC_INT_PWM,
		.end     = MXC_INT_PWM,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources
};

/*
 * Resource definition for the MXC SDHC
 */
static struct resource mxc_sdhc1_resources[] = {
	[0] = {
			.start = SDHC1_BASE_ADDR,
			.end   = SDHC1_BASE_ADDR + SZ_4K - 1,
			.flags = IORESOURCE_MEM,
			},
	[1] = {
			.start = MXC_INT_SDHC1,
			.end   = MXC_INT_SDHC1,
			.flags = IORESOURCE_IRQ,
			},
	[2] = {
			.start  = DMA_REQ_SDHC1,
			.end    = DMA_REQ_SDHC1,
			.flags  = IORESOURCE_DMA
		},
};

static u64 mxc_sdhc1_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device0 = {
       .name           = "mxc-mmc",
       .id             = 0,
       .dev            = {
               .dma_mask = &mxc_sdhc1_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
       .resource       = mxc_sdhc1_resources,
};

static struct resource mxc_sdhc2_resources[] = {
	[0] = {
			.start = SDHC2_BASE_ADDR,
			.end   = SDHC2_BASE_ADDR + SZ_4K - 1,
			.flags = IORESOURCE_MEM,
			},
	[1] = {
			.start = MXC_INT_SDHC2,
			.end   = MXC_INT_SDHC2,
			.flags = IORESOURCE_IRQ,
			},
	[2] = {
			.start  = DMA_REQ_SDHC2,
			.end    = DMA_REQ_SDHC2,
			.flags  = IORESOURCE_DMA
		},
};

static u64 mxc_sdhc2_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device1 = {
       .name           = "mxc-mmc",
       .id             = 1,
       .dev            = {
               .dma_mask = &mxc_sdhc2_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
       .resource       = mxc_sdhc2_resources,
};

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	[0] = {
		.chip.label = "gpio-0",
		.irq = MXC_INT_GPIO,
		.base = IO_ADDRESS(GPIO_BASE_ADDR),
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	},
	[1] = {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	},
	[2] = {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	},
	[3] = {
		.chip.label = "gpio-3",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
	},
	[4] = {
		.chip.label = "gpio-4",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
	},
	[5] = {
		.chip.label = "gpio-5",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
	34
80b02c17	35	#include <mach/irqs.h>
a09e64fb	36	#include <mach/hardware.h>
058b7a6f	37	#include <mach/common.h>
1a02be0e	38	#include <mach/mmc.h>
058b7a6f HS	39
058b7a6f HS	40	#include "devices.h"
fc80a5e3 JB	41
	42	/*
	43	* Resource definition for the MXC IrDA
	44	*/
	45	static struct resource mxc_irda_resources[] = {
	46	[0] = {
	47	.start = UART3_BASE_ADDR,
	48	.end = UART3_BASE_ADDR + SZ_4K - 1,
	49	.flags = IORESOURCE_MEM,
	50	},
	51	[1] = {
	52	.start = MXC_INT_UART3,
	53	.end = MXC_INT_UART3,
	54	.flags = IORESOURCE_IRQ,
	55	},
	56	};
	57
	58	/* Platform Data for MXC IrDA */
	59	struct platform_device mxc_irda_device = {
	60	.name = "mxc_irda",
	61	.id = 0,
	62	.num_resources = ARRAY_SIZE(mxc_irda_resources),
	63	.resource = mxc_irda_resources,
	64	};
	65
	66	/*
	67	* General Purpose Timer
	68	* - i.MX1: 2 timer (slighly different register handling)
	69	* - i.MX21: 3 timer
	70	* - i.MX27: 6 timer
	71	*/
	72
	73	/* We use gpt0 as system timer, so do not add a device for this one */
	74
	75	static struct resource timer1_resources[] = {
	76	[0] = {
	77	.start = GPT2_BASE_ADDR,
	78	.end = GPT2_BASE_ADDR + 0x17,
	79	.flags = IORESOURCE_MEM
	80	},
	81	[1] = {
	82	.start = MXC_INT_GPT2,
	83	.end = MXC_INT_GPT2,
	84	.flags = IORESOURCE_IRQ,
	85	}
	86	};
	87
	88	struct platform_device mxc_gpt1 = {
	89	.name = "imx_gpt",
	90	.id = 1,
	91	.num_resources = ARRAY_SIZE(timer1_resources),
	92	.resource = timer1_resources
	93	};
	94
	95	static struct resource timer2_resources[] = {
	96	[0] = {
	97	.start = GPT3_BASE_ADDR,
	98	.end = GPT3_BASE_ADDR + 0x17,
	99	.flags = IORESOURCE_MEM
	100	},
	101	[1] = {
	102	.start = MXC_INT_GPT3,
	103	.end = MXC_INT_GPT3,
	104	.flags = IORESOURCE_IRQ,
105	}
106	};
107
108	struct platform_device mxc_gpt2 = {
109	.name = "imx_gpt",
110	.id = 2,
111	.num_resources = ARRAY_SIZE(timer2_resources),
112	.resource = timer2_resources
113	};
114
115	#ifdef CONFIG_MACH_MX27
116	static struct resource timer3_resources[] = {
117	[0] = {
118	.start = GPT4_BASE_ADDR,
119	.end = GPT4_BASE_ADDR + 0x17,
120	.flags = IORESOURCE_MEM
121	},
122	[1] = {
123	.start = MXC_INT_GPT4,
124	.end = MXC_INT_GPT4,
125	.flags = IORESOURCE_IRQ,
126	}
127	};
128
129	struct platform_device mxc_gpt3 = {
130	.name = "imx_gpt",
131	.id = 3,
132	.num_resources = ARRAY_SIZE(timer3_resources),
133	.resource = timer3_resources
134	};
135
136	static struct resource timer4_resources[] = {
137	[0] = {
138	.start = GPT5_BASE_ADDR,
139	.end = GPT5_BASE_ADDR + 0x17,
140	.flags = IORESOURCE_MEM
141	},
142	[1] = {
143	.start = MXC_INT_GPT5,
144	.end = MXC_INT_GPT5,
145	.flags = IORESOURCE_IRQ,
146	}
147	};
148
149	struct platform_device mxc_gpt4 = {
150	.name = "imx_gpt",
151	.id = 4,
152	.num_resources = ARRAY_SIZE(timer4_resources),
153	.resource = timer4_resources
154	};
155
156	static struct resource timer5_resources[] = {
157	[0] = {
158	.start = GPT6_BASE_ADDR,
159	.end = GPT6_BASE_ADDR + 0x17,
160	.flags = IORESOURCE_MEM
161	},
162	[1] = {
163	.start = MXC_INT_GPT6,
164	.end = MXC_INT_GPT6,
165	.flags = IORESOURCE_IRQ,
166	}
167	};
168
169	struct platform_device mxc_gpt5 = {
170	.name = "imx_gpt",
171	.id = 5,
172	.num_resources = ARRAY_SIZE(timer5_resources),
173	.resource = timer5_resources
174	};
175	#endif
176
177	/*
178	* Watchdog:
179	* - i.MX1
180	* - i.MX21
181	* - i.MX27
182	*/
183	static struct resource mxc_wdt_resources[] = {
184	{
185	.start = WDOG_BASE_ADDR,
186	.end = WDOG_BASE_ADDR + 0x30,
187	.flags = IORESOURCE_MEM,
188	},
189	};
190
191	struct platform_device mxc_wdt = {
192	.name = "mxc_wdt",
193	.id = 0,
194	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
195	.resource = mxc_wdt_resources,
196	};
197
3d89baa7 SH	198	static struct resource mxc_w1_master_resources[] = {
	199	{
	200	.start = OWIRE_BASE_ADDR,
	201	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	202	.flags = IORESOURCE_MEM,
	203	},
	204	};
	205
	206	struct platform_device mxc_w1_master_device = {
	207	.name = "mxc_w1",
	208	.id = 0,
	209	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	210	.resource = mxc_w1_master_resources,
	211	};
	212
02870978 SH	213	static struct resource mxc_nand_resources[] = {
	214	{
	215	.start = NFC_BASE_ADDR,
	216	.end = NFC_BASE_ADDR + 0xfff,
	217	.flags = IORESOURCE_MEM
	218	}, {
	219	.start = MXC_INT_NANDFC,
	220	.end = MXC_INT_NANDFC,
	221	.flags = IORESOURCE_IRQ
	222	},
	223	};
	224
	225	struct platform_device mxc_nand_device = {
	226	.name = "mxc_nand",
	227	.id = 0,
	228	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	229	.resource = mxc_nand_resources,
	230	};
	231
e4813551 HS	232	#ifdef CONFIG_FB_IMX
	233	/*
	234	* lcdc:
	235	* - i.MX1: the basic controller
	236	* - i.MX21: to be checked
	237	* - i.MX27: like i.MX1, with slightly variations
	238	*/
	239	static struct resource mxc_fb[] = {
	240	{
	241	.start = LCDC_BASE_ADDR,
	242	.end = LCDC_BASE_ADDR + 0xFFF,
	243	.flags = IORESOURCE_MEM,
	244	},
	245	{
	246	.start = MXC_INT_LCDC,
	247	.end = MXC_INT_LCDC,
	248	.flags = IORESOURCE_IRQ,
	249	}
	250	};
	251
	252	/* mxc lcd driver */
	253	struct platform_device mxc_fb_device = {
	254	.name = "imx-fb",
	255	.id = 0,
	256	.num_resources = ARRAY_SIZE(mxc_fb),
	257	.resource = mxc_fb,
	258	.dev = {
	259	.coherent_dma_mask = 0xFFFFFFFF,
	260	},
	261	};
879fea1b	262	#endif
e4813551	263
879fea1b SH	264	#ifdef CONFIG_MACH_MX27
	265	static struct resource mxc_fec_resources[] = {
	266	{
	267	.start = FEC_BASE_ADDR,
	268	.end = FEC_BASE_ADDR + 0xfff,
	269	.flags = IORESOURCE_MEM
	270	}, {
	271	.start = MXC_INT_FEC,
	272	.end = MXC_INT_FEC,
	273	.flags = IORESOURCE_IRQ
	274	},
	275	};
	276
	277	struct platform_device mxc_fec_device = {
	278	.name = "fec",
	279	.id = 0,
	280	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	281	.resource = mxc_fec_resources,
	282	};
e4813551 HS	283	#endif
e4813551 HS	284
c5d4dbff SH	285	static struct resource mxc_i2c_1_resources[] = {
	286	[0] = {
	287	.start = I2C_BASE_ADDR,
	288	.end = I2C_BASE_ADDR + 0x0fff,
	289	.flags = IORESOURCE_MEM
	290	},
	291	[1] = {
	292	.start = MXC_INT_I2C,
	293	.end = MXC_INT_I2C,
	294	.flags = IORESOURCE_IRQ
	295	}
	296	};
	297
	298	struct platform_device mxc_i2c_device0 = {
	299	.name = "imx-i2c",
	300	.id = 0,
	301	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	302	.resource = mxc_i2c_1_resources
	303	};
	304
	305	#ifdef CONFIG_MACH_MX27
	306	static struct resource mxc_i2c_2_resources[] = {
	307	[0] = {
	308	.start = I2C2_BASE_ADDR,
	309	.end = I2C2_BASE_ADDR + 0x0fff,
	310	.flags = IORESOURCE_MEM
	311	},
	312	[1] = {
	313	.start = MXC_INT_I2C2,
	314	.end = MXC_INT_I2C2,
	315	.flags = IORESOURCE_IRQ
	316	}
	317	};
	318
	319	struct platform_device mxc_i2c_device1 = {
	320	.name = "imx-i2c",
	321	.id = 1,
	322	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	323	.resource = mxc_i2c_2_resources
	324	};
	325	#endif
	326
824b16e6 SH	327	static struct resource mxc_pwm_resources[] = {
	328	[0] = {
	329	.start = PWM_BASE_ADDR,
	330	.end = PWM_BASE_ADDR + 0x0fff,
	331	.flags = IORESOURCE_MEM
	332	},
	333	[1] = {
	334	.start = MXC_INT_PWM,
	335	.end = MXC_INT_PWM,
	336	.flags = IORESOURCE_IRQ,
	337	}
	338	};
	339
	340	struct platform_device mxc_pwm_device = {
	341	.name = "mxc_pwm",
	342	.id = 0,
	343	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	344	.resource = mxc_pwm_resources
	345	};
	346
1a02be0e SH	347	/*
	348	* Resource definition for the MXC SDHC
	349	*/
	350	static struct resource mxc_sdhc1_resources[] = {
	351	[0] = {
	352	.start = SDHC1_BASE_ADDR,
	353	.end = SDHC1_BASE_ADDR + SZ_4K - 1,
	354	.flags = IORESOURCE_MEM,
	355	},
	356	[1] = {
	357	.start = MXC_INT_SDHC1,
	358	.end = MXC_INT_SDHC1,
	359	.flags = IORESOURCE_IRQ,
	360	},
	361	[2] = {
	362	.start = DMA_REQ_SDHC1,
	363	.end = DMA_REQ_SDHC1,
	364	.flags = IORESOURCE_DMA
	365	},
	366	};
	367
	368	static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
	369
	370	struct platform_device mxc_sdhc_device0 = {
	371	.name = "mxc-mmc",
	372	.id = 0,
	373	.dev = {
	374	.dma_mask = &mxc_sdhc1_dmamask,
	375	.coherent_dma_mask = 0xffffffff,
	376	},
	377	.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
	378	.resource = mxc_sdhc1_resources,
	379	};
	380
	381	static struct resource mxc_sdhc2_resources[] = {
	382	[0] = {
	383	.start = SDHC2_BASE_ADDR,
	384	.end = SDHC2_BASE_ADDR + SZ_4K - 1,
	385	.flags = IORESOURCE_MEM,
	386	},
	387	[1] = {
	388	.start = MXC_INT_SDHC2,
	389	.end = MXC_INT_SDHC2,
	390	.flags = IORESOURCE_IRQ,
	391	},
	392	[2] = {
	393	.start = DMA_REQ_SDHC2,
	394	.end = DMA_REQ_SDHC2,
	395	.flags = IORESOURCE_DMA
	396	},
	397	};
	398
	399	static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
	400
	401	struct platform_device mxc_sdhc_device1 = {
	402	.name = "mxc-mmc",
	403	.id = 1,
	404	.dev = {
	405	.dma_mask = &mxc_sdhc2_dmamask,
	406	.coherent_dma_mask = 0xffffffff,
	407	},
	408	.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
	409	.resource = mxc_sdhc2_resources,
	410	};
411
fc80a5e3 JB	412	/* GPIO port description */
	413	static struct mxc_gpio_port imx_gpio_ports[] = {
	414	[0] = {
	415	.chip.label = "gpio-0",
	416	.irq = MXC_INT_GPIO,
058b7a6f	417	.base = IO_ADDRESS(GPIO_BASE_ADDR),
9d631b83	418	.virtual_irq_start = MXC_GPIO_IRQ_START,
fc80a5e3 JB	419	},
	420	[1] = {
	421	.chip.label = "gpio-1",
058b7a6f	422	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
9d631b83	423	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
fc80a5e3 JB	424	},
	425	[2] = {
	426	.chip.label = "gpio-2",
058b7a6f	427	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
9d631b83	428	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
fc80a5e3 JB	429	},
	430	[3] = {
	431	.chip.label = "gpio-3",
058b7a6f	432	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
9d631b83	433	.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
fc80a5e3 JB	434	},
	435	[4] = {
	436	.chip.label = "gpio-4",
058b7a6f	437	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
9d631b83	438	.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
fc80a5e3 JB	439	},
	440	[5] = {
	441	.chip.label = "gpio-5",
058b7a6f	442	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
9d631b83	443	.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
fc80a5e3 JB	444	}
	445	};
	446
	447	int __init mxc_register_gpios(void)
	448	{
	449	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	450	}