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fc80a5e3 JB |
1 | /* |
2 | * Author: MontaVista Software, Inc. | |
3 | * <source@mvista.com> | |
4 | * | |
5 | * Based on the OMAP devices.c | |
6 | * | |
7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | * | |
12 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
13 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version 2 | |
18 | * of the License, or (at your option) any later version. | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
27 | * MA 02110-1301, USA. | |
28 | */ | |
29 | #include <linux/module.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/gpio.h> | |
34 | ||
80b02c17 | 35 | #include <mach/irqs.h> |
a09e64fb | 36 | #include <mach/hardware.h> |
058b7a6f | 37 | #include <mach/common.h> |
1a02be0e | 38 | #include <mach/mmc.h> |
058b7a6f HS |
39 | |
40 | #include "devices.h" | |
fc80a5e3 | 41 | |
f420db84 SH |
42 | /* |
43 | * SPI master controller | |
44 | * | |
45 | * - i.MX1: 2 channel (slighly different register setting) | |
46 | * - i.MX21: 2 channel | |
47 | * - i.MX27: 3 channel | |
48 | */ | |
49 | static struct resource mxc_spi_resources0[] = { | |
50 | { | |
51 | .start = CSPI1_BASE_ADDR, | |
52 | .end = CSPI1_BASE_ADDR + SZ_4K - 1, | |
53 | .flags = IORESOURCE_MEM, | |
54 | }, { | |
55 | .start = MXC_INT_CSPI1, | |
56 | .end = MXC_INT_CSPI1, | |
57 | .flags = IORESOURCE_IRQ, | |
58 | }, | |
59 | }; | |
60 | ||
61 | static struct resource mxc_spi_resources1[] = { | |
62 | { | |
63 | .start = CSPI2_BASE_ADDR, | |
64 | .end = CSPI2_BASE_ADDR + SZ_4K - 1, | |
65 | .flags = IORESOURCE_MEM, | |
66 | }, { | |
67 | .start = MXC_INT_CSPI2, | |
68 | .end = MXC_INT_CSPI2, | |
69 | .flags = IORESOURCE_IRQ, | |
70 | }, | |
71 | }; | |
72 | ||
73 | #ifdef CONFIG_MACH_MX27 | |
74 | static struct resource mxc_spi_resources2[] = { | |
75 | { | |
76 | .start = CSPI3_BASE_ADDR, | |
77 | .end = CSPI3_BASE_ADDR + SZ_4K - 1, | |
78 | .flags = IORESOURCE_MEM, | |
79 | }, { | |
80 | .start = MXC_INT_CSPI3, | |
81 | .end = MXC_INT_CSPI3, | |
82 | .flags = IORESOURCE_IRQ, | |
83 | }, | |
84 | }; | |
85 | #endif | |
86 | ||
87 | struct platform_device mxc_spi_device0 = { | |
88 | .name = "spi_imx", | |
89 | .id = 0, | |
90 | .num_resources = ARRAY_SIZE(mxc_spi_resources0), | |
91 | .resource = mxc_spi_resources0, | |
92 | }; | |
93 | ||
94 | struct platform_device mxc_spi_device1 = { | |
95 | .name = "spi_imx", | |
96 | .id = 1, | |
97 | .num_resources = ARRAY_SIZE(mxc_spi_resources1), | |
98 | .resource = mxc_spi_resources1, | |
99 | }; | |
100 | ||
101 | #ifdef CONFIG_MACH_MX27 | |
102 | struct platform_device mxc_spi_device2 = { | |
103 | .name = "spi_imx", | |
104 | .id = 2, | |
105 | .num_resources = ARRAY_SIZE(mxc_spi_resources2), | |
106 | .resource = mxc_spi_resources2, | |
107 | }; | |
108 | #endif | |
109 | ||
fc80a5e3 JB |
110 | /* |
111 | * General Purpose Timer | |
bf50bcc2 SH |
112 | * - i.MX21: 3 timers |
113 | * - i.MX27: 6 timers | |
fc80a5e3 JB |
114 | */ |
115 | ||
116 | /* We use gpt0 as system timer, so do not add a device for this one */ | |
117 | ||
118 | static struct resource timer1_resources[] = { | |
bf50bcc2 | 119 | { |
fc80a5e3 JB |
120 | .start = GPT2_BASE_ADDR, |
121 | .end = GPT2_BASE_ADDR + 0x17, | |
bf50bcc2 SH |
122 | .flags = IORESOURCE_MEM, |
123 | }, { | |
fc80a5e3 JB |
124 | .start = MXC_INT_GPT2, |
125 | .end = MXC_INT_GPT2, | |
126 | .flags = IORESOURCE_IRQ, | |
127 | } | |
128 | }; | |
129 | ||
130 | struct platform_device mxc_gpt1 = { | |
131 | .name = "imx_gpt", | |
132 | .id = 1, | |
133 | .num_resources = ARRAY_SIZE(timer1_resources), | |
bf50bcc2 | 134 | .resource = timer1_resources, |
fc80a5e3 JB |
135 | }; |
136 | ||
137 | static struct resource timer2_resources[] = { | |
bf50bcc2 | 138 | { |
fc80a5e3 JB |
139 | .start = GPT3_BASE_ADDR, |
140 | .end = GPT3_BASE_ADDR + 0x17, | |
bf50bcc2 SH |
141 | .flags = IORESOURCE_MEM, |
142 | }, { | |
fc80a5e3 JB |
143 | .start = MXC_INT_GPT3, |
144 | .end = MXC_INT_GPT3, | |
145 | .flags = IORESOURCE_IRQ, | |
146 | } | |
147 | }; | |
148 | ||
149 | struct platform_device mxc_gpt2 = { | |
150 | .name = "imx_gpt", | |
151 | .id = 2, | |
152 | .num_resources = ARRAY_SIZE(timer2_resources), | |
bf50bcc2 | 153 | .resource = timer2_resources, |
fc80a5e3 JB |
154 | }; |
155 | ||
156 | #ifdef CONFIG_MACH_MX27 | |
157 | static struct resource timer3_resources[] = { | |
bf50bcc2 | 158 | { |
fc80a5e3 JB |
159 | .start = GPT4_BASE_ADDR, |
160 | .end = GPT4_BASE_ADDR + 0x17, | |
bf50bcc2 SH |
161 | .flags = IORESOURCE_MEM, |
162 | }, { | |
fc80a5e3 JB |
163 | .start = MXC_INT_GPT4, |
164 | .end = MXC_INT_GPT4, | |
165 | .flags = IORESOURCE_IRQ, | |
166 | } | |
167 | }; | |
168 | ||
169 | struct platform_device mxc_gpt3 = { | |
170 | .name = "imx_gpt", | |
171 | .id = 3, | |
172 | .num_resources = ARRAY_SIZE(timer3_resources), | |
bf50bcc2 | 173 | .resource = timer3_resources, |
fc80a5e3 JB |
174 | }; |
175 | ||
176 | static struct resource timer4_resources[] = { | |
bf50bcc2 | 177 | { |
fc80a5e3 JB |
178 | .start = GPT5_BASE_ADDR, |
179 | .end = GPT5_BASE_ADDR + 0x17, | |
bf50bcc2 SH |
180 | .flags = IORESOURCE_MEM, |
181 | }, { | |
fc80a5e3 JB |
182 | .start = MXC_INT_GPT5, |
183 | .end = MXC_INT_GPT5, | |
184 | .flags = IORESOURCE_IRQ, | |
185 | } | |
186 | }; | |
187 | ||
188 | struct platform_device mxc_gpt4 = { | |
189 | .name = "imx_gpt", | |
190 | .id = 4, | |
191 | .num_resources = ARRAY_SIZE(timer4_resources), | |
bf50bcc2 | 192 | .resource = timer4_resources, |
fc80a5e3 JB |
193 | }; |
194 | ||
195 | static struct resource timer5_resources[] = { | |
bf50bcc2 | 196 | { |
fc80a5e3 JB |
197 | .start = GPT6_BASE_ADDR, |
198 | .end = GPT6_BASE_ADDR + 0x17, | |
bf50bcc2 SH |
199 | .flags = IORESOURCE_MEM, |
200 | }, { | |
fc80a5e3 JB |
201 | .start = MXC_INT_GPT6, |
202 | .end = MXC_INT_GPT6, | |
203 | .flags = IORESOURCE_IRQ, | |
204 | } | |
205 | }; | |
206 | ||
207 | struct platform_device mxc_gpt5 = { | |
208 | .name = "imx_gpt", | |
209 | .id = 5, | |
210 | .num_resources = ARRAY_SIZE(timer5_resources), | |
bf50bcc2 | 211 | .resource = timer5_resources, |
fc80a5e3 JB |
212 | }; |
213 | #endif | |
214 | ||
215 | /* | |
216 | * Watchdog: | |
217 | * - i.MX1 | |
218 | * - i.MX21 | |
219 | * - i.MX27 | |
220 | */ | |
221 | static struct resource mxc_wdt_resources[] = { | |
222 | { | |
223 | .start = WDOG_BASE_ADDR, | |
224 | .end = WDOG_BASE_ADDR + 0x30, | |
225 | .flags = IORESOURCE_MEM, | |
226 | }, | |
227 | }; | |
228 | ||
229 | struct platform_device mxc_wdt = { | |
230 | .name = "mxc_wdt", | |
231 | .id = 0, | |
232 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | |
233 | .resource = mxc_wdt_resources, | |
234 | }; | |
235 | ||
3d89baa7 SH |
236 | static struct resource mxc_w1_master_resources[] = { |
237 | { | |
238 | .start = OWIRE_BASE_ADDR, | |
239 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | |
240 | .flags = IORESOURCE_MEM, | |
241 | }, | |
242 | }; | |
243 | ||
244 | struct platform_device mxc_w1_master_device = { | |
245 | .name = "mxc_w1", | |
246 | .id = 0, | |
247 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
248 | .resource = mxc_w1_master_resources, | |
249 | }; | |
250 | ||
02870978 SH |
251 | static struct resource mxc_nand_resources[] = { |
252 | { | |
253 | .start = NFC_BASE_ADDR, | |
254 | .end = NFC_BASE_ADDR + 0xfff, | |
bf50bcc2 | 255 | .flags = IORESOURCE_MEM, |
02870978 SH |
256 | }, { |
257 | .start = MXC_INT_NANDFC, | |
258 | .end = MXC_INT_NANDFC, | |
bf50bcc2 | 259 | .flags = IORESOURCE_IRQ, |
02870978 SH |
260 | }, |
261 | }; | |
262 | ||
263 | struct platform_device mxc_nand_device = { | |
264 | .name = "mxc_nand", | |
265 | .id = 0, | |
266 | .num_resources = ARRAY_SIZE(mxc_nand_resources), | |
267 | .resource = mxc_nand_resources, | |
268 | }; | |
269 | ||
e4813551 HS |
270 | /* |
271 | * lcdc: | |
272 | * - i.MX1: the basic controller | |
273 | * - i.MX21: to be checked | |
274 | * - i.MX27: like i.MX1, with slightly variations | |
275 | */ | |
276 | static struct resource mxc_fb[] = { | |
277 | { | |
278 | .start = LCDC_BASE_ADDR, | |
279 | .end = LCDC_BASE_ADDR + 0xFFF, | |
280 | .flags = IORESOURCE_MEM, | |
bf50bcc2 | 281 | }, { |
e4813551 HS |
282 | .start = MXC_INT_LCDC, |
283 | .end = MXC_INT_LCDC, | |
284 | .flags = IORESOURCE_IRQ, | |
285 | } | |
286 | }; | |
287 | ||
288 | /* mxc lcd driver */ | |
289 | struct platform_device mxc_fb_device = { | |
290 | .name = "imx-fb", | |
291 | .id = 0, | |
292 | .num_resources = ARRAY_SIZE(mxc_fb), | |
293 | .resource = mxc_fb, | |
294 | .dev = { | |
295 | .coherent_dma_mask = 0xFFFFFFFF, | |
296 | }, | |
297 | }; | |
298 | ||
879fea1b SH |
299 | #ifdef CONFIG_MACH_MX27 |
300 | static struct resource mxc_fec_resources[] = { | |
301 | { | |
302 | .start = FEC_BASE_ADDR, | |
303 | .end = FEC_BASE_ADDR + 0xfff, | |
bf50bcc2 | 304 | .flags = IORESOURCE_MEM, |
879fea1b SH |
305 | }, { |
306 | .start = MXC_INT_FEC, | |
307 | .end = MXC_INT_FEC, | |
bf50bcc2 | 308 | .flags = IORESOURCE_IRQ, |
879fea1b SH |
309 | }, |
310 | }; | |
311 | ||
312 | struct platform_device mxc_fec_device = { | |
313 | .name = "fec", | |
314 | .id = 0, | |
315 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | |
316 | .resource = mxc_fec_resources, | |
317 | }; | |
e4813551 HS |
318 | #endif |
319 | ||
c5d4dbff | 320 | static struct resource mxc_i2c_1_resources[] = { |
bf50bcc2 | 321 | { |
c5d4dbff SH |
322 | .start = I2C_BASE_ADDR, |
323 | .end = I2C_BASE_ADDR + 0x0fff, | |
bf50bcc2 SH |
324 | .flags = IORESOURCE_MEM, |
325 | }, { | |
c5d4dbff SH |
326 | .start = MXC_INT_I2C, |
327 | .end = MXC_INT_I2C, | |
bf50bcc2 | 328 | .flags = IORESOURCE_IRQ, |
c5d4dbff SH |
329 | } |
330 | }; | |
331 | ||
332 | struct platform_device mxc_i2c_device0 = { | |
333 | .name = "imx-i2c", | |
334 | .id = 0, | |
335 | .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), | |
bf50bcc2 | 336 | .resource = mxc_i2c_1_resources, |
c5d4dbff SH |
337 | }; |
338 | ||
339 | #ifdef CONFIG_MACH_MX27 | |
340 | static struct resource mxc_i2c_2_resources[] = { | |
bf50bcc2 | 341 | { |
c5d4dbff SH |
342 | .start = I2C2_BASE_ADDR, |
343 | .end = I2C2_BASE_ADDR + 0x0fff, | |
bf50bcc2 SH |
344 | .flags = IORESOURCE_MEM, |
345 | }, { | |
c5d4dbff SH |
346 | .start = MXC_INT_I2C2, |
347 | .end = MXC_INT_I2C2, | |
bf50bcc2 | 348 | .flags = IORESOURCE_IRQ, |
c5d4dbff SH |
349 | } |
350 | }; | |
351 | ||
352 | struct platform_device mxc_i2c_device1 = { | |
353 | .name = "imx-i2c", | |
354 | .id = 1, | |
355 | .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), | |
bf50bcc2 | 356 | .resource = mxc_i2c_2_resources, |
c5d4dbff SH |
357 | }; |
358 | #endif | |
359 | ||
824b16e6 | 360 | static struct resource mxc_pwm_resources[] = { |
bf50bcc2 | 361 | { |
824b16e6 SH |
362 | .start = PWM_BASE_ADDR, |
363 | .end = PWM_BASE_ADDR + 0x0fff, | |
bf50bcc2 SH |
364 | .flags = IORESOURCE_MEM, |
365 | }, { | |
824b16e6 SH |
366 | .start = MXC_INT_PWM, |
367 | .end = MXC_INT_PWM, | |
368 | .flags = IORESOURCE_IRQ, | |
369 | } | |
370 | }; | |
371 | ||
372 | struct platform_device mxc_pwm_device = { | |
373 | .name = "mxc_pwm", | |
374 | .id = 0, | |
375 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | |
bf50bcc2 | 376 | .resource = mxc_pwm_resources, |
824b16e6 SH |
377 | }; |
378 | ||
1a02be0e SH |
379 | /* |
380 | * Resource definition for the MXC SDHC | |
381 | */ | |
382 | static struct resource mxc_sdhc1_resources[] = { | |
bf50bcc2 SH |
383 | { |
384 | .start = SDHC1_BASE_ADDR, | |
385 | .end = SDHC1_BASE_ADDR + SZ_4K - 1, | |
386 | .flags = IORESOURCE_MEM, | |
387 | }, { | |
388 | .start = MXC_INT_SDHC1, | |
389 | .end = MXC_INT_SDHC1, | |
390 | .flags = IORESOURCE_IRQ, | |
391 | }, { | |
392 | .start = DMA_REQ_SDHC1, | |
393 | .end = DMA_REQ_SDHC1, | |
394 | .flags = IORESOURCE_DMA, | |
395 | }, | |
1a02be0e SH |
396 | }; |
397 | ||
398 | static u64 mxc_sdhc1_dmamask = 0xffffffffUL; | |
399 | ||
400 | struct platform_device mxc_sdhc_device0 = { | |
401 | .name = "mxc-mmc", | |
402 | .id = 0, | |
403 | .dev = { | |
404 | .dma_mask = &mxc_sdhc1_dmamask, | |
405 | .coherent_dma_mask = 0xffffffff, | |
406 | }, | |
407 | .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), | |
408 | .resource = mxc_sdhc1_resources, | |
409 | }; | |
410 | ||
411 | static struct resource mxc_sdhc2_resources[] = { | |
bf50bcc2 SH |
412 | { |
413 | .start = SDHC2_BASE_ADDR, | |
414 | .end = SDHC2_BASE_ADDR + SZ_4K - 1, | |
415 | .flags = IORESOURCE_MEM, | |
416 | }, { | |
417 | .start = MXC_INT_SDHC2, | |
418 | .end = MXC_INT_SDHC2, | |
419 | .flags = IORESOURCE_IRQ, | |
420 | }, { | |
421 | .start = DMA_REQ_SDHC2, | |
422 | .end = DMA_REQ_SDHC2, | |
423 | .flags = IORESOURCE_DMA, | |
424 | }, | |
1a02be0e SH |
425 | }; |
426 | ||
427 | static u64 mxc_sdhc2_dmamask = 0xffffffffUL; | |
428 | ||
429 | struct platform_device mxc_sdhc_device1 = { | |
430 | .name = "mxc-mmc", | |
431 | .id = 1, | |
432 | .dev = { | |
433 | .dma_mask = &mxc_sdhc2_dmamask, | |
434 | .coherent_dma_mask = 0xffffffff, | |
435 | }, | |
436 | .num_resources = ARRAY_SIZE(mxc_sdhc2_resources), | |
437 | .resource = mxc_sdhc2_resources, | |
438 | }; | |
439 | ||
627fb3b9 M |
440 | static struct resource otg_resources[] = { |
441 | { | |
442 | .start = OTG_BASE_ADDR, | |
443 | .end = OTG_BASE_ADDR + 0x1ff, | |
444 | .flags = IORESOURCE_MEM, | |
445 | }, { | |
446 | .start = MXC_INT_USB3, | |
447 | .end = MXC_INT_USB3, | |
448 | .flags = IORESOURCE_IRQ, | |
449 | }, | |
450 | }; | |
451 | ||
452 | static u64 otg_dmamask = 0xffffffffUL; | |
453 | ||
454 | /* OTG gadget device */ | |
455 | struct platform_device mxc_otg_udc_device = { | |
456 | .name = "fsl-usb2-udc", | |
457 | .id = -1, | |
458 | .dev = { | |
459 | .dma_mask = &otg_dmamask, | |
460 | .coherent_dma_mask = 0xffffffffUL, | |
461 | }, | |
462 | .resource = otg_resources, | |
463 | .num_resources = ARRAY_SIZE(otg_resources), | |
464 | }; | |
465 | ||
466 | /* OTG host */ | |
467 | struct platform_device mxc_otg_host = { | |
468 | .name = "mxc-ehci", | |
469 | .id = 0, | |
470 | .dev = { | |
471 | .coherent_dma_mask = 0xffffffff, | |
472 | .dma_mask = &otg_dmamask, | |
473 | }, | |
474 | .resource = otg_resources, | |
475 | .num_resources = ARRAY_SIZE(otg_resources), | |
476 | }; | |
477 | ||
478 | /* USB host 1 */ | |
479 | ||
480 | static u64 usbh1_dmamask = 0xffffffffUL; | |
481 | ||
482 | static struct resource mxc_usbh1_resources[] = { | |
483 | { | |
484 | .start = OTG_BASE_ADDR + 0x200, | |
485 | .end = OTG_BASE_ADDR + 0x3ff, | |
486 | .flags = IORESOURCE_MEM, | |
487 | }, { | |
488 | .start = MXC_INT_USB1, | |
489 | .end = MXC_INT_USB1, | |
490 | .flags = IORESOURCE_IRQ, | |
491 | }, | |
492 | }; | |
493 | ||
494 | struct platform_device mxc_usbh1 = { | |
495 | .name = "mxc-ehci", | |
496 | .id = 1, | |
497 | .dev = { | |
498 | .coherent_dma_mask = 0xffffffff, | |
499 | .dma_mask = &usbh1_dmamask, | |
500 | }, | |
501 | .resource = mxc_usbh1_resources, | |
502 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | |
503 | }; | |
504 | ||
505 | /* USB host 2 */ | |
506 | static u64 usbh2_dmamask = 0xffffffffUL; | |
507 | ||
508 | static struct resource mxc_usbh2_resources[] = { | |
509 | { | |
510 | .start = OTG_BASE_ADDR + 0x400, | |
511 | .end = OTG_BASE_ADDR + 0x5ff, | |
512 | .flags = IORESOURCE_MEM, | |
513 | }, { | |
514 | .start = MXC_INT_USB2, | |
515 | .end = MXC_INT_USB2, | |
516 | .flags = IORESOURCE_IRQ, | |
517 | }, | |
518 | }; | |
519 | ||
520 | struct platform_device mxc_usbh2 = { | |
521 | .name = "mxc-ehci", | |
522 | .id = 2, | |
523 | .dev = { | |
524 | .coherent_dma_mask = 0xffffffff, | |
525 | .dma_mask = &usbh2_dmamask, | |
526 | }, | |
527 | .resource = mxc_usbh2_resources, | |
528 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | |
529 | }; | |
530 | ||
531 | ||
fc80a5e3 JB |
532 | /* GPIO port description */ |
533 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
bf50bcc2 | 534 | { |
fc80a5e3 JB |
535 | .chip.label = "gpio-0", |
536 | .irq = MXC_INT_GPIO, | |
058b7a6f | 537 | .base = IO_ADDRESS(GPIO_BASE_ADDR), |
9d631b83 | 538 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
bf50bcc2 | 539 | }, { |
fc80a5e3 | 540 | .chip.label = "gpio-1", |
058b7a6f | 541 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), |
9d631b83 | 542 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
bf50bcc2 | 543 | }, { |
fc80a5e3 | 544 | .chip.label = "gpio-2", |
058b7a6f | 545 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), |
9d631b83 | 546 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
bf50bcc2 | 547 | }, { |
fc80a5e3 | 548 | .chip.label = "gpio-3", |
058b7a6f | 549 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), |
9d631b83 | 550 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, |
bf50bcc2 | 551 | }, { |
fc80a5e3 | 552 | .chip.label = "gpio-4", |
058b7a6f | 553 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), |
9d631b83 | 554 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, |
bf50bcc2 | 555 | }, { |
fc80a5e3 | 556 | .chip.label = "gpio-5", |
058b7a6f | 557 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), |
9d631b83 | 558 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |
fc80a5e3 JB |
559 | } |
560 | }; | |
561 | ||
562 | int __init mxc_register_gpios(void) | |
563 | { | |
564 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
565 | } |