[deliverable/linux.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * SPI master controller
 *
 * - i.MX1: 2 channel (slighly different register setting)
 * - i.MX21: 2 channel
 * - i.MX27: 3 channel
 */
#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)					\
	static struct resource mxc_spi_resources ## n[] = {			\
		{								\
			.start = baseaddr,					\
			.end = baseaddr + SZ_4K - 1,				\
			.flags = IORESOURCE_MEM,				\
		}, {								\
			.start = irq,						\
			.end = irq,						\
			.flags = IORESOURCE_IRQ,				\
		},								\
	};									\
										\
	struct platform_device mxc_spi_device ## n = {				\
		.name = "spi_imx",						\
		.id = n,							\
		.num_resources = ARRAY_SIZE(mxc_spi_resources ## n),		\
		.resource = mxc_spi_resources ## n,				\
	}

DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
#endif

/*
 * General Purpose Timer
 * - i.MX21: 3 timers
 * - i.MX27: 6 timers
 */
#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq)				\
	static struct resource timer ## n ##_resources[] = {		\
		{							\
			.start = baseaddr,				\
			.end = baseaddr + SZ_4K - 1,			\
			.flags = IORESOURCE_MEM,			\
		}, {							\
			.start = irq,					\
			.end = irq,					\
			.flags = IORESOURCE_IRQ,			\
		}							\
	};								\
									\
	struct platform_device mxc_gpt ## n = {				\
		.name = "imx_gpt",					\
		.id = n,						\
		.num_resources = ARRAY_SIZE(timer ## n ## _resources),	\
		.resource = timer ## n ## _resources,			\
	}

/* We use gpt1 as system timer, so do not add a device for this one */
DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
#endif

/*
 * Watchdog:
 * - i.MX1
 * - i.MX21
 * - i.MX27
 */
static struct resource mxc_wdt_resources[] = {
	{
		.start	= WDOG_BASE_ADDR,
		.end	= WDOG_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "mxc_wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= NFC_BASE_ADDR,
		.end	= NFC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = LCDC_BASE_ADDR,
		.end   = LCDC_BASE_ADDR + 0xFFF,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_LCDC,
		.end   = MXC_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = 0xFFFFFFFF,
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start	= FEC_BASE_ADDR,
		.end	= FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource mxc_i2c_1_resources[] = {
	{
		.start	= I2C_BASE_ADDR,
		.end	= I2C_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C,
		.end	= MXC_INT_I2C,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	.resource = mxc_i2c_1_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = {
	{
		.start	= I2C2_BASE_ADDR,
		.end	= I2C2_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C2,
		.end	= MXC_INT_I2C2,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	.resource = mxc_i2c_2_resources,
};
#endif

static struct resource mxc_pwm_resources[] = {
	{
		.start	= PWM_BASE_ADDR,
		.end	= PWM_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_PWM,
		.end     = MXC_INT_PWM,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources,
};

/*
 * Resource definition for the MXC SDHC
 */
static struct resource mxc_sdhc1_resources[] = {
	{
		.start = SDHC1_BASE_ADDR,
		.end   = SDHC1_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC1,
		.end   = MXC_INT_SDHC1,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC1,
		.end    = DMA_REQ_SDHC1,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc1_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device0 = {
       .name           = "mxc-mmc",
       .id             = 0,
       .dev            = {
               .dma_mask = &mxc_sdhc1_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
       .resource       = mxc_sdhc1_resources,
};

static struct resource mxc_sdhc2_resources[] = {
	{
		.start = SDHC2_BASE_ADDR,
		.end   = SDHC2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC2,
		.end   = MXC_INT_SDHC2,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC2,
		.end    = DMA_REQ_SDHC2,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc2_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device1 = {
       .name           = "mxc-mmc",
       .id             = 1,
       .dev            = {
               .dma_mask = &mxc_sdhc2_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
       .resource       = mxc_sdhc2_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
	{
		.start	= OTG_BASE_ADDR,
		.end	= OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = 0xffffffffUL;

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= 0xffffffffUL,
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = 0xffffffffUL;

static struct resource mxc_usbh1_resources[] = {
	{
		.start = OTG_BASE_ADDR + 0x200,
		.end = OTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB1,
		.end = MXC_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = 0xffffffffUL;

static struct resource mxc_usbh2_resources[] = {
	{
		.start = OTG_BASE_ADDR + 0x400,
		.end = OTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB2,
		.end = MXC_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif

static struct resource imx_ssi_resources0[] = {
	{
		.start	= SSI1_BASE_ADDR,
		.end	= SSI1_BASE_ADDR + 0x6F,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_SSI1,
		.end	= MXC_INT_SSI1,
		.flags	= IORESOURCE_IRQ,
	}, {
		.name	= "tx0",
		.start	= DMA_REQ_SSI1_TX0,
		.end	= DMA_REQ_SSI1_TX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx0",
		.start	= DMA_REQ_SSI1_RX0,
		.end	= DMA_REQ_SSI1_RX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "tx1",
		.start	= DMA_REQ_SSI1_TX1,
		.end	= DMA_REQ_SSI1_TX1,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx1",
		.start	= DMA_REQ_SSI1_RX1,
		.end	= DMA_REQ_SSI1_RX1,
		.flags	= IORESOURCE_DMA,
	},
};

static struct resource imx_ssi_resources1[] = {
	{
		.start	= SSI2_BASE_ADDR,
		.end	= SSI2_BASE_ADDR + 0x6F,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_SSI2,
		.end	= MXC_INT_SSI2,
		.flags	= IORESOURCE_IRQ,
	}, {
		.name	= "tx0",
		.start	= DMA_REQ_SSI2_TX0,
		.end	= DMA_REQ_SSI2_TX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx0",
		.start	= DMA_REQ_SSI2_RX0,
		.end	= DMA_REQ_SSI2_RX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "tx1",
		.start	= DMA_REQ_SSI2_TX1,
		.end	= DMA_REQ_SSI2_TX1,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx1",
		.start	= DMA_REQ_SSI2_RX1,
		.end	= DMA_REQ_SSI2_RX1,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device imx_ssi_device0 = {
	.name = "imx-ssi",
	.id = 0,
	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
	.resource = imx_ssi_resources0,
};

struct platform_device imx_ssi_device1 = {
	.name = "imx-ssi",
	.id = 1,
	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
	.resource = imx_ssi_resources1,
};

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	{
		.chip.label = "gpio-0",
		.irq = MXC_INT_GPIO,
		.base = IO_ADDRESS(GPIO_BASE_ADDR),
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	}, {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	}, {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}, {
		.chip.label = "gpio-3",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
	}, {
		.chip.label = "gpio-4",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
	}, {
		.chip.label = "gpio-5",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
	34
80b02c17	35	#include <mach/irqs.h>
a09e64fb	36	#include <mach/hardware.h>
058b7a6f	37	#include <mach/common.h>
1a02be0e	38	#include <mach/mmc.h>
058b7a6f HS	39
058b7a6f HS	40	#include "devices.h"
fc80a5e3	41
f420db84 SH	42	/*
	43	* SPI master controller
	44	*
	45	* - i.MX1: 2 channel (slighly different register setting)
	46	* - i.MX21: 2 channel
	47	* - i.MX27: 3 channel
	48	*/
68c94b40 UKK	49	#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
	50	static struct resource mxc_spi_resources ## n[] = { \
	51	{ \
	52	.start = baseaddr, \
	53	.end = baseaddr + SZ_4K - 1, \
	54	.flags = IORESOURCE_MEM, \
	55	}, { \
	56	.start = irq, \
	57	.end = irq, \
	58	.flags = IORESOURCE_IRQ, \
	59	}, \
	60	}; \
	61	\
	62	struct platform_device mxc_spi_device ## n = { \
	63	.name = "spi_imx", \
	64	.id = n, \
	65	.num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
	66	.resource = mxc_spi_resources ## n, \
	67	}
f420db84	68
68c94b40 UKK	69	DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
68c94b40 UKK	70	DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
f420db84 SH	71
f420db84 SH	72	#ifdef CONFIG_MACH_MX27
68c94b40	73	DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
f420db84 SH	74	#endif
f420db84 SH	75
fc80a5e3 JB	76	/*
fc80a5e3 JB	77	* General Purpose Timer
bf50bcc2 SH	78	* - i.MX21: 3 timers
bf50bcc2 SH	79	* - i.MX27: 6 timers
fc80a5e3	80	*/
2b84a364 UKK	81	#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
	82	static struct resource timer ## n ##_resources[] = { \
	83	{ \
	84	.start = baseaddr, \
	85	.end = baseaddr + SZ_4K - 1, \
	86	.flags = IORESOURCE_MEM, \
	87	}, { \
	88	.start = irq, \
	89	.end = irq, \
	90	.flags = IORESOURCE_IRQ, \
	91	} \
	92	}; \
	93	\
	94	struct platform_device mxc_gpt ## n = { \
	95	.name = "imx_gpt", \
	96	.id = n, \
	97	.num_resources = ARRAY_SIZE(timer ## n ## _resources), \
	98	.resource = timer ## n ## _resources, \
fc80a5e3	99	}
fc80a5e3	100
2b84a364 UKK	101	/* We use gpt1 as system timer, so do not add a device for this one */
	102	DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
	103	DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
fc80a5e3 JB	104
fc80a5e3 JB	105	#ifdef CONFIG_MACH_MX27
2b84a364 UKK	106	DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
	107	DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
	108	DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
fc80a5e3 JB	109	#endif
	110
	111	/*
	112	* Watchdog:
	113	* - i.MX1
	114	* - i.MX21
	115	* - i.MX27
	116	*/
	117	static struct resource mxc_wdt_resources[] = {
	118	{
	119	.start = WDOG_BASE_ADDR,
	120	.end = WDOG_BASE_ADDR + 0x30,
	121	.flags = IORESOURCE_MEM,
	122	},
	123	};
	124
	125	struct platform_device mxc_wdt = {
	126	.name = "mxc_wdt",
	127	.id = 0,
	128	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	129	.resource = mxc_wdt_resources,
	130	};
	131
3d89baa7 SH	132	static struct resource mxc_w1_master_resources[] = {
	133	{
	134	.start = OWIRE_BASE_ADDR,
	135	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	136	.flags = IORESOURCE_MEM,
	137	},
	138	};
	139
	140	struct platform_device mxc_w1_master_device = {
	141	.name = "mxc_w1",
	142	.id = 0,
	143	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	144	.resource = mxc_w1_master_resources,
	145	};
	146
02870978 SH	147	static struct resource mxc_nand_resources[] = {
	148	{
	149	.start = NFC_BASE_ADDR,
	150	.end = NFC_BASE_ADDR + 0xfff,
bf50bcc2	151	.flags = IORESOURCE_MEM,
02870978 SH	152	}, {
	153	.start = MXC_INT_NANDFC,
	154	.end = MXC_INT_NANDFC,
bf50bcc2	155	.flags = IORESOURCE_IRQ,
02870978 SH	156	},
	157	};
	158
	159	struct platform_device mxc_nand_device = {
	160	.name = "mxc_nand",
	161	.id = 0,
	162	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	163	.resource = mxc_nand_resources,
	164	};
	165
e4813551 HS	166	/*
	167	* lcdc:
	168	* - i.MX1: the basic controller
	169	* - i.MX21: to be checked
	170	* - i.MX27: like i.MX1, with slightly variations
	171	*/
	172	static struct resource mxc_fb[] = {
	173	{
	174	.start = LCDC_BASE_ADDR,
	175	.end = LCDC_BASE_ADDR + 0xFFF,
	176	.flags = IORESOURCE_MEM,
bf50bcc2	177	}, {
e4813551 HS	178	.start = MXC_INT_LCDC,
	179	.end = MXC_INT_LCDC,
	180	.flags = IORESOURCE_IRQ,
	181	}
	182	};
	183
	184	/* mxc lcd driver */
	185	struct platform_device mxc_fb_device = {
	186	.name = "imx-fb",
	187	.id = 0,
	188	.num_resources = ARRAY_SIZE(mxc_fb),
	189	.resource = mxc_fb,
	190	.dev = {
	191	.coherent_dma_mask = 0xFFFFFFFF,
	192	},
	193	};
	194
879fea1b SH	195	#ifdef CONFIG_MACH_MX27
	196	static struct resource mxc_fec_resources[] = {
	197	{
	198	.start = FEC_BASE_ADDR,
	199	.end = FEC_BASE_ADDR + 0xfff,
bf50bcc2	200	.flags = IORESOURCE_MEM,
879fea1b SH	201	}, {
	202	.start = MXC_INT_FEC,
	203	.end = MXC_INT_FEC,
bf50bcc2	204	.flags = IORESOURCE_IRQ,
879fea1b SH	205	},
	206	};
	207
	208	struct platform_device mxc_fec_device = {
	209	.name = "fec",
	210	.id = 0,
	211	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	212	.resource = mxc_fec_resources,
	213	};
e4813551 HS	214	#endif
e4813551 HS	215
c5d4dbff	216	static struct resource mxc_i2c_1_resources[] = {
bf50bcc2	217	{
c5d4dbff SH	218	.start = I2C_BASE_ADDR,
c5d4dbff SH	219	.end = I2C_BASE_ADDR + 0x0fff,
bf50bcc2 SH	220	.flags = IORESOURCE_MEM,
bf50bcc2 SH	221	}, {
c5d4dbff SH	222	.start = MXC_INT_I2C,
c5d4dbff SH	223	.end = MXC_INT_I2C,
bf50bcc2	224	.flags = IORESOURCE_IRQ,
c5d4dbff SH	225	}
	226	};
	227
	228	struct platform_device mxc_i2c_device0 = {
	229	.name = "imx-i2c",
	230	.id = 0,
	231	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
bf50bcc2	232	.resource = mxc_i2c_1_resources,
c5d4dbff SH	233	};
	234
	235	#ifdef CONFIG_MACH_MX27
	236	static struct resource mxc_i2c_2_resources[] = {
bf50bcc2	237	{
c5d4dbff SH	238	.start = I2C2_BASE_ADDR,
c5d4dbff SH	239	.end = I2C2_BASE_ADDR + 0x0fff,
bf50bcc2 SH	240	.flags = IORESOURCE_MEM,
bf50bcc2 SH	241	}, {
c5d4dbff SH	242	.start = MXC_INT_I2C2,
c5d4dbff SH	243	.end = MXC_INT_I2C2,
bf50bcc2	244	.flags = IORESOURCE_IRQ,
c5d4dbff SH	245	}
	246	};
	247
	248	struct platform_device mxc_i2c_device1 = {
	249	.name = "imx-i2c",
	250	.id = 1,
	251	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
bf50bcc2	252	.resource = mxc_i2c_2_resources,
c5d4dbff SH	253	};
	254	#endif
	255
824b16e6	256	static struct resource mxc_pwm_resources[] = {
bf50bcc2	257	{
824b16e6 SH	258	.start = PWM_BASE_ADDR,
824b16e6 SH	259	.end = PWM_BASE_ADDR + 0x0fff,
bf50bcc2 SH	260	.flags = IORESOURCE_MEM,
bf50bcc2 SH	261	}, {
824b16e6 SH	262	.start = MXC_INT_PWM,
	263	.end = MXC_INT_PWM,
	264	.flags = IORESOURCE_IRQ,
	265	}
	266	};
	267
	268	struct platform_device mxc_pwm_device = {
	269	.name = "mxc_pwm",
	270	.id = 0,
	271	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
bf50bcc2	272	.resource = mxc_pwm_resources,
824b16e6 SH	273	};
824b16e6 SH	274
1a02be0e SH	275	/*
	276	* Resource definition for the MXC SDHC
	277	*/
	278	static struct resource mxc_sdhc1_resources[] = {
bf50bcc2 SH	279	{
	280	.start = SDHC1_BASE_ADDR,
	281	.end = SDHC1_BASE_ADDR + SZ_4K - 1,
	282	.flags = IORESOURCE_MEM,
	283	}, {
	284	.start = MXC_INT_SDHC1,
	285	.end = MXC_INT_SDHC1,
	286	.flags = IORESOURCE_IRQ,
	287	}, {
	288	.start = DMA_REQ_SDHC1,
	289	.end = DMA_REQ_SDHC1,
	290	.flags = IORESOURCE_DMA,
	291	},
1a02be0e SH	292	};
	293
	294	static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
	295
	296	struct platform_device mxc_sdhc_device0 = {
	297	.name = "mxc-mmc",
	298	.id = 0,
	299	.dev = {
	300	.dma_mask = &mxc_sdhc1_dmamask,
	301	.coherent_dma_mask = 0xffffffff,
	302	},
	303	.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
	304	.resource = mxc_sdhc1_resources,
	305	};
	306
	307	static struct resource mxc_sdhc2_resources[] = {
bf50bcc2 SH	308	{
	309	.start = SDHC2_BASE_ADDR,
	310	.end = SDHC2_BASE_ADDR + SZ_4K - 1,
	311	.flags = IORESOURCE_MEM,
	312	}, {
	313	.start = MXC_INT_SDHC2,
	314	.end = MXC_INT_SDHC2,
	315	.flags = IORESOURCE_IRQ,
	316	}, {
	317	.start = DMA_REQ_SDHC2,
	318	.end = DMA_REQ_SDHC2,
	319	.flags = IORESOURCE_DMA,
	320	},
1a02be0e SH	321	};
	322
	323	static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
	324
	325	struct platform_device mxc_sdhc_device1 = {
	326	.name = "mxc-mmc",
	327	.id = 1,
	328	.dev = {
	329	.dma_mask = &mxc_sdhc2_dmamask,
	330	.coherent_dma_mask = 0xffffffff,
	331	},
	332	.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
	333	.resource = mxc_sdhc2_resources,
	334	};
	335
f6d2fa7d	336	#ifdef CONFIG_MACH_MX27
627fb3b9 M	337	static struct resource otg_resources[] = {
	338	{
	339	.start = OTG_BASE_ADDR,
	340	.end = OTG_BASE_ADDR + 0x1ff,
	341	.flags = IORESOURCE_MEM,
	342	}, {
	343	.start = MXC_INT_USB3,
	344	.end = MXC_INT_USB3,
	345	.flags = IORESOURCE_IRQ,
	346	},
	347	};
	348
	349	static u64 otg_dmamask = 0xffffffffUL;
	350
	351	/* OTG gadget device */
	352	struct platform_device mxc_otg_udc_device = {
	353	.name = "fsl-usb2-udc",
	354	.id = -1,
	355	.dev = {
	356	.dma_mask = &otg_dmamask,
	357	.coherent_dma_mask = 0xffffffffUL,
	358	},
	359	.resource = otg_resources,
	360	.num_resources = ARRAY_SIZE(otg_resources),
	361	};
	362
	363	/* OTG host */
	364	struct platform_device mxc_otg_host = {
	365	.name = "mxc-ehci",
	366	.id = 0,
	367	.dev = {
	368	.coherent_dma_mask = 0xffffffff,
	369	.dma_mask = &otg_dmamask,
	370	},
	371	.resource = otg_resources,
	372	.num_resources = ARRAY_SIZE(otg_resources),
	373	};
	374
	375	/* USB host 1 */
	376
	377	static u64 usbh1_dmamask = 0xffffffffUL;
	378
	379	static struct resource mxc_usbh1_resources[] = {
	380	{
	381	.start = OTG_BASE_ADDR + 0x200,
	382	.end = OTG_BASE_ADDR + 0x3ff,
	383	.flags = IORESOURCE_MEM,
	384	}, {
	385	.start = MXC_INT_USB1,
	386	.end = MXC_INT_USB1,
	387	.flags = IORESOURCE_IRQ,
	388	},
	389	};
	390
	391	struct platform_device mxc_usbh1 = {
	392	.name = "mxc-ehci",
	393	.id = 1,
	394	.dev = {
	395	.coherent_dma_mask = 0xffffffff,
	396	.dma_mask = &usbh1_dmamask,
	397	},
	398	.resource = mxc_usbh1_resources,
	399	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	400	};
401
402	/* USB host 2 */
403	static u64 usbh2_dmamask = 0xffffffffUL;
404
405	static struct resource mxc_usbh2_resources[] = {
406	{
407	.start = OTG_BASE_ADDR + 0x400,
408	.end = OTG_BASE_ADDR + 0x5ff,
409	.flags = IORESOURCE_MEM,
410	}, {
411	.start = MXC_INT_USB2,
412	.end = MXC_INT_USB2,
413	.flags = IORESOURCE_IRQ,
414	},
415	};
416
417	struct platform_device mxc_usbh2 = {
418	.name = "mxc-ehci",
419	.id = 2,
420	.dev = {
421	.coherent_dma_mask = 0xffffffff,
422	.dma_mask = &usbh2_dmamask,
423	},
424	.resource = mxc_usbh2_resources,
425	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
426	};
f6d2fa7d	427	#endif
627fb3b9	428
23291df4 SH	429	static struct resource imx_ssi_resources0[] = {
	430	{
	431	.start = SSI1_BASE_ADDR,
	432	.end = SSI1_BASE_ADDR + 0x6F,
	433	.flags = IORESOURCE_MEM,
	434	}, {
	435	.start = MXC_INT_SSI1,
	436	.end = MXC_INT_SSI1,
	437	.flags = IORESOURCE_IRQ,
	438	}, {
	439	.name = "tx0",
	440	.start = DMA_REQ_SSI1_TX0,
	441	.end = DMA_REQ_SSI1_TX0,
	442	.flags = IORESOURCE_DMA,
	443	}, {
	444	.name = "rx0",
	445	.start = DMA_REQ_SSI1_RX0,
	446	.end = DMA_REQ_SSI1_RX0,
	447	.flags = IORESOURCE_DMA,
	448	}, {
	449	.name = "tx1",
	450	.start = DMA_REQ_SSI1_TX1,
	451	.end = DMA_REQ_SSI1_TX1,
	452	.flags = IORESOURCE_DMA,
	453	}, {
	454	.name = "rx1",
	455	.start = DMA_REQ_SSI1_RX1,
	456	.end = DMA_REQ_SSI1_RX1,
	457	.flags = IORESOURCE_DMA,
	458	},
	459	};
	460
	461	static struct resource imx_ssi_resources1[] = {
	462	{
	463	.start = SSI2_BASE_ADDR,
	464	.end = SSI2_BASE_ADDR + 0x6F,
	465	.flags = IORESOURCE_MEM,
	466	}, {
	467	.start = MXC_INT_SSI2,
	468	.end = MXC_INT_SSI2,
	469	.flags = IORESOURCE_IRQ,
	470	}, {
	471	.name = "tx0",
	472	.start = DMA_REQ_SSI2_TX0,
	473	.end = DMA_REQ_SSI2_TX0,
	474	.flags = IORESOURCE_DMA,
	475	}, {
	476	.name = "rx0",
	477	.start = DMA_REQ_SSI2_RX0,
	478	.end = DMA_REQ_SSI2_RX0,
	479	.flags = IORESOURCE_DMA,
	480	}, {
	481	.name = "tx1",
	482	.start = DMA_REQ_SSI2_TX1,
	483	.end = DMA_REQ_SSI2_TX1,
	484	.flags = IORESOURCE_DMA,
	485	}, {
	486	.name = "rx1",
	487	.start = DMA_REQ_SSI2_RX1,
	488	.end = DMA_REQ_SSI2_RX1,
	489	.flags = IORESOURCE_DMA,
	490	},
	491	};
	492
493	struct platform_device imx_ssi_device0 = {
494	.name = "imx-ssi",
495	.id = 0,
496	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
497	.resource = imx_ssi_resources0,
498	};
499
500	struct platform_device imx_ssi_device1 = {
501	.name = "imx-ssi",
502	.id = 1,
503	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
504	.resource = imx_ssi_resources1,
505	};
506
fc80a5e3 JB	507	/* GPIO port description */
fc80a5e3 JB	508	static struct mxc_gpio_port imx_gpio_ports[] = {
bf50bcc2	509	{
fc80a5e3 JB	510	.chip.label = "gpio-0",
fc80a5e3 JB	511	.irq = MXC_INT_GPIO,
058b7a6f	512	.base = IO_ADDRESS(GPIO_BASE_ADDR),
9d631b83	513	.virtual_irq_start = MXC_GPIO_IRQ_START,
bf50bcc2	514	}, {
fc80a5e3	515	.chip.label = "gpio-1",
058b7a6f	516	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
9d631b83	517	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
bf50bcc2	518	}, {
fc80a5e3	519	.chip.label = "gpio-2",
058b7a6f	520	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
9d631b83	521	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
bf50bcc2	522	}, {
fc80a5e3	523	.chip.label = "gpio-3",
058b7a6f	524	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
9d631b83	525	.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
bf50bcc2	526	}, {
fc80a5e3	527	.chip.label = "gpio-4",
058b7a6f	528	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
9d631b83	529	.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
bf50bcc2	530	}, {
fc80a5e3	531	.chip.label = "gpio-5",
058b7a6f	532	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
9d631b83	533	.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
fc80a5e3 JB	534	}
	535	};
	536
	537	int __init mxc_register_gpios(void)
	538	{
	539	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	540	}