[deliverable/linux.git] / arch / arm / mach-mx2 / devices.c

/*
 * Author: MontaVista Software, Inc.
 *       <source@mvista.com>
 *
 * Based on the OMAP devices.c
 *
 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>

#include <mach/irqs.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/mmc.h>

#include "devices.h"

/*
 * SPI master controller
 *
 * - i.MX1: 2 channel (slighly different register setting)
 * - i.MX21: 2 channel
 * - i.MX27: 3 channel
 */
#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)					\
	static struct resource mxc_spi_resources ## n[] = {			\
		{								\
			.start = baseaddr,					\
			.end = baseaddr + SZ_4K - 1,				\
			.flags = IORESOURCE_MEM,				\
		}, {								\
			.start = irq,						\
			.end = irq,						\
			.flags = IORESOURCE_IRQ,				\
		},								\
	};									\
										\
	struct platform_device mxc_spi_device ## n = {				\
		.name = "spi_imx",						\
		.id = n,							\
		.num_resources = ARRAY_SIZE(mxc_spi_resources ## n),		\
		.resource = mxc_spi_resources ## n,				\
	}

DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);

#ifdef CONFIG_MACH_MX27
DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
#endif

/*
 * General Purpose Timer
 * - i.MX21: 3 timers
 * - i.MX27: 6 timers
 */

/* We use gpt0 as system timer, so do not add a device for this one */

static struct resource timer1_resources[] = {
	{
		.start	= GPT2_BASE_ADDR,
		.end	= GPT2_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT2,
		.end     = MXC_INT_GPT2,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt1 = {
	.name = "imx_gpt",
	.id = 1,
	.num_resources = ARRAY_SIZE(timer1_resources),
	.resource = timer1_resources,
};

static struct resource timer2_resources[] = {
	{
		.start	= GPT3_BASE_ADDR,
		.end	= GPT3_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT3,
		.end     = MXC_INT_GPT3,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt2 = {
	.name = "imx_gpt",
	.id = 2,
	.num_resources = ARRAY_SIZE(timer2_resources),
	.resource = timer2_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource timer3_resources[] = {
	{
		.start	= GPT4_BASE_ADDR,
		.end	= GPT4_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT4,
		.end     = MXC_INT_GPT4,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt3 = {
	.name = "imx_gpt",
	.id = 3,
	.num_resources = ARRAY_SIZE(timer3_resources),
	.resource = timer3_resources,
};

static struct resource timer4_resources[] = {
	{
		.start	= GPT5_BASE_ADDR,
		.end	= GPT5_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT5,
		.end     = MXC_INT_GPT5,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt4 = {
	.name = "imx_gpt",
	.id = 4,
	.num_resources = ARRAY_SIZE(timer4_resources),
	.resource = timer4_resources,
};

static struct resource timer5_resources[] = {
	{
		.start	= GPT6_BASE_ADDR,
		.end	= GPT6_BASE_ADDR + 0x17,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_GPT6,
		.end     = MXC_INT_GPT6,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_gpt5 = {
	.name = "imx_gpt",
	.id = 5,
	.num_resources = ARRAY_SIZE(timer5_resources),
	.resource = timer5_resources,
};
#endif

/*
 * Watchdog:
 * - i.MX1
 * - i.MX21
 * - i.MX27
 */
static struct resource mxc_wdt_resources[] = {
	{
		.start	= WDOG_BASE_ADDR,
		.end	= WDOG_BASE_ADDR + 0x30,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mxc_wdt = {
	.name = "mxc_wdt",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	.resource = mxc_wdt_resources,
};

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= NFC_BASE_ADDR,
		.end	= NFC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

/*
 * lcdc:
 * - i.MX1: the basic controller
 * - i.MX21: to be checked
 * - i.MX27: like i.MX1, with slightly variations
 */
static struct resource mxc_fb[] = {
	{
		.start = LCDC_BASE_ADDR,
		.end   = LCDC_BASE_ADDR + 0xFFF,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_LCDC,
		.end   = MXC_INT_LCDC,
		.flags = IORESOURCE_IRQ,
	}
};

/* mxc lcd driver */
struct platform_device mxc_fb_device = {
	.name = "imx-fb",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fb),
	.resource = mxc_fb,
	.dev = {
		.coherent_dma_mask = 0xFFFFFFFF,
	},
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
	{
		.start	= FEC_BASE_ADDR,
		.end	= FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource mxc_i2c_1_resources[] = {
	{
		.start	= I2C_BASE_ADDR,
		.end	= I2C_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C,
		.end	= MXC_INT_I2C,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
	.resource = mxc_i2c_1_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource mxc_i2c_2_resources[] = {
	{
		.start	= I2C2_BASE_ADDR,
		.end	= I2C2_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_I2C2,
		.end	= MXC_INT_I2C2,
		.flags	= IORESOURCE_IRQ,
	}
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
	.resource = mxc_i2c_2_resources,
};
#endif

static struct resource mxc_pwm_resources[] = {
	{
		.start	= PWM_BASE_ADDR,
		.end	= PWM_BASE_ADDR + 0x0fff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start   = MXC_INT_PWM,
		.end     = MXC_INT_PWM,
		.flags   = IORESOURCE_IRQ,
	}
};

struct platform_device mxc_pwm_device = {
	.name = "mxc_pwm",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
	.resource = mxc_pwm_resources,
};

/*
 * Resource definition for the MXC SDHC
 */
static struct resource mxc_sdhc1_resources[] = {
	{
		.start = SDHC1_BASE_ADDR,
		.end   = SDHC1_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC1,
		.end   = MXC_INT_SDHC1,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC1,
		.end    = DMA_REQ_SDHC1,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc1_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device0 = {
       .name           = "mxc-mmc",
       .id             = 0,
       .dev            = {
               .dma_mask = &mxc_sdhc1_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc1_resources),
       .resource       = mxc_sdhc1_resources,
};

static struct resource mxc_sdhc2_resources[] = {
	{
		.start = SDHC2_BASE_ADDR,
		.end   = SDHC2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_SDHC2,
		.end   = MXC_INT_SDHC2,
		.flags = IORESOURCE_IRQ,
	}, {
		.start  = DMA_REQ_SDHC2,
		.end    = DMA_REQ_SDHC2,
		.flags  = IORESOURCE_DMA,
	},
};

static u64 mxc_sdhc2_dmamask = 0xffffffffUL;

struct platform_device mxc_sdhc_device1 = {
       .name           = "mxc-mmc",
       .id             = 1,
       .dev            = {
               .dma_mask = &mxc_sdhc2_dmamask,
               .coherent_dma_mask = 0xffffffff,
       },
       .num_resources  = ARRAY_SIZE(mxc_sdhc2_resources),
       .resource       = mxc_sdhc2_resources,
};

#ifdef CONFIG_MACH_MX27
static struct resource otg_resources[] = {
	{
		.start	= OTG_BASE_ADDR,
		.end	= OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = 0xffffffffUL;

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= 0xffffffffUL,
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = 0xffffffffUL;

static struct resource mxc_usbh1_resources[] = {
	{
		.start = OTG_BASE_ADDR + 0x200,
		.end = OTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB1,
		.end = MXC_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = 0xffffffffUL;

static struct resource mxc_usbh2_resources[] = {
	{
		.start = OTG_BASE_ADDR + 0x400,
		.end = OTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB2,
		.end = MXC_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};
#endif

static struct resource imx_ssi_resources0[] = {
	{
		.start	= SSI1_BASE_ADDR,
		.end	= SSI1_BASE_ADDR + 0x6F,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_SSI1,
		.end	= MXC_INT_SSI1,
		.flags	= IORESOURCE_IRQ,
	}, {
		.name	= "tx0",
		.start	= DMA_REQ_SSI1_TX0,
		.end	= DMA_REQ_SSI1_TX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx0",
		.start	= DMA_REQ_SSI1_RX0,
		.end	= DMA_REQ_SSI1_RX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "tx1",
		.start	= DMA_REQ_SSI1_TX1,
		.end	= DMA_REQ_SSI1_TX1,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx1",
		.start	= DMA_REQ_SSI1_RX1,
		.end	= DMA_REQ_SSI1_RX1,
		.flags	= IORESOURCE_DMA,
	},
};

static struct resource imx_ssi_resources1[] = {
	{
		.start	= SSI2_BASE_ADDR,
		.end	= SSI2_BASE_ADDR + 0x6F,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_SSI2,
		.end	= MXC_INT_SSI2,
		.flags	= IORESOURCE_IRQ,
	}, {
		.name	= "tx0",
		.start	= DMA_REQ_SSI2_TX0,
		.end	= DMA_REQ_SSI2_TX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx0",
		.start	= DMA_REQ_SSI2_RX0,
		.end	= DMA_REQ_SSI2_RX0,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "tx1",
		.start	= DMA_REQ_SSI2_TX1,
		.end	= DMA_REQ_SSI2_TX1,
		.flags	= IORESOURCE_DMA,
	}, {
		.name	= "rx1",
		.start	= DMA_REQ_SSI2_RX1,
		.end	= DMA_REQ_SSI2_RX1,
		.flags	= IORESOURCE_DMA,
	},
};

struct platform_device imx_ssi_device0 = {
	.name = "imx-ssi",
	.id = 0,
	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
	.resource = imx_ssi_resources0,
};

struct platform_device imx_ssi_device1 = {
	.name = "imx-ssi",
	.id = 1,
	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
	.resource = imx_ssi_resources1,
};

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	{
		.chip.label = "gpio-0",
		.irq = MXC_INT_GPIO,
		.base = IO_ADDRESS(GPIO_BASE_ADDR),
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	}, {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	}, {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}, {
		.chip.label = "gpio-3",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
	}, {
		.chip.label = "gpio-4",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
	}, {
		.chip.label = "gpio-5",
		.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
		.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}
Commit	Line	Data
fc80a5e3 JB	1	/*
	2	* Author: MontaVista Software, Inc.
	3	* <source@mvista.com>
	4	*
	5	* Based on the OMAP devices.c
	6	*
	7	* 2005 (c) MontaVista Software, Inc. This file is licensed under the
	8	* terms of the GNU General Public License version 2. This program is
	9	* licensed "as is" without any warranty of any kind, whether express
	10	* or implied.
	11	*
	12	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	13	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version 2
	18	* of the License, or (at your option) any later version.
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	27	* MA 02110-1301, USA.
	28	*/
	29	#include <linux/module.h>
	30	#include <linux/kernel.h>
	31	#include <linux/init.h>
	32	#include <linux/platform_device.h>
	33	#include <linux/gpio.h>
	34
80b02c17	35	#include <mach/irqs.h>
a09e64fb	36	#include <mach/hardware.h>
058b7a6f	37	#include <mach/common.h>
1a02be0e	38	#include <mach/mmc.h>
058b7a6f HS	39
058b7a6f HS	40	#include "devices.h"
fc80a5e3	41
f420db84 SH	42	/*
	43	* SPI master controller
	44	*
	45	* - i.MX1: 2 channel (slighly different register setting)
	46	* - i.MX21: 2 channel
	47	* - i.MX27: 3 channel
	48	*/
68c94b40 UKK	49	#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
	50	static struct resource mxc_spi_resources ## n[] = { \
	51	{ \
	52	.start = baseaddr, \
	53	.end = baseaddr + SZ_4K - 1, \
	54	.flags = IORESOURCE_MEM, \
	55	}, { \
	56	.start = irq, \
	57	.end = irq, \
	58	.flags = IORESOURCE_IRQ, \
	59	}, \
	60	}; \
	61	\
	62	struct platform_device mxc_spi_device ## n = { \
	63	.name = "spi_imx", \
	64	.id = n, \
	65	.num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
	66	.resource = mxc_spi_resources ## n, \
	67	}
f420db84	68
68c94b40 UKK	69	DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
68c94b40 UKK	70	DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
f420db84 SH	71
f420db84 SH	72	#ifdef CONFIG_MACH_MX27
68c94b40	73	DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
f420db84 SH	74	#endif
f420db84 SH	75
fc80a5e3 JB	76	/*
fc80a5e3 JB	77	* General Purpose Timer
bf50bcc2 SH	78	* - i.MX21: 3 timers
bf50bcc2 SH	79	* - i.MX27: 6 timers
fc80a5e3 JB	80	*/
	81
	82	/* We use gpt0 as system timer, so do not add a device for this one */
	83
	84	static struct resource timer1_resources[] = {
bf50bcc2	85	{
fc80a5e3 JB	86	.start = GPT2_BASE_ADDR,
fc80a5e3 JB	87	.end = GPT2_BASE_ADDR + 0x17,
bf50bcc2 SH	88	.flags = IORESOURCE_MEM,
bf50bcc2 SH	89	}, {
fc80a5e3 JB	90	.start = MXC_INT_GPT2,
	91	.end = MXC_INT_GPT2,
	92	.flags = IORESOURCE_IRQ,
	93	}
	94	};
	95
	96	struct platform_device mxc_gpt1 = {
	97	.name = "imx_gpt",
	98	.id = 1,
	99	.num_resources = ARRAY_SIZE(timer1_resources),
bf50bcc2	100	.resource = timer1_resources,
fc80a5e3 JB	101	};
	102
	103	static struct resource timer2_resources[] = {
bf50bcc2	104	{
fc80a5e3 JB	105	.start = GPT3_BASE_ADDR,
fc80a5e3 JB	106	.end = GPT3_BASE_ADDR + 0x17,
bf50bcc2 SH	107	.flags = IORESOURCE_MEM,
bf50bcc2 SH	108	}, {
fc80a5e3 JB	109	.start = MXC_INT_GPT3,
	110	.end = MXC_INT_GPT3,
	111	.flags = IORESOURCE_IRQ,
	112	}
	113	};
	114
	115	struct platform_device mxc_gpt2 = {
	116	.name = "imx_gpt",
	117	.id = 2,
	118	.num_resources = ARRAY_SIZE(timer2_resources),
bf50bcc2	119	.resource = timer2_resources,
fc80a5e3 JB	120	};
	121
	122	#ifdef CONFIG_MACH_MX27
	123	static struct resource timer3_resources[] = {
bf50bcc2	124	{
fc80a5e3 JB	125	.start = GPT4_BASE_ADDR,
fc80a5e3 JB	126	.end = GPT4_BASE_ADDR + 0x17,
bf50bcc2 SH	127	.flags = IORESOURCE_MEM,
bf50bcc2 SH	128	}, {
fc80a5e3 JB	129	.start = MXC_INT_GPT4,
	130	.end = MXC_INT_GPT4,
	131	.flags = IORESOURCE_IRQ,
	132	}
	133	};
	134
	135	struct platform_device mxc_gpt3 = {
	136	.name = "imx_gpt",
	137	.id = 3,
	138	.num_resources = ARRAY_SIZE(timer3_resources),
bf50bcc2	139	.resource = timer3_resources,
fc80a5e3 JB	140	};
	141
	142	static struct resource timer4_resources[] = {
bf50bcc2	143	{
fc80a5e3 JB	144	.start = GPT5_BASE_ADDR,
fc80a5e3 JB	145	.end = GPT5_BASE_ADDR + 0x17,
bf50bcc2 SH	146	.flags = IORESOURCE_MEM,
bf50bcc2 SH	147	}, {
fc80a5e3 JB	148	.start = MXC_INT_GPT5,
	149	.end = MXC_INT_GPT5,
	150	.flags = IORESOURCE_IRQ,
	151	}
	152	};
	153
	154	struct platform_device mxc_gpt4 = {
	155	.name = "imx_gpt",
	156	.id = 4,
	157	.num_resources = ARRAY_SIZE(timer4_resources),
bf50bcc2	158	.resource = timer4_resources,
fc80a5e3 JB	159	};
	160
	161	static struct resource timer5_resources[] = {
bf50bcc2	162	{
fc80a5e3 JB	163	.start = GPT6_BASE_ADDR,
fc80a5e3 JB	164	.end = GPT6_BASE_ADDR + 0x17,
bf50bcc2 SH	165	.flags = IORESOURCE_MEM,
bf50bcc2 SH	166	}, {
fc80a5e3 JB	167	.start = MXC_INT_GPT6,
	168	.end = MXC_INT_GPT6,
	169	.flags = IORESOURCE_IRQ,
	170	}
	171	};
	172
	173	struct platform_device mxc_gpt5 = {
	174	.name = "imx_gpt",
	175	.id = 5,
	176	.num_resources = ARRAY_SIZE(timer5_resources),
bf50bcc2	177	.resource = timer5_resources,
fc80a5e3 JB	178	};
	179	#endif
	180
	181	/*
	182	* Watchdog:
	183	* - i.MX1
	184	* - i.MX21
	185	* - i.MX27
	186	*/
	187	static struct resource mxc_wdt_resources[] = {
	188	{
	189	.start = WDOG_BASE_ADDR,
	190	.end = WDOG_BASE_ADDR + 0x30,
	191	.flags = IORESOURCE_MEM,
	192	},
	193	};
	194
	195	struct platform_device mxc_wdt = {
	196	.name = "mxc_wdt",
	197	.id = 0,
	198	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
	199	.resource = mxc_wdt_resources,
	200	};
	201
3d89baa7 SH	202	static struct resource mxc_w1_master_resources[] = {
	203	{
	204	.start = OWIRE_BASE_ADDR,
	205	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	206	.flags = IORESOURCE_MEM,
	207	},
	208	};
	209
	210	struct platform_device mxc_w1_master_device = {
	211	.name = "mxc_w1",
	212	.id = 0,
	213	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	214	.resource = mxc_w1_master_resources,
	215	};
	216
02870978 SH	217	static struct resource mxc_nand_resources[] = {
	218	{
	219	.start = NFC_BASE_ADDR,
	220	.end = NFC_BASE_ADDR + 0xfff,
bf50bcc2	221	.flags = IORESOURCE_MEM,
02870978 SH	222	}, {
	223	.start = MXC_INT_NANDFC,
	224	.end = MXC_INT_NANDFC,
bf50bcc2	225	.flags = IORESOURCE_IRQ,
02870978 SH	226	},
	227	};
	228
	229	struct platform_device mxc_nand_device = {
	230	.name = "mxc_nand",
	231	.id = 0,
	232	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	233	.resource = mxc_nand_resources,
	234	};
	235
e4813551 HS	236	/*
	237	* lcdc:
	238	* - i.MX1: the basic controller
	239	* - i.MX21: to be checked
	240	* - i.MX27: like i.MX1, with slightly variations
	241	*/
	242	static struct resource mxc_fb[] = {
	243	{
	244	.start = LCDC_BASE_ADDR,
	245	.end = LCDC_BASE_ADDR + 0xFFF,
	246	.flags = IORESOURCE_MEM,
bf50bcc2	247	}, {
e4813551 HS	248	.start = MXC_INT_LCDC,
	249	.end = MXC_INT_LCDC,
	250	.flags = IORESOURCE_IRQ,
	251	}
	252	};
	253
	254	/* mxc lcd driver */
	255	struct platform_device mxc_fb_device = {
	256	.name = "imx-fb",
	257	.id = 0,
	258	.num_resources = ARRAY_SIZE(mxc_fb),
	259	.resource = mxc_fb,
	260	.dev = {
	261	.coherent_dma_mask = 0xFFFFFFFF,
	262	},
	263	};
	264
879fea1b SH	265	#ifdef CONFIG_MACH_MX27
	266	static struct resource mxc_fec_resources[] = {
	267	{
	268	.start = FEC_BASE_ADDR,
	269	.end = FEC_BASE_ADDR + 0xfff,
bf50bcc2	270	.flags = IORESOURCE_MEM,
879fea1b SH	271	}, {
	272	.start = MXC_INT_FEC,
	273	.end = MXC_INT_FEC,
bf50bcc2	274	.flags = IORESOURCE_IRQ,
879fea1b SH	275	},
	276	};
	277
	278	struct platform_device mxc_fec_device = {
	279	.name = "fec",
	280	.id = 0,
	281	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	282	.resource = mxc_fec_resources,
	283	};
e4813551 HS	284	#endif
e4813551 HS	285
c5d4dbff	286	static struct resource mxc_i2c_1_resources[] = {
bf50bcc2	287	{
c5d4dbff SH	288	.start = I2C_BASE_ADDR,
c5d4dbff SH	289	.end = I2C_BASE_ADDR + 0x0fff,
bf50bcc2 SH	290	.flags = IORESOURCE_MEM,
bf50bcc2 SH	291	}, {
c5d4dbff SH	292	.start = MXC_INT_I2C,
c5d4dbff SH	293	.end = MXC_INT_I2C,
bf50bcc2	294	.flags = IORESOURCE_IRQ,
c5d4dbff SH	295	}
	296	};
	297
	298	struct platform_device mxc_i2c_device0 = {
	299	.name = "imx-i2c",
	300	.id = 0,
	301	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
bf50bcc2	302	.resource = mxc_i2c_1_resources,
c5d4dbff SH	303	};
	304
	305	#ifdef CONFIG_MACH_MX27
	306	static struct resource mxc_i2c_2_resources[] = {
bf50bcc2	307	{
c5d4dbff SH	308	.start = I2C2_BASE_ADDR,
c5d4dbff SH	309	.end = I2C2_BASE_ADDR + 0x0fff,
bf50bcc2 SH	310	.flags = IORESOURCE_MEM,
bf50bcc2 SH	311	}, {
c5d4dbff SH	312	.start = MXC_INT_I2C2,
c5d4dbff SH	313	.end = MXC_INT_I2C2,
bf50bcc2	314	.flags = IORESOURCE_IRQ,
c5d4dbff SH	315	}
	316	};
	317
	318	struct platform_device mxc_i2c_device1 = {
	319	.name = "imx-i2c",
	320	.id = 1,
	321	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
bf50bcc2	322	.resource = mxc_i2c_2_resources,
c5d4dbff SH	323	};
	324	#endif
	325
824b16e6	326	static struct resource mxc_pwm_resources[] = {
bf50bcc2	327	{
824b16e6 SH	328	.start = PWM_BASE_ADDR,
824b16e6 SH	329	.end = PWM_BASE_ADDR + 0x0fff,
bf50bcc2 SH	330	.flags = IORESOURCE_MEM,
bf50bcc2 SH	331	}, {
824b16e6 SH	332	.start = MXC_INT_PWM,
	333	.end = MXC_INT_PWM,
	334	.flags = IORESOURCE_IRQ,
	335	}
	336	};
	337
	338	struct platform_device mxc_pwm_device = {
	339	.name = "mxc_pwm",
	340	.id = 0,
	341	.num_resources = ARRAY_SIZE(mxc_pwm_resources),
bf50bcc2	342	.resource = mxc_pwm_resources,
824b16e6 SH	343	};
824b16e6 SH	344
1a02be0e SH	345	/*
	346	* Resource definition for the MXC SDHC
	347	*/
	348	static struct resource mxc_sdhc1_resources[] = {
bf50bcc2 SH	349	{
	350	.start = SDHC1_BASE_ADDR,
	351	.end = SDHC1_BASE_ADDR + SZ_4K - 1,
	352	.flags = IORESOURCE_MEM,
	353	}, {
	354	.start = MXC_INT_SDHC1,
	355	.end = MXC_INT_SDHC1,
	356	.flags = IORESOURCE_IRQ,
	357	}, {
	358	.start = DMA_REQ_SDHC1,
	359	.end = DMA_REQ_SDHC1,
	360	.flags = IORESOURCE_DMA,
	361	},
1a02be0e SH	362	};
	363
	364	static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
	365
	366	struct platform_device mxc_sdhc_device0 = {
	367	.name = "mxc-mmc",
	368	.id = 0,
	369	.dev = {
	370	.dma_mask = &mxc_sdhc1_dmamask,
	371	.coherent_dma_mask = 0xffffffff,
	372	},
	373	.num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
	374	.resource = mxc_sdhc1_resources,
	375	};
	376
	377	static struct resource mxc_sdhc2_resources[] = {
bf50bcc2 SH	378	{
	379	.start = SDHC2_BASE_ADDR,
	380	.end = SDHC2_BASE_ADDR + SZ_4K - 1,
	381	.flags = IORESOURCE_MEM,
	382	}, {
	383	.start = MXC_INT_SDHC2,
	384	.end = MXC_INT_SDHC2,
	385	.flags = IORESOURCE_IRQ,
	386	}, {
	387	.start = DMA_REQ_SDHC2,
	388	.end = DMA_REQ_SDHC2,
	389	.flags = IORESOURCE_DMA,
	390	},
1a02be0e SH	391	};
	392
	393	static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
	394
	395	struct platform_device mxc_sdhc_device1 = {
	396	.name = "mxc-mmc",
	397	.id = 1,
	398	.dev = {
	399	.dma_mask = &mxc_sdhc2_dmamask,
	400	.coherent_dma_mask = 0xffffffff,
	401	},
	402	.num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
	403	.resource = mxc_sdhc2_resources,
	404	};
	405
f6d2fa7d	406	#ifdef CONFIG_MACH_MX27
627fb3b9 M	407	static struct resource otg_resources[] = {
	408	{
	409	.start = OTG_BASE_ADDR,
	410	.end = OTG_BASE_ADDR + 0x1ff,
	411	.flags = IORESOURCE_MEM,
	412	}, {
	413	.start = MXC_INT_USB3,
	414	.end = MXC_INT_USB3,
	415	.flags = IORESOURCE_IRQ,
	416	},
	417	};
	418
	419	static u64 otg_dmamask = 0xffffffffUL;
	420
	421	/* OTG gadget device */
	422	struct platform_device mxc_otg_udc_device = {
	423	.name = "fsl-usb2-udc",
	424	.id = -1,
	425	.dev = {
	426	.dma_mask = &otg_dmamask,
	427	.coherent_dma_mask = 0xffffffffUL,
	428	},
	429	.resource = otg_resources,
	430	.num_resources = ARRAY_SIZE(otg_resources),
	431	};
	432
	433	/* OTG host */
	434	struct platform_device mxc_otg_host = {
	435	.name = "mxc-ehci",
	436	.id = 0,
	437	.dev = {
	438	.coherent_dma_mask = 0xffffffff,
	439	.dma_mask = &otg_dmamask,
	440	},
	441	.resource = otg_resources,
	442	.num_resources = ARRAY_SIZE(otg_resources),
	443	};
	444
	445	/* USB host 1 */
	446
	447	static u64 usbh1_dmamask = 0xffffffffUL;
	448
	449	static struct resource mxc_usbh1_resources[] = {
	450	{
	451	.start = OTG_BASE_ADDR + 0x200,
	452	.end = OTG_BASE_ADDR + 0x3ff,
	453	.flags = IORESOURCE_MEM,
	454	}, {
	455	.start = MXC_INT_USB1,
	456	.end = MXC_INT_USB1,
	457	.flags = IORESOURCE_IRQ,
	458	},
	459	};
	460
	461	struct platform_device mxc_usbh1 = {
	462	.name = "mxc-ehci",
	463	.id = 1,
	464	.dev = {
	465	.coherent_dma_mask = 0xffffffff,
	466	.dma_mask = &usbh1_dmamask,
	467	},
	468	.resource = mxc_usbh1_resources,
	469	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	470	};
471
472	/* USB host 2 */
473	static u64 usbh2_dmamask = 0xffffffffUL;
474
475	static struct resource mxc_usbh2_resources[] = {
476	{
477	.start = OTG_BASE_ADDR + 0x400,
478	.end = OTG_BASE_ADDR + 0x5ff,
479	.flags = IORESOURCE_MEM,
480	}, {
481	.start = MXC_INT_USB2,
482	.end = MXC_INT_USB2,
483	.flags = IORESOURCE_IRQ,
484	},
485	};
486
487	struct platform_device mxc_usbh2 = {
488	.name = "mxc-ehci",
489	.id = 2,
490	.dev = {
491	.coherent_dma_mask = 0xffffffff,
492	.dma_mask = &usbh2_dmamask,
493	},
494	.resource = mxc_usbh2_resources,
495	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
496	};
f6d2fa7d	497	#endif
627fb3b9	498
23291df4 SH	499	static struct resource imx_ssi_resources0[] = {
	500	{
	501	.start = SSI1_BASE_ADDR,
	502	.end = SSI1_BASE_ADDR + 0x6F,
	503	.flags = IORESOURCE_MEM,
	504	}, {
	505	.start = MXC_INT_SSI1,
	506	.end = MXC_INT_SSI1,
	507	.flags = IORESOURCE_IRQ,
	508	}, {
	509	.name = "tx0",
	510	.start = DMA_REQ_SSI1_TX0,
	511	.end = DMA_REQ_SSI1_TX0,
	512	.flags = IORESOURCE_DMA,
	513	}, {
	514	.name = "rx0",
	515	.start = DMA_REQ_SSI1_RX0,
	516	.end = DMA_REQ_SSI1_RX0,
	517	.flags = IORESOURCE_DMA,
	518	}, {
	519	.name = "tx1",
	520	.start = DMA_REQ_SSI1_TX1,
	521	.end = DMA_REQ_SSI1_TX1,
	522	.flags = IORESOURCE_DMA,
	523	}, {
	524	.name = "rx1",
	525	.start = DMA_REQ_SSI1_RX1,
	526	.end = DMA_REQ_SSI1_RX1,
	527	.flags = IORESOURCE_DMA,
	528	},
	529	};
	530
	531	static struct resource imx_ssi_resources1[] = {
	532	{
	533	.start = SSI2_BASE_ADDR,
	534	.end = SSI2_BASE_ADDR + 0x6F,
	535	.flags = IORESOURCE_MEM,
	536	}, {
	537	.start = MXC_INT_SSI2,
	538	.end = MXC_INT_SSI2,
	539	.flags = IORESOURCE_IRQ,
	540	}, {
	541	.name = "tx0",
	542	.start = DMA_REQ_SSI2_TX0,
	543	.end = DMA_REQ_SSI2_TX0,
	544	.flags = IORESOURCE_DMA,
	545	}, {
	546	.name = "rx0",
	547	.start = DMA_REQ_SSI2_RX0,
	548	.end = DMA_REQ_SSI2_RX0,
	549	.flags = IORESOURCE_DMA,
	550	}, {
	551	.name = "tx1",
	552	.start = DMA_REQ_SSI2_TX1,
	553	.end = DMA_REQ_SSI2_TX1,
	554	.flags = IORESOURCE_DMA,
	555	}, {
	556	.name = "rx1",
	557	.start = DMA_REQ_SSI2_RX1,
	558	.end = DMA_REQ_SSI2_RX1,
	559	.flags = IORESOURCE_DMA,
	560	},
	561	};
	562
563	struct platform_device imx_ssi_device0 = {
564	.name = "imx-ssi",
565	.id = 0,
566	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
567	.resource = imx_ssi_resources0,
568	};
569
570	struct platform_device imx_ssi_device1 = {
571	.name = "imx-ssi",
572	.id = 1,
573	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
574	.resource = imx_ssi_resources1,
575	};
576
fc80a5e3 JB	577	/* GPIO port description */
fc80a5e3 JB	578	static struct mxc_gpio_port imx_gpio_ports[] = {
bf50bcc2	579	{
fc80a5e3 JB	580	.chip.label = "gpio-0",
fc80a5e3 JB	581	.irq = MXC_INT_GPIO,
058b7a6f	582	.base = IO_ADDRESS(GPIO_BASE_ADDR),
9d631b83	583	.virtual_irq_start = MXC_GPIO_IRQ_START,
bf50bcc2	584	}, {
fc80a5e3	585	.chip.label = "gpio-1",
058b7a6f	586	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
9d631b83	587	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
bf50bcc2	588	}, {
fc80a5e3	589	.chip.label = "gpio-2",
058b7a6f	590	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
9d631b83	591	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
bf50bcc2	592	}, {
fc80a5e3	593	.chip.label = "gpio-3",
058b7a6f	594	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
9d631b83	595	.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
bf50bcc2	596	}, {
fc80a5e3	597	.chip.label = "gpio-4",
058b7a6f	598	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
9d631b83	599	.virtual_irq_start = MXC_GPIO_IRQ_START + 128,
bf50bcc2	600	}, {
fc80a5e3	601	.chip.label = "gpio-5",
058b7a6f	602	.base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
9d631b83	603	.virtual_irq_start = MXC_GPIO_IRQ_START + 160,
fc80a5e3 JB	604	}
	605	};
	606
	607	int __init mxc_register_gpios(void)
	608	{
	609	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	610	}