Commit | Line | Data |
---|---|---|
fc80a5e3 JB |
1 | /* |
2 | * Author: MontaVista Software, Inc. | |
3 | * <source@mvista.com> | |
4 | * | |
5 | * Based on the OMAP devices.c | |
6 | * | |
7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | * | |
12 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
13 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version 2 | |
18 | * of the License, or (at your option) any later version. | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
27 | * MA 02110-1301, USA. | |
28 | */ | |
29 | #include <linux/module.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/gpio.h> | |
34 | ||
80b02c17 | 35 | #include <mach/irqs.h> |
a09e64fb | 36 | #include <mach/hardware.h> |
058b7a6f HS |
37 | #include <mach/common.h> |
38 | ||
39 | #include "devices.h" | |
fc80a5e3 JB |
40 | |
41 | /* | |
42 | * Resource definition for the MXC IrDA | |
43 | */ | |
44 | static struct resource mxc_irda_resources[] = { | |
45 | [0] = { | |
46 | .start = UART3_BASE_ADDR, | |
47 | .end = UART3_BASE_ADDR + SZ_4K - 1, | |
48 | .flags = IORESOURCE_MEM, | |
49 | }, | |
50 | [1] = { | |
51 | .start = MXC_INT_UART3, | |
52 | .end = MXC_INT_UART3, | |
53 | .flags = IORESOURCE_IRQ, | |
54 | }, | |
55 | }; | |
56 | ||
57 | /* Platform Data for MXC IrDA */ | |
58 | struct platform_device mxc_irda_device = { | |
59 | .name = "mxc_irda", | |
60 | .id = 0, | |
61 | .num_resources = ARRAY_SIZE(mxc_irda_resources), | |
62 | .resource = mxc_irda_resources, | |
63 | }; | |
64 | ||
65 | /* | |
66 | * General Purpose Timer | |
67 | * - i.MX1: 2 timer (slighly different register handling) | |
68 | * - i.MX21: 3 timer | |
69 | * - i.MX27: 6 timer | |
70 | */ | |
71 | ||
72 | /* We use gpt0 as system timer, so do not add a device for this one */ | |
73 | ||
74 | static struct resource timer1_resources[] = { | |
75 | [0] = { | |
76 | .start = GPT2_BASE_ADDR, | |
77 | .end = GPT2_BASE_ADDR + 0x17, | |
78 | .flags = IORESOURCE_MEM | |
79 | }, | |
80 | [1] = { | |
81 | .start = MXC_INT_GPT2, | |
82 | .end = MXC_INT_GPT2, | |
83 | .flags = IORESOURCE_IRQ, | |
84 | } | |
85 | }; | |
86 | ||
87 | struct platform_device mxc_gpt1 = { | |
88 | .name = "imx_gpt", | |
89 | .id = 1, | |
90 | .num_resources = ARRAY_SIZE(timer1_resources), | |
91 | .resource = timer1_resources | |
92 | }; | |
93 | ||
94 | static struct resource timer2_resources[] = { | |
95 | [0] = { | |
96 | .start = GPT3_BASE_ADDR, | |
97 | .end = GPT3_BASE_ADDR + 0x17, | |
98 | .flags = IORESOURCE_MEM | |
99 | }, | |
100 | [1] = { | |
101 | .start = MXC_INT_GPT3, | |
102 | .end = MXC_INT_GPT3, | |
103 | .flags = IORESOURCE_IRQ, | |
104 | } | |
105 | }; | |
106 | ||
107 | struct platform_device mxc_gpt2 = { | |
108 | .name = "imx_gpt", | |
109 | .id = 2, | |
110 | .num_resources = ARRAY_SIZE(timer2_resources), | |
111 | .resource = timer2_resources | |
112 | }; | |
113 | ||
114 | #ifdef CONFIG_MACH_MX27 | |
115 | static struct resource timer3_resources[] = { | |
116 | [0] = { | |
117 | .start = GPT4_BASE_ADDR, | |
118 | .end = GPT4_BASE_ADDR + 0x17, | |
119 | .flags = IORESOURCE_MEM | |
120 | }, | |
121 | [1] = { | |
122 | .start = MXC_INT_GPT4, | |
123 | .end = MXC_INT_GPT4, | |
124 | .flags = IORESOURCE_IRQ, | |
125 | } | |
126 | }; | |
127 | ||
128 | struct platform_device mxc_gpt3 = { | |
129 | .name = "imx_gpt", | |
130 | .id = 3, | |
131 | .num_resources = ARRAY_SIZE(timer3_resources), | |
132 | .resource = timer3_resources | |
133 | }; | |
134 | ||
135 | static struct resource timer4_resources[] = { | |
136 | [0] = { | |
137 | .start = GPT5_BASE_ADDR, | |
138 | .end = GPT5_BASE_ADDR + 0x17, | |
139 | .flags = IORESOURCE_MEM | |
140 | }, | |
141 | [1] = { | |
142 | .start = MXC_INT_GPT5, | |
143 | .end = MXC_INT_GPT5, | |
144 | .flags = IORESOURCE_IRQ, | |
145 | } | |
146 | }; | |
147 | ||
148 | struct platform_device mxc_gpt4 = { | |
149 | .name = "imx_gpt", | |
150 | .id = 4, | |
151 | .num_resources = ARRAY_SIZE(timer4_resources), | |
152 | .resource = timer4_resources | |
153 | }; | |
154 | ||
155 | static struct resource timer5_resources[] = { | |
156 | [0] = { | |
157 | .start = GPT6_BASE_ADDR, | |
158 | .end = GPT6_BASE_ADDR + 0x17, | |
159 | .flags = IORESOURCE_MEM | |
160 | }, | |
161 | [1] = { | |
162 | .start = MXC_INT_GPT6, | |
163 | .end = MXC_INT_GPT6, | |
164 | .flags = IORESOURCE_IRQ, | |
165 | } | |
166 | }; | |
167 | ||
168 | struct platform_device mxc_gpt5 = { | |
169 | .name = "imx_gpt", | |
170 | .id = 5, | |
171 | .num_resources = ARRAY_SIZE(timer5_resources), | |
172 | .resource = timer5_resources | |
173 | }; | |
174 | #endif | |
175 | ||
176 | /* | |
177 | * Watchdog: | |
178 | * - i.MX1 | |
179 | * - i.MX21 | |
180 | * - i.MX27 | |
181 | */ | |
182 | static struct resource mxc_wdt_resources[] = { | |
183 | { | |
184 | .start = WDOG_BASE_ADDR, | |
185 | .end = WDOG_BASE_ADDR + 0x30, | |
186 | .flags = IORESOURCE_MEM, | |
187 | }, | |
188 | }; | |
189 | ||
190 | struct platform_device mxc_wdt = { | |
191 | .name = "mxc_wdt", | |
192 | .id = 0, | |
193 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | |
194 | .resource = mxc_wdt_resources, | |
195 | }; | |
196 | ||
3d89baa7 SH |
197 | static struct resource mxc_w1_master_resources[] = { |
198 | { | |
199 | .start = OWIRE_BASE_ADDR, | |
200 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | |
201 | .flags = IORESOURCE_MEM, | |
202 | }, | |
203 | }; | |
204 | ||
205 | struct platform_device mxc_w1_master_device = { | |
206 | .name = "mxc_w1", | |
207 | .id = 0, | |
208 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
209 | .resource = mxc_w1_master_resources, | |
210 | }; | |
211 | ||
02870978 SH |
212 | static struct resource mxc_nand_resources[] = { |
213 | { | |
214 | .start = NFC_BASE_ADDR, | |
215 | .end = NFC_BASE_ADDR + 0xfff, | |
216 | .flags = IORESOURCE_MEM | |
217 | }, { | |
218 | .start = MXC_INT_NANDFC, | |
219 | .end = MXC_INT_NANDFC, | |
220 | .flags = IORESOURCE_IRQ | |
221 | }, | |
222 | }; | |
223 | ||
224 | struct platform_device mxc_nand_device = { | |
225 | .name = "mxc_nand", | |
226 | .id = 0, | |
227 | .num_resources = ARRAY_SIZE(mxc_nand_resources), | |
228 | .resource = mxc_nand_resources, | |
229 | }; | |
230 | ||
e4813551 HS |
231 | #ifdef CONFIG_FB_IMX |
232 | /* | |
233 | * lcdc: | |
234 | * - i.MX1: the basic controller | |
235 | * - i.MX21: to be checked | |
236 | * - i.MX27: like i.MX1, with slightly variations | |
237 | */ | |
238 | static struct resource mxc_fb[] = { | |
239 | { | |
240 | .start = LCDC_BASE_ADDR, | |
241 | .end = LCDC_BASE_ADDR + 0xFFF, | |
242 | .flags = IORESOURCE_MEM, | |
243 | }, | |
244 | { | |
245 | .start = MXC_INT_LCDC, | |
246 | .end = MXC_INT_LCDC, | |
247 | .flags = IORESOURCE_IRQ, | |
248 | } | |
249 | }; | |
250 | ||
251 | /* mxc lcd driver */ | |
252 | struct platform_device mxc_fb_device = { | |
253 | .name = "imx-fb", | |
254 | .id = 0, | |
255 | .num_resources = ARRAY_SIZE(mxc_fb), | |
256 | .resource = mxc_fb, | |
257 | .dev = { | |
258 | .coherent_dma_mask = 0xFFFFFFFF, | |
259 | }, | |
260 | }; | |
879fea1b | 261 | #endif |
e4813551 | 262 | |
879fea1b SH |
263 | #ifdef CONFIG_MACH_MX27 |
264 | static struct resource mxc_fec_resources[] = { | |
265 | { | |
266 | .start = FEC_BASE_ADDR, | |
267 | .end = FEC_BASE_ADDR + 0xfff, | |
268 | .flags = IORESOURCE_MEM | |
269 | }, { | |
270 | .start = MXC_INT_FEC, | |
271 | .end = MXC_INT_FEC, | |
272 | .flags = IORESOURCE_IRQ | |
273 | }, | |
274 | }; | |
275 | ||
276 | struct platform_device mxc_fec_device = { | |
277 | .name = "fec", | |
278 | .id = 0, | |
279 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | |
280 | .resource = mxc_fec_resources, | |
281 | }; | |
e4813551 HS |
282 | #endif |
283 | ||
c5d4dbff SH |
284 | static struct resource mxc_i2c_1_resources[] = { |
285 | [0] = { | |
286 | .start = I2C_BASE_ADDR, | |
287 | .end = I2C_BASE_ADDR + 0x0fff, | |
288 | .flags = IORESOURCE_MEM | |
289 | }, | |
290 | [1] = { | |
291 | .start = MXC_INT_I2C, | |
292 | .end = MXC_INT_I2C, | |
293 | .flags = IORESOURCE_IRQ | |
294 | } | |
295 | }; | |
296 | ||
297 | struct platform_device mxc_i2c_device0 = { | |
298 | .name = "imx-i2c", | |
299 | .id = 0, | |
300 | .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), | |
301 | .resource = mxc_i2c_1_resources | |
302 | }; | |
303 | ||
304 | #ifdef CONFIG_MACH_MX27 | |
305 | static struct resource mxc_i2c_2_resources[] = { | |
306 | [0] = { | |
307 | .start = I2C2_BASE_ADDR, | |
308 | .end = I2C2_BASE_ADDR + 0x0fff, | |
309 | .flags = IORESOURCE_MEM | |
310 | }, | |
311 | [1] = { | |
312 | .start = MXC_INT_I2C2, | |
313 | .end = MXC_INT_I2C2, | |
314 | .flags = IORESOURCE_IRQ | |
315 | } | |
316 | }; | |
317 | ||
318 | struct platform_device mxc_i2c_device1 = { | |
319 | .name = "imx-i2c", | |
320 | .id = 1, | |
321 | .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), | |
322 | .resource = mxc_i2c_2_resources | |
323 | }; | |
324 | #endif | |
325 | ||
824b16e6 SH |
326 | static struct resource mxc_pwm_resources[] = { |
327 | [0] = { | |
328 | .start = PWM_BASE_ADDR, | |
329 | .end = PWM_BASE_ADDR + 0x0fff, | |
330 | .flags = IORESOURCE_MEM | |
331 | }, | |
332 | [1] = { | |
333 | .start = MXC_INT_PWM, | |
334 | .end = MXC_INT_PWM, | |
335 | .flags = IORESOURCE_IRQ, | |
336 | } | |
337 | }; | |
338 | ||
339 | struct platform_device mxc_pwm_device = { | |
340 | .name = "mxc_pwm", | |
341 | .id = 0, | |
342 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | |
343 | .resource = mxc_pwm_resources | |
344 | }; | |
345 | ||
fc80a5e3 JB |
346 | /* GPIO port description */ |
347 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
348 | [0] = { | |
349 | .chip.label = "gpio-0", | |
350 | .irq = MXC_INT_GPIO, | |
058b7a6f | 351 | .base = IO_ADDRESS(GPIO_BASE_ADDR), |
9d631b83 | 352 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
fc80a5e3 JB |
353 | }, |
354 | [1] = { | |
355 | .chip.label = "gpio-1", | |
058b7a6f | 356 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), |
9d631b83 | 357 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
fc80a5e3 JB |
358 | }, |
359 | [2] = { | |
360 | .chip.label = "gpio-2", | |
058b7a6f | 361 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), |
9d631b83 | 362 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
fc80a5e3 JB |
363 | }, |
364 | [3] = { | |
365 | .chip.label = "gpio-3", | |
058b7a6f | 366 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), |
9d631b83 | 367 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, |
fc80a5e3 JB |
368 | }, |
369 | [4] = { | |
370 | .chip.label = "gpio-4", | |
058b7a6f | 371 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), |
9d631b83 | 372 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, |
fc80a5e3 JB |
373 | }, |
374 | [5] = { | |
375 | .chip.label = "gpio-5", | |
058b7a6f | 376 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), |
9d631b83 | 377 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |
fc80a5e3 JB |
378 | } |
379 | }; | |
380 | ||
381 | int __init mxc_register_gpios(void) | |
382 | { | |
383 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
384 | } |