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fc80a5e3 JB |
1 | /* |
2 | * Author: MontaVista Software, Inc. | |
3 | * <source@mvista.com> | |
4 | * | |
5 | * Based on the OMAP devices.c | |
6 | * | |
7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | * | |
12 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
13 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version 2 | |
18 | * of the License, or (at your option) any later version. | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
27 | * MA 02110-1301, USA. | |
28 | */ | |
29 | #include <linux/module.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/gpio.h> | |
34 | ||
80b02c17 | 35 | #include <mach/irqs.h> |
a09e64fb | 36 | #include <mach/hardware.h> |
fc80a5e3 JB |
37 | |
38 | /* | |
39 | * Resource definition for the MXC IrDA | |
40 | */ | |
41 | static struct resource mxc_irda_resources[] = { | |
42 | [0] = { | |
43 | .start = UART3_BASE_ADDR, | |
44 | .end = UART3_BASE_ADDR + SZ_4K - 1, | |
45 | .flags = IORESOURCE_MEM, | |
46 | }, | |
47 | [1] = { | |
48 | .start = MXC_INT_UART3, | |
49 | .end = MXC_INT_UART3, | |
50 | .flags = IORESOURCE_IRQ, | |
51 | }, | |
52 | }; | |
53 | ||
54 | /* Platform Data for MXC IrDA */ | |
55 | struct platform_device mxc_irda_device = { | |
56 | .name = "mxc_irda", | |
57 | .id = 0, | |
58 | .num_resources = ARRAY_SIZE(mxc_irda_resources), | |
59 | .resource = mxc_irda_resources, | |
60 | }; | |
61 | ||
62 | /* | |
63 | * General Purpose Timer | |
64 | * - i.MX1: 2 timer (slighly different register handling) | |
65 | * - i.MX21: 3 timer | |
66 | * - i.MX27: 6 timer | |
67 | */ | |
68 | ||
69 | /* We use gpt0 as system timer, so do not add a device for this one */ | |
70 | ||
71 | static struct resource timer1_resources[] = { | |
72 | [0] = { | |
73 | .start = GPT2_BASE_ADDR, | |
74 | .end = GPT2_BASE_ADDR + 0x17, | |
75 | .flags = IORESOURCE_MEM | |
76 | }, | |
77 | [1] = { | |
78 | .start = MXC_INT_GPT2, | |
79 | .end = MXC_INT_GPT2, | |
80 | .flags = IORESOURCE_IRQ, | |
81 | } | |
82 | }; | |
83 | ||
84 | struct platform_device mxc_gpt1 = { | |
85 | .name = "imx_gpt", | |
86 | .id = 1, | |
87 | .num_resources = ARRAY_SIZE(timer1_resources), | |
88 | .resource = timer1_resources | |
89 | }; | |
90 | ||
91 | static struct resource timer2_resources[] = { | |
92 | [0] = { | |
93 | .start = GPT3_BASE_ADDR, | |
94 | .end = GPT3_BASE_ADDR + 0x17, | |
95 | .flags = IORESOURCE_MEM | |
96 | }, | |
97 | [1] = { | |
98 | .start = MXC_INT_GPT3, | |
99 | .end = MXC_INT_GPT3, | |
100 | .flags = IORESOURCE_IRQ, | |
101 | } | |
102 | }; | |
103 | ||
104 | struct platform_device mxc_gpt2 = { | |
105 | .name = "imx_gpt", | |
106 | .id = 2, | |
107 | .num_resources = ARRAY_SIZE(timer2_resources), | |
108 | .resource = timer2_resources | |
109 | }; | |
110 | ||
111 | #ifdef CONFIG_MACH_MX27 | |
112 | static struct resource timer3_resources[] = { | |
113 | [0] = { | |
114 | .start = GPT4_BASE_ADDR, | |
115 | .end = GPT4_BASE_ADDR + 0x17, | |
116 | .flags = IORESOURCE_MEM | |
117 | }, | |
118 | [1] = { | |
119 | .start = MXC_INT_GPT4, | |
120 | .end = MXC_INT_GPT4, | |
121 | .flags = IORESOURCE_IRQ, | |
122 | } | |
123 | }; | |
124 | ||
125 | struct platform_device mxc_gpt3 = { | |
126 | .name = "imx_gpt", | |
127 | .id = 3, | |
128 | .num_resources = ARRAY_SIZE(timer3_resources), | |
129 | .resource = timer3_resources | |
130 | }; | |
131 | ||
132 | static struct resource timer4_resources[] = { | |
133 | [0] = { | |
134 | .start = GPT5_BASE_ADDR, | |
135 | .end = GPT5_BASE_ADDR + 0x17, | |
136 | .flags = IORESOURCE_MEM | |
137 | }, | |
138 | [1] = { | |
139 | .start = MXC_INT_GPT5, | |
140 | .end = MXC_INT_GPT5, | |
141 | .flags = IORESOURCE_IRQ, | |
142 | } | |
143 | }; | |
144 | ||
145 | struct platform_device mxc_gpt4 = { | |
146 | .name = "imx_gpt", | |
147 | .id = 4, | |
148 | .num_resources = ARRAY_SIZE(timer4_resources), | |
149 | .resource = timer4_resources | |
150 | }; | |
151 | ||
152 | static struct resource timer5_resources[] = { | |
153 | [0] = { | |
154 | .start = GPT6_BASE_ADDR, | |
155 | .end = GPT6_BASE_ADDR + 0x17, | |
156 | .flags = IORESOURCE_MEM | |
157 | }, | |
158 | [1] = { | |
159 | .start = MXC_INT_GPT6, | |
160 | .end = MXC_INT_GPT6, | |
161 | .flags = IORESOURCE_IRQ, | |
162 | } | |
163 | }; | |
164 | ||
165 | struct platform_device mxc_gpt5 = { | |
166 | .name = "imx_gpt", | |
167 | .id = 5, | |
168 | .num_resources = ARRAY_SIZE(timer5_resources), | |
169 | .resource = timer5_resources | |
170 | }; | |
171 | #endif | |
172 | ||
173 | /* | |
174 | * Watchdog: | |
175 | * - i.MX1 | |
176 | * - i.MX21 | |
177 | * - i.MX27 | |
178 | */ | |
179 | static struct resource mxc_wdt_resources[] = { | |
180 | { | |
181 | .start = WDOG_BASE_ADDR, | |
182 | .end = WDOG_BASE_ADDR + 0x30, | |
183 | .flags = IORESOURCE_MEM, | |
184 | }, | |
185 | }; | |
186 | ||
187 | struct platform_device mxc_wdt = { | |
188 | .name = "mxc_wdt", | |
189 | .id = 0, | |
190 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | |
191 | .resource = mxc_wdt_resources, | |
192 | }; | |
193 | ||
3d89baa7 SH |
194 | static struct resource mxc_w1_master_resources[] = { |
195 | { | |
196 | .start = OWIRE_BASE_ADDR, | |
197 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | |
198 | .flags = IORESOURCE_MEM, | |
199 | }, | |
200 | }; | |
201 | ||
202 | struct platform_device mxc_w1_master_device = { | |
203 | .name = "mxc_w1", | |
204 | .id = 0, | |
205 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
206 | .resource = mxc_w1_master_resources, | |
207 | }; | |
208 | ||
02870978 SH |
209 | static struct resource mxc_nand_resources[] = { |
210 | { | |
211 | .start = NFC_BASE_ADDR, | |
212 | .end = NFC_BASE_ADDR + 0xfff, | |
213 | .flags = IORESOURCE_MEM | |
214 | }, { | |
215 | .start = MXC_INT_NANDFC, | |
216 | .end = MXC_INT_NANDFC, | |
217 | .flags = IORESOURCE_IRQ | |
218 | }, | |
219 | }; | |
220 | ||
221 | struct platform_device mxc_nand_device = { | |
222 | .name = "mxc_nand", | |
223 | .id = 0, | |
224 | .num_resources = ARRAY_SIZE(mxc_nand_resources), | |
225 | .resource = mxc_nand_resources, | |
226 | }; | |
227 | ||
fc80a5e3 JB |
228 | /* GPIO port description */ |
229 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
230 | [0] = { | |
231 | .chip.label = "gpio-0", | |
232 | .irq = MXC_INT_GPIO, | |
233 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0), | |
9d631b83 | 234 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
fc80a5e3 JB |
235 | }, |
236 | [1] = { | |
237 | .chip.label = "gpio-1", | |
238 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1), | |
9d631b83 | 239 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
fc80a5e3 JB |
240 | }, |
241 | [2] = { | |
242 | .chip.label = "gpio-2", | |
243 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2), | |
9d631b83 | 244 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
fc80a5e3 JB |
245 | }, |
246 | [3] = { | |
247 | .chip.label = "gpio-3", | |
248 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3), | |
9d631b83 | 249 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, |
fc80a5e3 JB |
250 | }, |
251 | [4] = { | |
252 | .chip.label = "gpio-4", | |
253 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4), | |
9d631b83 | 254 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, |
fc80a5e3 JB |
255 | }, |
256 | [5] = { | |
257 | .chip.label = "gpio-5", | |
258 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5), | |
9d631b83 | 259 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |
fc80a5e3 JB |
260 | } |
261 | }; | |
262 | ||
263 | int __init mxc_register_gpios(void) | |
264 | { | |
265 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
266 | } |