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fc80a5e3 JB |
1 | /* |
2 | * Author: MontaVista Software, Inc. | |
3 | * <source@mvista.com> | |
4 | * | |
5 | * Based on the OMAP devices.c | |
6 | * | |
7 | * 2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | * | |
12 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
13 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version 2 | |
18 | * of the License, or (at your option) any later version. | |
19 | * This program is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this program; if not, write to the Free Software | |
26 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
27 | * MA 02110-1301, USA. | |
28 | */ | |
29 | #include <linux/module.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/init.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/gpio.h> | |
3eb352c7 | 34 | #include <linux/dma-mapping.h> |
fc80a5e3 | 35 | |
80b02c17 | 36 | #include <mach/irqs.h> |
a09e64fb | 37 | #include <mach/hardware.h> |
058b7a6f | 38 | #include <mach/common.h> |
1a02be0e | 39 | #include <mach/mmc.h> |
058b7a6f HS |
40 | |
41 | #include "devices.h" | |
fc80a5e3 | 42 | |
f420db84 SH |
43 | /* |
44 | * SPI master controller | |
45 | * | |
46 | * - i.MX1: 2 channel (slighly different register setting) | |
47 | * - i.MX21: 2 channel | |
48 | * - i.MX27: 3 channel | |
49 | */ | |
68c94b40 UKK |
50 | #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ |
51 | static struct resource mxc_spi_resources ## n[] = { \ | |
52 | { \ | |
53 | .start = baseaddr, \ | |
54 | .end = baseaddr + SZ_4K - 1, \ | |
55 | .flags = IORESOURCE_MEM, \ | |
56 | }, { \ | |
57 | .start = irq, \ | |
58 | .end = irq, \ | |
59 | .flags = IORESOURCE_IRQ, \ | |
60 | }, \ | |
61 | }; \ | |
62 | \ | |
63 | struct platform_device mxc_spi_device ## n = { \ | |
64 | .name = "spi_imx", \ | |
65 | .id = n, \ | |
66 | .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ | |
67 | .resource = mxc_spi_resources ## n, \ | |
68 | } | |
f420db84 | 69 | |
68c94b40 UKK |
70 | DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); |
71 | DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); | |
f420db84 SH |
72 | |
73 | #ifdef CONFIG_MACH_MX27 | |
68c94b40 | 74 | DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); |
f420db84 SH |
75 | #endif |
76 | ||
fc80a5e3 JB |
77 | /* |
78 | * General Purpose Timer | |
bf50bcc2 SH |
79 | * - i.MX21: 3 timers |
80 | * - i.MX27: 6 timers | |
fc80a5e3 | 81 | */ |
2b84a364 UKK |
82 | #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ |
83 | static struct resource timer ## n ##_resources[] = { \ | |
84 | { \ | |
85 | .start = baseaddr, \ | |
86 | .end = baseaddr + SZ_4K - 1, \ | |
87 | .flags = IORESOURCE_MEM, \ | |
88 | }, { \ | |
89 | .start = irq, \ | |
90 | .end = irq, \ | |
91 | .flags = IORESOURCE_IRQ, \ | |
92 | } \ | |
93 | }; \ | |
94 | \ | |
95 | struct platform_device mxc_gpt ## n = { \ | |
96 | .name = "imx_gpt", \ | |
97 | .id = n, \ | |
98 | .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ | |
99 | .resource = timer ## n ## _resources, \ | |
fc80a5e3 | 100 | } |
fc80a5e3 | 101 | |
2b84a364 UKK |
102 | /* We use gpt1 as system timer, so do not add a device for this one */ |
103 | DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); | |
104 | DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); | |
fc80a5e3 JB |
105 | |
106 | #ifdef CONFIG_MACH_MX27 | |
2b84a364 UKK |
107 | DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); |
108 | DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); | |
109 | DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); | |
fc80a5e3 JB |
110 | #endif |
111 | ||
112 | /* | |
113 | * Watchdog: | |
114 | * - i.MX1 | |
115 | * - i.MX21 | |
116 | * - i.MX27 | |
117 | */ | |
118 | static struct resource mxc_wdt_resources[] = { | |
119 | { | |
58152a16 UKK |
120 | .start = MX2x_WDOG_BASE_ADDR, |
121 | .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, | |
122 | .flags = IORESOURCE_MEM, | |
fc80a5e3 JB |
123 | }, |
124 | }; | |
125 | ||
126 | struct platform_device mxc_wdt = { | |
127 | .name = "mxc_wdt", | |
128 | .id = 0, | |
129 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | |
130 | .resource = mxc_wdt_resources, | |
131 | }; | |
132 | ||
3d89baa7 SH |
133 | static struct resource mxc_w1_master_resources[] = { |
134 | { | |
58152a16 UKK |
135 | .start = MX2x_OWIRE_BASE_ADDR, |
136 | .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, | |
3d89baa7 SH |
137 | .flags = IORESOURCE_MEM, |
138 | }, | |
139 | }; | |
140 | ||
141 | struct platform_device mxc_w1_master_device = { | |
142 | .name = "mxc_w1", | |
143 | .id = 0, | |
144 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
145 | .resource = mxc_w1_master_resources, | |
146 | }; | |
147 | ||
f0d3ab49 UKK |
148 | #define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ |
149 | static struct resource pfx ## _nand_resources[] = { \ | |
150 | { \ | |
151 | .start = baseaddr, \ | |
152 | .end = baseaddr + SZ_4K - 1, \ | |
153 | .flags = IORESOURCE_MEM, \ | |
154 | }, { \ | |
155 | .start = irq, \ | |
156 | .end = irq, \ | |
157 | .flags = IORESOURCE_IRQ, \ | |
158 | }, \ | |
159 | }; \ | |
160 | \ | |
161 | struct platform_device pfx ## _nand_device = { \ | |
162 | .name = "mxc_nand", \ | |
163 | .id = 0, \ | |
164 | .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ | |
165 | .resource = pfx ## _nand_resources, \ | |
166 | } | |
02870978 | 167 | |
f0d3ab49 UKK |
168 | #ifdef CONFIG_MACH_MX21 |
169 | DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); | |
170 | #endif | |
171 | ||
172 | #ifdef CONFIG_MACH_MX27 | |
173 | DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); | |
174 | #endif | |
02870978 | 175 | |
e4813551 HS |
176 | /* |
177 | * lcdc: | |
178 | * - i.MX1: the basic controller | |
179 | * - i.MX21: to be checked | |
180 | * - i.MX27: like i.MX1, with slightly variations | |
181 | */ | |
182 | static struct resource mxc_fb[] = { | |
183 | { | |
58152a16 UKK |
184 | .start = MX2x_LCDC_BASE_ADDR, |
185 | .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, | |
e4813551 | 186 | .flags = IORESOURCE_MEM, |
bf50bcc2 | 187 | }, { |
58152a16 UKK |
188 | .start = MX2x_INT_LCDC, |
189 | .end = MX2x_INT_LCDC, | |
e4813551 HS |
190 | .flags = IORESOURCE_IRQ, |
191 | } | |
192 | }; | |
193 | ||
194 | /* mxc lcd driver */ | |
195 | struct platform_device mxc_fb_device = { | |
196 | .name = "imx-fb", | |
197 | .id = 0, | |
198 | .num_resources = ARRAY_SIZE(mxc_fb), | |
199 | .resource = mxc_fb, | |
200 | .dev = { | |
3eb352c7 | 201 | .coherent_dma_mask = DMA_BIT_MASK(32), |
e4813551 HS |
202 | }, |
203 | }; | |
204 | ||
879fea1b SH |
205 | #ifdef CONFIG_MACH_MX27 |
206 | static struct resource mxc_fec_resources[] = { | |
207 | { | |
58152a16 UKK |
208 | .start = MX27_FEC_BASE_ADDR, |
209 | .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, | |
210 | .flags = IORESOURCE_MEM, | |
879fea1b | 211 | }, { |
58152a16 UKK |
212 | .start = MX27_INT_FEC, |
213 | .end = MX27_INT_FEC, | |
214 | .flags = IORESOURCE_IRQ, | |
879fea1b SH |
215 | }, |
216 | }; | |
217 | ||
218 | struct platform_device mxc_fec_device = { | |
219 | .name = "fec", | |
220 | .id = 0, | |
221 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | |
222 | .resource = mxc_fec_resources, | |
223 | }; | |
e4813551 HS |
224 | #endif |
225 | ||
9309b2ba UKK |
226 | #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ |
227 | static struct resource mxc_i2c_resources ## n[] = { \ | |
228 | { \ | |
229 | .start = baseaddr, \ | |
230 | .end = baseaddr + SZ_4K - 1, \ | |
231 | .flags = IORESOURCE_MEM, \ | |
232 | }, { \ | |
233 | .start = irq, \ | |
234 | .end = irq, \ | |
235 | .flags = IORESOURCE_IRQ, \ | |
236 | } \ | |
237 | }; \ | |
238 | \ | |
239 | struct platform_device mxc_i2c_device ## n = { \ | |
240 | .name = "imx-i2c", \ | |
241 | .id = n, \ | |
242 | .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ | |
243 | .resource = mxc_i2c_resources ## n, \ | |
c5d4dbff | 244 | } |
c5d4dbff | 245 | |
9309b2ba | 246 | DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); |
c5d4dbff SH |
247 | |
248 | #ifdef CONFIG_MACH_MX27 | |
9309b2ba | 249 | DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); |
c5d4dbff SH |
250 | #endif |
251 | ||
824b16e6 | 252 | static struct resource mxc_pwm_resources[] = { |
bf50bcc2 | 253 | { |
58152a16 UKK |
254 | .start = MX2x_PWM_BASE_ADDR, |
255 | .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, | |
256 | .flags = IORESOURCE_MEM, | |
bf50bcc2 | 257 | }, { |
58152a16 UKK |
258 | .start = MX2x_INT_PWM, |
259 | .end = MX2x_INT_PWM, | |
260 | .flags = IORESOURCE_IRQ, | |
824b16e6 SH |
261 | } |
262 | }; | |
263 | ||
264 | struct platform_device mxc_pwm_device = { | |
265 | .name = "mxc_pwm", | |
266 | .id = 0, | |
267 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | |
bf50bcc2 | 268 | .resource = mxc_pwm_resources, |
824b16e6 SH |
269 | }; |
270 | ||
ccd0e42c UKK |
271 | #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ |
272 | static struct resource mxc_sdhc_resources ## n[] = { \ | |
273 | { \ | |
274 | .start = baseaddr, \ | |
275 | .end = baseaddr + SZ_4K - 1, \ | |
276 | .flags = IORESOURCE_MEM, \ | |
277 | }, { \ | |
278 | .start = irq, \ | |
279 | .end = irq, \ | |
280 | .flags = IORESOURCE_IRQ, \ | |
281 | }, { \ | |
282 | .start = dmareq, \ | |
283 | .end = dmareq, \ | |
284 | .flags = IORESOURCE_DMA, \ | |
285 | }, \ | |
286 | }; \ | |
287 | \ | |
988addf8 | 288 | static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \ |
ccd0e42c UKK |
289 | \ |
290 | struct platform_device mxc_sdhc_device ## n = { \ | |
291 | .name = "mxc-mmc", \ | |
292 | .id = n, \ | |
293 | .dev = { \ | |
294 | .dma_mask = &mxc_sdhc ## n ## _dmamask, \ | |
988addf8 | 295 | .coherent_dma_mask = DMA_BIT_MASK(32), \ |
ccd0e42c UKK |
296 | }, \ |
297 | .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ | |
298 | .resource = mxc_sdhc_resources ## n, \ | |
299 | } | |
1a02be0e | 300 | |
ccd0e42c UKK |
301 | DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); |
302 | DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); | |
1a02be0e | 303 | |
f6d2fa7d | 304 | #ifdef CONFIG_MACH_MX27 |
627fb3b9 M |
305 | static struct resource otg_resources[] = { |
306 | { | |
58152a16 UKK |
307 | .start = MX27_USBOTG_BASE_ADDR, |
308 | .end = MX27_USBOTG_BASE_ADDR + 0x1ff, | |
309 | .flags = IORESOURCE_MEM, | |
627fb3b9 | 310 | }, { |
58152a16 UKK |
311 | .start = MX27_INT_USB3, |
312 | .end = MX27_INT_USB3, | |
313 | .flags = IORESOURCE_IRQ, | |
627fb3b9 M |
314 | }, |
315 | }; | |
316 | ||
3eb352c7 | 317 | static u64 otg_dmamask = DMA_BIT_MASK(32); |
627fb3b9 M |
318 | |
319 | /* OTG gadget device */ | |
320 | struct platform_device mxc_otg_udc_device = { | |
321 | .name = "fsl-usb2-udc", | |
322 | .id = -1, | |
323 | .dev = { | |
324 | .dma_mask = &otg_dmamask, | |
3eb352c7 | 325 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
326 | }, |
327 | .resource = otg_resources, | |
328 | .num_resources = ARRAY_SIZE(otg_resources), | |
329 | }; | |
330 | ||
331 | /* OTG host */ | |
332 | struct platform_device mxc_otg_host = { | |
333 | .name = "mxc-ehci", | |
334 | .id = 0, | |
335 | .dev = { | |
3eb352c7 | 336 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
337 | .dma_mask = &otg_dmamask, |
338 | }, | |
339 | .resource = otg_resources, | |
340 | .num_resources = ARRAY_SIZE(otg_resources), | |
341 | }; | |
342 | ||
343 | /* USB host 1 */ | |
344 | ||
3eb352c7 | 345 | static u64 usbh1_dmamask = DMA_BIT_MASK(32); |
627fb3b9 M |
346 | |
347 | static struct resource mxc_usbh1_resources[] = { | |
348 | { | |
58152a16 UKK |
349 | .start = MX27_USBOTG_BASE_ADDR + 0x200, |
350 | .end = MX27_USBOTG_BASE_ADDR + 0x3ff, | |
627fb3b9 M |
351 | .flags = IORESOURCE_MEM, |
352 | }, { | |
58152a16 UKK |
353 | .start = MX27_INT_USB1, |
354 | .end = MX27_INT_USB1, | |
627fb3b9 M |
355 | .flags = IORESOURCE_IRQ, |
356 | }, | |
357 | }; | |
358 | ||
359 | struct platform_device mxc_usbh1 = { | |
360 | .name = "mxc-ehci", | |
361 | .id = 1, | |
362 | .dev = { | |
3eb352c7 | 363 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
364 | .dma_mask = &usbh1_dmamask, |
365 | }, | |
366 | .resource = mxc_usbh1_resources, | |
367 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | |
368 | }; | |
369 | ||
370 | /* USB host 2 */ | |
3eb352c7 | 371 | static u64 usbh2_dmamask = DMA_BIT_MASK(32); |
627fb3b9 M |
372 | |
373 | static struct resource mxc_usbh2_resources[] = { | |
374 | { | |
58152a16 UKK |
375 | .start = MX27_USBOTG_BASE_ADDR + 0x400, |
376 | .end = MX27_USBOTG_BASE_ADDR + 0x5ff, | |
627fb3b9 M |
377 | .flags = IORESOURCE_MEM, |
378 | }, { | |
58152a16 UKK |
379 | .start = MX27_INT_USB2, |
380 | .end = MX27_INT_USB2, | |
627fb3b9 M |
381 | .flags = IORESOURCE_IRQ, |
382 | }, | |
383 | }; | |
384 | ||
385 | struct platform_device mxc_usbh2 = { | |
386 | .name = "mxc-ehci", | |
387 | .id = 2, | |
388 | .dev = { | |
3eb352c7 | 389 | .coherent_dma_mask = DMA_BIT_MASK(32), |
627fb3b9 M |
390 | .dma_mask = &usbh2_dmamask, |
391 | }, | |
392 | .resource = mxc_usbh2_resources, | |
393 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | |
394 | }; | |
f6d2fa7d | 395 | #endif |
627fb3b9 | 396 | |
69ddb488 UKK |
397 | #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ |
398 | { \ | |
399 | .name = _name, \ | |
400 | .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ | |
401 | .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ | |
402 | .flags = IORESOURCE_DMA, \ | |
403 | } | |
23291df4 | 404 | |
69ddb488 UKK |
405 | #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ |
406 | static struct resource imx_ssi_resources ## n[] = { \ | |
407 | { \ | |
408 | .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ | |
409 | .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ | |
410 | .flags = IORESOURCE_MEM, \ | |
411 | }, { \ | |
412 | .start = MX2x_INT_SSI1, \ | |
413 | .end = MX2x_INT_SSI1, \ | |
414 | .flags = IORESOURCE_IRQ, \ | |
415 | }, \ | |
416 | DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ | |
417 | DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ | |
418 | DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ | |
419 | DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ | |
420 | }; \ | |
421 | \ | |
422 | struct platform_device imx_ssi_device ## n = { \ | |
423 | .name = "imx-ssi", \ | |
424 | .id = n, \ | |
425 | .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ | |
426 | .resource = imx_ssi_resources ## n, \ | |
427 | } | |
23291df4 | 428 | |
69ddb488 UKK |
429 | DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); |
430 | DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); | |
23291df4 | 431 | |
fc80a5e3 | 432 | /* GPIO port description */ |
897359d5 UKK |
433 | #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ |
434 | { \ | |
435 | .chip.label = "gpio-" #n, \ | |
436 | .irq = _irq, \ | |
437 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | |
438 | n * 0x100), \ | |
439 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | |
440 | } | |
441 | ||
442 | #define DEFINE_MXC_GPIO_PORT(SOC, n) \ | |
443 | { \ | |
444 | .chip.label = "gpio-" #n, \ | |
445 | .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ | |
446 | n * 0x100), \ | |
447 | .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ | |
fc80a5e3 | 448 | } |
897359d5 UKK |
449 | |
450 | #define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ | |
451 | static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ | |
452 | DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ | |
453 | DEFINE_MXC_GPIO_PORT(SOC, 1), \ | |
454 | DEFINE_MXC_GPIO_PORT(SOC, 2), \ | |
455 | DEFINE_MXC_GPIO_PORT(SOC, 3), \ | |
456 | DEFINE_MXC_GPIO_PORT(SOC, 4), \ | |
457 | DEFINE_MXC_GPIO_PORT(SOC, 5), \ | |
458 | } | |
459 | ||
460 | #ifdef CONFIG_MACH_MX21 | |
461 | DEFINE_MXC_GPIO_PORTS(MX21, imx21); | |
462 | #endif | |
463 | ||
464 | #ifdef CONFIG_MACH_MX27 | |
465 | DEFINE_MXC_GPIO_PORTS(MX27, imx27); | |
466 | #endif | |
fc80a5e3 JB |
467 | |
468 | int __init mxc_register_gpios(void) | |
469 | { | |
897359d5 UKK |
470 | #ifdef CONFIG_MACH_MX21 |
471 | if (cpu_is_mx21()) | |
472 | return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); | |
473 | else | |
474 | #endif | |
475 | #ifdef CONFIG_MACH_MX27 | |
476 | if (cpu_is_mx27()) | |
477 | return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); | |
478 | else | |
479 | #endif | |
480 | return 0; | |
fc80a5e3 | 481 | } |
4e0fa90d MF |
482 | |
483 | #ifdef CONFIG_MACH_MX21 | |
484 | static struct resource mx21_usbhc_resources[] = { | |
485 | { | |
988addf8 RK |
486 | .start = MX21_BASE_ADDR, |
487 | .end = MX21_BASE_ADDR + 0x1FFF, | |
4e0fa90d MF |
488 | .flags = IORESOURCE_MEM, |
489 | }, | |
490 | { | |
988addf8 RK |
491 | .start = MX21_INT_USBHOST, |
492 | .end = MX21_INT_USBHOST, | |
4e0fa90d MF |
493 | .flags = IORESOURCE_IRQ, |
494 | }, | |
495 | }; | |
496 | ||
497 | struct platform_device mx21_usbhc_device = { | |
498 | .name = "imx21-hcd", | |
499 | .id = 0, | |
500 | .dev = { | |
501 | .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask, | |
502 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
503 | }, | |
504 | .num_resources = ARRAY_SIZE(mx21_usbhc_resources), | |
505 | .resource = mx21_usbhc_resources, | |
506 | }; | |
507 | #endif | |
508 |