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1 | /* |
2 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #include <linux/platform_device.h> | |
22 | #include <linux/mtd/mtd.h> | |
23 | #include <linux/mtd/map.h> | |
24 | #include <linux/mtd/partitions.h> | |
25 | #include <linux/mtd/physmap.h> | |
a09e64fb RK |
26 | #include <mach/common.h> |
27 | #include <mach/hardware.h> | |
80eedae6 JB |
28 | #include <asm/mach-types.h> |
29 | #include <asm/mach/arch.h> | |
30 | #include <asm/mach/time.h> | |
31 | #include <asm/mach/map.h> | |
a09e64fb RK |
32 | #include <mach/gpio.h> |
33 | #include <mach/imx-uart.h> | |
34 | #include <mach/iomux-mx1-mx2.h> | |
35 | #include <mach/board-mx27ads.h> | |
80eedae6 JB |
36 | |
37 | /* ADS's NOR flash */ | |
38 | static struct physmap_flash_data mx27ads_flash_data = { | |
39 | .width = 2, | |
40 | }; | |
41 | ||
42 | static struct resource mx27ads_flash_resource = { | |
43 | .start = 0xc0000000, | |
44 | .end = 0xc0000000 + 0x02000000 - 1, | |
45 | .flags = IORESOURCE_MEM, | |
46 | ||
47 | }; | |
48 | ||
49 | static struct platform_device mx27ads_nor_mtd_device = { | |
50 | .name = "physmap-flash", | |
51 | .id = 0, | |
52 | .dev = { | |
53 | .platform_data = &mx27ads_flash_data, | |
54 | }, | |
55 | .num_resources = 1, | |
56 | .resource = &mx27ads_flash_resource, | |
57 | }; | |
58 | ||
59 | static int mxc_uart0_pins[] = { | |
60 | PE12_PF_UART1_TXD, | |
61 | PE13_PF_UART1_RXD, | |
62 | PE14_PF_UART1_CTS, | |
63 | PE15_PF_UART1_RTS | |
64 | }; | |
65 | ||
66 | static int uart_mxc_port0_init(struct platform_device *pdev) | |
67 | { | |
68 | return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, | |
69 | ARRAY_SIZE(mxc_uart0_pins), | |
70 | MXC_GPIO_ALLOC_MODE_NORMAL, "UART0"); | |
71 | } | |
72 | ||
73 | static int uart_mxc_port0_exit(struct platform_device *pdev) | |
74 | { | |
75 | return mxc_gpio_setup_multiple_pins(mxc_uart0_pins, | |
76 | ARRAY_SIZE(mxc_uart0_pins), | |
77 | MXC_GPIO_ALLOC_MODE_RELEASE, "UART0"); | |
78 | } | |
79 | ||
80 | static int mxc_uart1_pins[] = { | |
81 | PE3_PF_UART2_CTS, | |
82 | PE4_PF_UART2_RTS, | |
83 | PE6_PF_UART2_TXD, | |
84 | PE7_PF_UART2_RXD | |
85 | }; | |
86 | ||
87 | static int uart_mxc_port1_init(struct platform_device *pdev) | |
88 | { | |
89 | return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, | |
90 | ARRAY_SIZE(mxc_uart1_pins), | |
91 | MXC_GPIO_ALLOC_MODE_NORMAL, "UART1"); | |
92 | } | |
93 | ||
94 | static int uart_mxc_port1_exit(struct platform_device *pdev) | |
95 | { | |
96 | return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, | |
97 | ARRAY_SIZE(mxc_uart1_pins), | |
98 | MXC_GPIO_ALLOC_MODE_RELEASE, "UART1"); | |
99 | } | |
100 | ||
101 | static int mxc_uart2_pins[] = { | |
102 | PE8_PF_UART3_TXD, | |
103 | PE9_PF_UART3_RXD, | |
104 | PE10_PF_UART3_CTS, | |
105 | PE11_PF_UART3_RTS | |
106 | }; | |
107 | ||
108 | static int uart_mxc_port2_init(struct platform_device *pdev) | |
109 | { | |
110 | return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, | |
111 | ARRAY_SIZE(mxc_uart2_pins), | |
112 | MXC_GPIO_ALLOC_MODE_NORMAL, "UART2"); | |
113 | } | |
114 | ||
115 | static int uart_mxc_port2_exit(struct platform_device *pdev) | |
116 | { | |
117 | return mxc_gpio_setup_multiple_pins(mxc_uart2_pins, | |
118 | ARRAY_SIZE(mxc_uart2_pins), | |
119 | MXC_GPIO_ALLOC_MODE_RELEASE, "UART2"); | |
120 | } | |
121 | ||
122 | static int mxc_uart3_pins[] = { | |
123 | PB26_AF_UART4_RTS, | |
124 | PB28_AF_UART4_TXD, | |
125 | PB29_AF_UART4_CTS, | |
126 | PB31_AF_UART4_RXD | |
127 | }; | |
128 | ||
129 | static int uart_mxc_port3_init(struct platform_device *pdev) | |
130 | { | |
131 | return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, | |
132 | ARRAY_SIZE(mxc_uart3_pins), | |
133 | MXC_GPIO_ALLOC_MODE_NORMAL, "UART3"); | |
134 | } | |
135 | ||
136 | static int uart_mxc_port3_exit(struct platform_device *pdev) | |
137 | { | |
138 | return mxc_gpio_setup_multiple_pins(mxc_uart3_pins, | |
139 | ARRAY_SIZE(mxc_uart3_pins), | |
140 | MXC_GPIO_ALLOC_MODE_RELEASE, "UART3"); | |
141 | } | |
142 | ||
143 | static int mxc_uart4_pins[] = { | |
144 | PB18_AF_UART5_TXD, | |
145 | PB19_AF_UART5_RXD, | |
146 | PB20_AF_UART5_CTS, | |
147 | PB21_AF_UART5_RTS | |
148 | }; | |
149 | ||
150 | static int uart_mxc_port4_init(struct platform_device *pdev) | |
151 | { | |
152 | return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, | |
153 | ARRAY_SIZE(mxc_uart4_pins), | |
154 | MXC_GPIO_ALLOC_MODE_NORMAL, "UART4"); | |
155 | } | |
156 | ||
157 | static int uart_mxc_port4_exit(struct platform_device *pdev) | |
158 | { | |
159 | return mxc_gpio_setup_multiple_pins(mxc_uart4_pins, | |
160 | ARRAY_SIZE(mxc_uart4_pins), | |
161 | MXC_GPIO_ALLOC_MODE_RELEASE, "UART4"); | |
162 | } | |
163 | ||
164 | static int mxc_uart5_pins[] = { | |
165 | PB10_AF_UART6_TXD, | |
166 | PB12_AF_UART6_CTS, | |
167 | PB11_AF_UART6_RXD, | |
168 | PB13_AF_UART6_RTS | |
169 | }; | |
170 | ||
171 | static int uart_mxc_port5_init(struct platform_device *pdev) | |
172 | { | |
173 | return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, | |
174 | ARRAY_SIZE(mxc_uart5_pins), | |
175 | MXC_GPIO_ALLOC_MODE_NORMAL, "UART5"); | |
176 | } | |
177 | ||
178 | static int uart_mxc_port5_exit(struct platform_device *pdev) | |
179 | { | |
180 | return mxc_gpio_setup_multiple_pins(mxc_uart5_pins, | |
181 | ARRAY_SIZE(mxc_uart5_pins), | |
182 | MXC_GPIO_ALLOC_MODE_RELEASE, "UART5"); | |
183 | } | |
184 | ||
185 | static struct platform_device *platform_devices[] __initdata = { | |
186 | &mx27ads_nor_mtd_device, | |
187 | }; | |
188 | ||
189 | static int mxc_fec_pins[] = { | |
190 | PD0_AIN_FEC_TXD0, | |
191 | PD1_AIN_FEC_TXD1, | |
192 | PD2_AIN_FEC_TXD2, | |
193 | PD3_AIN_FEC_TXD3, | |
194 | PD4_AOUT_FEC_RX_ER, | |
195 | PD5_AOUT_FEC_RXD1, | |
196 | PD6_AOUT_FEC_RXD2, | |
197 | PD7_AOUT_FEC_RXD3, | |
198 | PD8_AF_FEC_MDIO, | |
199 | PD9_AIN_FEC_MDC, | |
200 | PD10_AOUT_FEC_CRS, | |
201 | PD11_AOUT_FEC_TX_CLK, | |
202 | PD12_AOUT_FEC_RXD0, | |
203 | PD13_AOUT_FEC_RX_DV, | |
204 | PD14_AOUT_FEC_CLR, | |
205 | PD15_AOUT_FEC_COL, | |
206 | PD16_AIN_FEC_TX_ER, | |
207 | PF23_AIN_FEC_TX_EN | |
208 | }; | |
209 | ||
210 | static void gpio_fec_active(void) | |
211 | { | |
212 | mxc_gpio_setup_multiple_pins(mxc_fec_pins, | |
213 | ARRAY_SIZE(mxc_fec_pins), | |
214 | MXC_GPIO_ALLOC_MODE_NORMAL, "FEC"); | |
215 | } | |
216 | ||
217 | static void gpio_fec_inactive(void) | |
218 | { | |
219 | mxc_gpio_setup_multiple_pins(mxc_fec_pins, | |
220 | ARRAY_SIZE(mxc_fec_pins), | |
221 | MXC_GPIO_ALLOC_MODE_RELEASE, "FEC"); | |
222 | } | |
223 | ||
224 | static struct imxuart_platform_data uart_pdata[] = { | |
225 | { | |
226 | .init = uart_mxc_port0_init, | |
227 | .exit = uart_mxc_port0_exit, | |
228 | .flags = IMXUART_HAVE_RTSCTS, | |
229 | }, { | |
230 | .init = uart_mxc_port1_init, | |
231 | .exit = uart_mxc_port1_exit, | |
232 | .flags = IMXUART_HAVE_RTSCTS, | |
233 | }, { | |
234 | .init = uart_mxc_port2_init, | |
235 | .exit = uart_mxc_port2_exit, | |
236 | .flags = IMXUART_HAVE_RTSCTS, | |
237 | }, { | |
238 | .init = uart_mxc_port3_init, | |
239 | .exit = uart_mxc_port3_exit, | |
240 | .flags = IMXUART_HAVE_RTSCTS, | |
241 | }, { | |
242 | .init = uart_mxc_port4_init, | |
243 | .exit = uart_mxc_port4_exit, | |
244 | .flags = IMXUART_HAVE_RTSCTS, | |
245 | }, { | |
246 | .init = uart_mxc_port5_init, | |
247 | .exit = uart_mxc_port5_exit, | |
248 | .flags = IMXUART_HAVE_RTSCTS, | |
249 | }, | |
250 | }; | |
251 | ||
252 | static void __init mx27ads_board_init(void) | |
253 | { | |
254 | int i; | |
255 | ||
256 | gpio_fec_active(); | |
257 | ||
258 | for (i = 0; i < 6; i++) | |
259 | imx_init_uart(i, &uart_pdata[i]); | |
260 | ||
261 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | |
262 | } | |
263 | ||
264 | static void __init mx27ads_timer_init(void) | |
265 | { | |
266 | unsigned long fref = 26000000; | |
267 | ||
268 | if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) | |
269 | fref = 27000000; | |
270 | ||
271 | mxc_clocks_init(fref); | |
272 | mxc_timer_init("gpt_clk.0"); | |
273 | } | |
274 | ||
275 | struct sys_timer mx27ads_timer = { | |
276 | .init = mx27ads_timer_init, | |
277 | }; | |
278 | ||
279 | static struct map_desc mx27ads_io_desc[] __initdata = { | |
280 | { | |
281 | .virtual = PBC_BASE_ADDRESS, | |
282 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), | |
283 | .length = SZ_1M, | |
284 | .type = MT_DEVICE, | |
285 | }, | |
286 | }; | |
287 | ||
288 | void __init mx27ads_map_io(void) | |
289 | { | |
290 | mxc_map_io(); | |
291 | iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); | |
292 | } | |
293 | ||
294 | MACHINE_START(MX27ADS, "Freescale i.MX27ADS") | |
295 | /* maintainer: Freescale Semiconductor, Inc. */ | |
296 | .phys_io = AIPI_BASE_ADDR, | |
297 | .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, | |
298 | .boot_params = PHYS_OFFSET + 0x100, | |
299 | .map_io = mx27ads_map_io, | |
300 | .init_irq = mxc_init_irq, | |
301 | .init_machine = mx27ads_board_init, | |
302 | .timer = &mx27ads_timer, | |
303 | MACHINE_END | |
304 |