[deliverable/linux.git] / arch / arm / mach-mx2 / pcm038.c

/*
 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>

#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux.h>
#ifdef CONFIG_I2C_IMX
#include <mach/i2c.h>
#endif
#include <asm/mach/time.h>
#include <mach/imx-uart.h>
#include <mach/board-pcm038.h>
#include <mach/mxc_nand.h>

#include "devices.h"

/*
 * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
 * 16 bit width
 */

static struct platdata_mtd_ram pcm038_sram_data = {
	.bankwidth = 2,
};

static struct resource pcm038_sram_resource = {
	.start = CS1_BASE_ADDR,
	.end   = CS1_BASE_ADDR + 512 * 1024 - 1,
	.flags = IORESOURCE_MEM,
};

static struct platform_device pcm038_sram_mtd_device = {
	.name = "mtd-ram",
	.id = 0,
	.dev = {
		.platform_data = &pcm038_sram_data,
	},
	.num_resources = 1,
	.resource = &pcm038_sram_resource,
};

/*
 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
 * 16 bit width
 */
static struct physmap_flash_data pcm038_flash_data = {
	.width = 2,
};

static struct resource pcm038_flash_resource = {
	.start = 0xc0000000,
	.end   = 0xc1ffffff,
	.flags = IORESOURCE_MEM,
};

static struct platform_device pcm038_nor_mtd_device = {
	.name = "physmap-flash",
	.id = 0,
	.dev = {
		.platform_data = &pcm038_flash_data,
	},
	.num_resources = 1,
	.resource = &pcm038_flash_resource,
};

static int mxc_uart0_pins[] = {
	PE12_PF_UART1_TXD,
	PE13_PF_UART1_RXD,
	PE14_PF_UART1_CTS,
	PE15_PF_UART1_RTS
};

static int uart_mxc_port0_init(struct platform_device *pdev)
{
	return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
			ARRAY_SIZE(mxc_uart0_pins), "UART0");
}

static void uart_mxc_port0_exit(struct platform_device *pdev)
{
	mxc_gpio_release_multiple_pins(mxc_uart0_pins,
			ARRAY_SIZE(mxc_uart0_pins));
}

static int mxc_uart1_pins[] = {
	PE3_PF_UART2_CTS,
	PE4_PF_UART2_RTS,
	PE6_PF_UART2_TXD,
	PE7_PF_UART2_RXD
};

static int uart_mxc_port1_init(struct platform_device *pdev)
{
	return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
			ARRAY_SIZE(mxc_uart1_pins), "UART1");
}

static void uart_mxc_port1_exit(struct platform_device *pdev)
{
	mxc_gpio_release_multiple_pins(mxc_uart1_pins,
			ARRAY_SIZE(mxc_uart1_pins));
}

static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
				PE9_PF_UART3_RXD,
				PE10_PF_UART3_CTS,
				PE11_PF_UART3_RTS };

static int uart_mxc_port2_init(struct platform_device *pdev)
{
	return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
			ARRAY_SIZE(mxc_uart2_pins), "UART2");
}

static void uart_mxc_port2_exit(struct platform_device *pdev)
{
	mxc_gpio_release_multiple_pins(mxc_uart2_pins,
			ARRAY_SIZE(mxc_uart2_pins));
}

static struct imxuart_platform_data uart_pdata[] = {
	{
		.init = uart_mxc_port0_init,
		.exit = uart_mxc_port0_exit,
		.flags = IMXUART_HAVE_RTSCTS,
	}, {
		.init = uart_mxc_port1_init,
		.exit = uart_mxc_port1_exit,
		.flags = IMXUART_HAVE_RTSCTS,
	}, {
		.init = uart_mxc_port2_init,
		.exit = uart_mxc_port2_exit,
		.flags = IMXUART_HAVE_RTSCTS,
	},
};

static int mxc_fec_pins[] = {
	PD0_AIN_FEC_TXD0,
	PD1_AIN_FEC_TXD1,
	PD2_AIN_FEC_TXD2,
	PD3_AIN_FEC_TXD3,
	PD4_AOUT_FEC_RX_ER,
	PD5_AOUT_FEC_RXD1,
	PD6_AOUT_FEC_RXD2,
	PD7_AOUT_FEC_RXD3,
	PD8_AF_FEC_MDIO,
	PD9_AIN_FEC_MDC,
	PD10_AOUT_FEC_CRS,
	PD11_AOUT_FEC_TX_CLK,
	PD12_AOUT_FEC_RXD0,
	PD13_AOUT_FEC_RX_DV,
	PD14_AOUT_FEC_RX_CLK,
	PD15_AOUT_FEC_COL,
	PD16_AIN_FEC_TX_ER,
	PF23_AIN_FEC_TX_EN
};

static void gpio_fec_active(void)
{
	mxc_gpio_setup_multiple_pins(mxc_fec_pins,
			ARRAY_SIZE(mxc_fec_pins), "FEC");
}

static struct mxc_nand_platform_data pcm038_nand_board_info = {
	.width = 1,
	.hw_ecc = 1,
};

static struct platform_device *platform_devices[] __initdata = {
	&pcm038_nor_mtd_device,
	&mxc_w1_master_device,
	&mxc_fec_device,
	&pcm038_sram_mtd_device,
};

/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
 * setup other stuffs to access the sram. */
static void __init pcm038_init_sram(void)
{
	__raw_writel(0x0000d843, CSCR_U(1));
	__raw_writel(0x22252521, CSCR_L(1));
	__raw_writel(0x22220a00, CSCR_A(1));
}

#ifdef CONFIG_I2C_IMX
static int mxc_i2c1_pins[] = {
	PC5_PF_I2C2_SDA,
	PC6_PF_I2C2_SCL
};

static int pcm038_i2c_1_init(struct device *dev)
{
	return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
			"I2C1");
}

static void pcm038_i2c_1_exit(struct device *dev)
{
	mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
}

static struct imxi2c_platform_data pcm038_i2c_1_data = {
	.bitrate = 100000,
	.init = pcm038_i2c_1_init,
	.exit = pcm038_i2c_1_exit,
};

static struct at24_platform_data board_eeprom = {
	.byte_len = 4096,
	.page_size = 32,
	.flags = AT24_FLAG_ADDR16,
};

static struct i2c_board_info pcm038_i2c_devices[] = {
	[0] = {
		I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
		.platform_data = &board_eeprom,
	},
	[1] = {
		I2C_BOARD_INFO("rtc-pcf8563", 0x51),
		.type = "pcf8563"
	},
	[2] = {
		I2C_BOARD_INFO("lm75", 0x4a),
		.type = "lm75"
	}
};
#endif

static void __init pcm038_init(void)
{
	gpio_fec_active();
	pcm038_init_sram();

	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
	mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
	mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);

	mxc_gpio_mode(PE16_AF_OWIRE);
	mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);

#ifdef CONFIG_I2C_IMX
	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, pcm038_i2c_devices,
				ARRAY_SIZE(pcm038_i2c_devices));

	mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
#endif

	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

#ifdef CONFIG_MACH_PCM970_BASEBOARD
	pcm970_baseboard_init();
#endif
}

static void __init pcm038_timer_init(void)
{
	mx27_clocks_init(26000000);
}

static struct sys_timer pcm038_timer = {
	.init = pcm038_timer_init,
};

MACHINE_START(PCM038, "phyCORE-i.MX27")
	.phys_io        = AIPI_BASE_ADDR,
	.io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	.boot_params    = PHYS_OFFSET + 0x100,
	.map_io         = mx27_map_io,
	.init_irq       = mxc_init_irq,
	.init_machine   = pcm038_init,
	.timer          = &pcm038_timer,
MACHINE_END
Commit	Line	Data
7e5e9f54 JB	1	/*
	2	* Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
	3	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	* MA 02110-1301, USA.
	18	*/
	19
	20	#include <linux/platform_device.h>
	21	#include <linux/mtd/physmap.h>
3620c0dc	22	#include <linux/mtd/plat-ram.h>
ccfe30a7	23	#include <linux/io.h>
a4e9a65a SH	24	#include <linux/i2c.h>
	25	#include <linux/i2c/at24.h>
	26
7e5e9f54 JB	27	#include <asm/mach/arch.h>
7e5e9f54 JB	28	#include <asm/mach-types.h>
a09e64fb RK	29	#include <mach/common.h>
a09e64fb RK	30	#include <mach/hardware.h>
ccfe30a7	31	#include <mach/iomux.h>
a4e9a65a SH	32	#ifdef CONFIG_I2C_IMX
	33	#include <mach/i2c.h>
	34	#endif
7e5e9f54	35	#include <asm/mach/time.h>
a09e64fb RK	36	#include <mach/imx-uart.h>
a09e64fb RK	37	#include <mach/board-pcm038.h>
01f71a37	38	#include <mach/mxc_nand.h>
7e5e9f54	39
7e90534a SH	40	#include "devices.h"
7e90534a SH	41
3620c0dc SH	42	/*
	43	* Phytec's PCM038 comes with 2MiB battery buffered SRAM,
	44	* 16 bit width
	45	*/
	46
	47	static struct platdata_mtd_ram pcm038_sram_data = {
	48	.bankwidth = 2,
	49	};
	50
	51	static struct resource pcm038_sram_resource = {
	52	.start = CS1_BASE_ADDR,
	53	.end = CS1_BASE_ADDR + 512 * 1024 - 1,
	54	.flags = IORESOURCE_MEM,
	55	};
	56
	57	static struct platform_device pcm038_sram_mtd_device = {
	58	.name = "mtd-ram",
	59	.id = 0,
	60	.dev = {
	61	.platform_data = &pcm038_sram_data,
	62	},
	63	.num_resources = 1,
	64	.resource = &pcm038_sram_resource,
	65	};
	66
7e5e9f54 JB	67	/*
	68	* Phytec's phyCORE-i.MX27 comes with 32MiB flash,
	69	* 16 bit width
	70	*/
	71	static struct physmap_flash_data pcm038_flash_data = {
	72	.width = 2,
	73	};
	74
	75	static struct resource pcm038_flash_resource = {
	76	.start = 0xc0000000,
	77	.end = 0xc1ffffff,
	78	.flags = IORESOURCE_MEM,
	79	};
	80
	81	static struct platform_device pcm038_nor_mtd_device = {
	82	.name = "physmap-flash",
	83	.id = 0,
	84	.dev = {
	85	.platform_data = &pcm038_flash_data,
	86	},
	87	.num_resources = 1,
	88	.resource = &pcm038_flash_resource,
	89	};
	90
	91	static int mxc_uart0_pins[] = {
	92	PE12_PF_UART1_TXD,
	93	PE13_PF_UART1_RXD,
	94	PE14_PF_UART1_CTS,
	95	PE15_PF_UART1_RTS
	96	};
	97
	98	static int uart_mxc_port0_init(struct platform_device *pdev)
	99	{
	100	return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
7bd18221	101	ARRAY_SIZE(mxc_uart0_pins), "UART0");
7e5e9f54 JB	102	}
7e5e9f54 JB	103
fde36474	104	static void uart_mxc_port0_exit(struct platform_device *pdev)
7e5e9f54	105	{
7bd18221 SH	106	mxc_gpio_release_multiple_pins(mxc_uart0_pins,
7bd18221 SH	107	ARRAY_SIZE(mxc_uart0_pins));
7e5e9f54 JB	108	}
	109
	110	static int mxc_uart1_pins[] = {
	111	PE3_PF_UART2_CTS,
	112	PE4_PF_UART2_RTS,
	113	PE6_PF_UART2_TXD,
	114	PE7_PF_UART2_RXD
	115	};
	116
	117	static int uart_mxc_port1_init(struct platform_device *pdev)
	118	{
	119	return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
7bd18221	120	ARRAY_SIZE(mxc_uart1_pins), "UART1");
7e5e9f54 JB	121	}
7e5e9f54 JB	122
fde36474	123	static void uart_mxc_port1_exit(struct platform_device *pdev)
7e5e9f54	124	{
7bd18221 SH	125	mxc_gpio_release_multiple_pins(mxc_uart1_pins,
7bd18221 SH	126	ARRAY_SIZE(mxc_uart1_pins));
7e5e9f54 JB	127	}
7e5e9f54 JB	128
9a51157b	129	static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
7e5e9f54 JB	130	PE9_PF_UART3_RXD,
7e5e9f54 JB	131	PE10_PF_UART3_CTS,
9a51157b	132	PE11_PF_UART3_RTS };
7e5e9f54 JB	133
	134	static int uart_mxc_port2_init(struct platform_device *pdev)
	135	{
	136	return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
7bd18221	137	ARRAY_SIZE(mxc_uart2_pins), "UART2");
7e5e9f54 JB	138	}
7e5e9f54 JB	139
fde36474	140	static void uart_mxc_port2_exit(struct platform_device *pdev)
7e5e9f54	141	{
7bd18221 SH	142	mxc_gpio_release_multiple_pins(mxc_uart2_pins,
7bd18221 SH	143	ARRAY_SIZE(mxc_uart2_pins));
7e5e9f54 JB	144	}
	145
	146	static struct imxuart_platform_data uart_pdata[] = {
	147	{
	148	.init = uart_mxc_port0_init,
	149	.exit = uart_mxc_port0_exit,
	150	.flags = IMXUART_HAVE_RTSCTS,
	151	}, {
	152	.init = uart_mxc_port1_init,
	153	.exit = uart_mxc_port1_exit,
	154	.flags = IMXUART_HAVE_RTSCTS,
	155	}, {
	156	.init = uart_mxc_port2_init,
	157	.exit = uart_mxc_port2_exit,
	158	.flags = IMXUART_HAVE_RTSCTS,
	159	},
	160	};
	161
	162	static int mxc_fec_pins[] = {
	163	PD0_AIN_FEC_TXD0,
	164	PD1_AIN_FEC_TXD1,
	165	PD2_AIN_FEC_TXD2,
	166	PD3_AIN_FEC_TXD3,
	167	PD4_AOUT_FEC_RX_ER,
	168	PD5_AOUT_FEC_RXD1,
	169	PD6_AOUT_FEC_RXD2,
	170	PD7_AOUT_FEC_RXD3,
	171	PD8_AF_FEC_MDIO,
	172	PD9_AIN_FEC_MDC,
	173	PD10_AOUT_FEC_CRS,
	174	PD11_AOUT_FEC_TX_CLK,
	175	PD12_AOUT_FEC_RXD0,
	176	PD13_AOUT_FEC_RX_DV,
ccfe30a7	177	PD14_AOUT_FEC_RX_CLK,
7e5e9f54 JB	178	PD15_AOUT_FEC_COL,
	179	PD16_AIN_FEC_TX_ER,
	180	PF23_AIN_FEC_TX_EN
	181	};
	182
	183	static void gpio_fec_active(void)
	184	{
	185	mxc_gpio_setup_multiple_pins(mxc_fec_pins,
7bd18221	186	ARRAY_SIZE(mxc_fec_pins), "FEC");
7e5e9f54 JB	187	}
7e5e9f54 JB	188
01f71a37 SH	189	static struct mxc_nand_platform_data pcm038_nand_board_info = {
	190	.width = 1,
	191	.hw_ecc = 1,
	192	};
	193
7e5e9f54 JB	194	static struct platform_device *platform_devices[] __initdata = {
7e5e9f54 JB	195	&pcm038_nor_mtd_device,
d40a0992	196	&mxc_w1_master_device,
879fea1b	197	&mxc_fec_device,
3620c0dc	198	&pcm038_sram_mtd_device,
7e5e9f54 JB	199	};
7e5e9f54 JB	200
3620c0dc SH	201	/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
	202	* setup other stuffs to access the sram. */
	203	static void __init pcm038_init_sram(void)
	204	{
	205	__raw_writel(0x0000d843, CSCR_U(1));
	206	__raw_writel(0x22252521, CSCR_L(1));
	207	__raw_writel(0x22220a00, CSCR_A(1));
	208	}
	209
a4e9a65a SH	210	#ifdef CONFIG_I2C_IMX
	211	static int mxc_i2c1_pins[] = {
	212	PC5_PF_I2C2_SDA,
	213	PC6_PF_I2C2_SCL
	214	};
	215
	216	static int pcm038_i2c_1_init(struct device *dev)
	217	{
	218	return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
	219	"I2C1");
	220	}
	221
	222	static void pcm038_i2c_1_exit(struct device *dev)
	223	{
	224	mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
	225	}
	226
	227	static struct imxi2c_platform_data pcm038_i2c_1_data = {
	228	.bitrate = 100000,
	229	.init = pcm038_i2c_1_init,
	230	.exit = pcm038_i2c_1_exit,
	231	};
	232
	233	static struct at24_platform_data board_eeprom = {
	234	.byte_len = 4096,
	235	.page_size = 32,
	236	.flags = AT24_FLAG_ADDR16,
	237	};
	238
	239	static struct i2c_board_info pcm038_i2c_devices[] = {
	240	[0] = {
	241	I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
	242	.platform_data = &board_eeprom,
	243	},
	244	[1] = {
	245	I2C_BOARD_INFO("rtc-pcf8563", 0x51),
	246	.type = "pcf8563"
	247	},
	248	[2] = {
	249	I2C_BOARD_INFO("lm75", 0x4a),
	250	.type = "lm75"
	251	}
	252	};
	253	#endif
	254
7e5e9f54 JB	255	static void __init pcm038_init(void)
7e5e9f54 JB	256	{
7e5e9f54	257	gpio_fec_active();
3620c0dc	258	pcm038_init_sram();
7e5e9f54	259
7e90534a SH	260	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
	261	mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
	262	mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
01f71a37	263
ccfe30a7	264	mxc_gpio_mode(PE16_AF_OWIRE);
01f71a37	265	mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
7e5e9f54	266
a4e9a65a SH	267	#ifdef CONFIG_I2C_IMX
	268	/* only the i2c master 1 is used on this CPU card */
	269	i2c_register_board_info(1, pcm038_i2c_devices,
	270	ARRAY_SIZE(pcm038_i2c_devices));
	271
	272	mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
	273	#endif
	274
7e5e9f54	275	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
ff6552e4 JB	276
	277	#ifdef CONFIG_MACH_PCM970_BASEBOARD
	278	pcm970_baseboard_init();
	279	#endif
7e5e9f54 JB	280	}
	281
	282	static void __init pcm038_timer_init(void)
	283	{
30c730f8	284	mx27_clocks_init(26000000);
7e5e9f54 JB	285	}
7e5e9f54 JB	286
058b7a6f	287	static struct sys_timer pcm038_timer = {
7e5e9f54 JB	288	.init = pcm038_timer_init,
	289	};
	290
	291	MACHINE_START(PCM038, "phyCORE-i.MX27")
	292	.phys_io = AIPI_BASE_ADDR,
	293	.io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	294	.boot_params = PHYS_OFFSET + 0x100,
cd4a05f9	295	.map_io = mx27_map_io,
7e5e9f54 JB	296	.init_irq = mxc_init_irq,
	297	.init_machine = pcm038_init,
	298	.timer = &pcm038_timer,
	299	MACHINE_END