[deliverable/linux.git] / arch / arm / mach-mx3 / devices.c

/*
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
 * Boston, MA  02110-1301, USA.
 */

#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/mx3_camera.h>

#include "devices.h"

static struct resource uart0[] = {
	{
		.start = UART1_BASE_ADDR,
		.end = UART1_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART1,
		.end = MXC_INT_UART1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device0 = {
	.name = "imx-uart",
	.id = 0,
	.resource = uart0,
	.num_resources = ARRAY_SIZE(uart0),
};

static struct resource uart1[] = {
	{
		.start = UART2_BASE_ADDR,
		.end = UART2_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART2,
		.end = MXC_INT_UART2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device1 = {
	.name = "imx-uart",
	.id = 1,
	.resource = uart1,
	.num_resources = ARRAY_SIZE(uart1),
};

static struct resource uart2[] = {
	{
		.start = UART3_BASE_ADDR,
		.end = UART3_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART3,
		.end = MXC_INT_UART3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device2 = {
	.name = "imx-uart",
	.id = 2,
	.resource = uart2,
	.num_resources = ARRAY_SIZE(uart2),
};

#ifdef CONFIG_ARCH_MX31
static struct resource uart3[] = {
	{
		.start = UART4_BASE_ADDR,
		.end = UART4_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART4,
		.end = MXC_INT_UART4,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device3 = {
	.name = "imx-uart",
	.id = 3,
	.resource = uart3,
	.num_resources = ARRAY_SIZE(uart3),
};

static struct resource uart4[] = {
	{
		.start = UART5_BASE_ADDR,
		.end = UART5_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART5,
		.end = MXC_INT_UART5,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device4 = {
	.name = "imx-uart",
	.id = 4,
	.resource = uart4,
	.num_resources = ARRAY_SIZE(uart4),
};
#endif /* CONFIG_ARCH_MX31 */

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	{
		.chip.label = "gpio-0",
		.base = IO_ADDRESS(GPIO1_BASE_ADDR),
		.irq = MXC_INT_GPIO1,
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	}, {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO2_BASE_ADDR),
		.irq = MXC_INT_GPIO2,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	}, {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO3_BASE_ADDR),
		.irq = MXC_INT_GPIO3,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= 0, /* runtime dependent */
		.end	= 0,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

static struct resource mxc_i2c0_resources[] = {
	{
		.start = I2C_BASE_ADDR,
		.end = I2C_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_I2C,
		.end = MXC_INT_I2C,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	.resource = mxc_i2c0_resources,
};

static struct resource mxc_i2c1_resources[] = {
	{
		.start = I2C2_BASE_ADDR,
		.end = I2C2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_I2C2,
		.end = MXC_INT_I2C2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	.resource = mxc_i2c1_resources,
};

static struct resource mxc_i2c2_resources[] = {
	{
		.start = I2C3_BASE_ADDR,
		.end = I2C3_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_I2C3,
		.end = MXC_INT_I2C3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device2 = {
	.name = "imx-i2c",
	.id = 2,
	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	.resource = mxc_i2c2_resources,
};

#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
	{
		.start = MMC_SDHC1_BASE_ADDR,
		.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC1,
		.end = MXC_INT_MMC_SDHC1,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxcsdhc1_resources[] = {
	{
		.start = MMC_SDHC2_BASE_ADDR,
		.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC2,
		.end = MXC_INT_MMC_SDHC2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxcsdhc_device0 = {
	.name = "mxc-mmc",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	.resource = mxcsdhc0_resources,
};

struct platform_device mxcsdhc_device1 = {
	.name = "mxc-mmc",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	.resource = mxcsdhc1_resources,
};

static struct resource rnga_resources[] = {
	{
		.start = RNGA_BASE_ADDR,
		.end = RNGA_BASE_ADDR + 0x28,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_rnga_device = {
	.name = "mxc_rnga",
	.id = -1,
	.num_resources = 1,
	.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */

/* i.MX31 Image Processing Unit */

/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
	{
		.start = IPU_CTRL_BASE_ADDR,
		.end = IPU_CTRL_BASE_ADDR + 0x5F,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IPU_CTRL_BASE_ADDR + 0x88,
		.end = IPU_CTRL_BASE_ADDR + 0xB3,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_IPU_SYN,
		.end = MXC_INT_IPU_SYN,
		.flags = IORESOURCE_IRQ,
	}, {
		.start = MXC_INT_IPU_ERR,
		.end = MXC_INT_IPU_ERR,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mx3_ipu = {
	.name = "ipu-core",
	.id = -1,
	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	.resource = mx3_ipu_rsrc,
};

static struct resource fb_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0xB4,
		.end	= IPU_CTRL_BASE_ADDR + 0x1BF,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_fb = {
	.name		= "mx3_sdc_fb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(fb_resources),
	.resource	= fb_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
       },
};

static struct resource camera_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0x60,
		.end	= IPU_CTRL_BASE_ADDR + 0x87,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_camera = {
	.name		= "mx3-camera",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(camera_resources),
	.resource	= camera_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

static struct resource otg_resources[] = {
	{
		.start	= MX31_OTG_BASE_ADDR,
		.end	= MX31_OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

/* OTG host */
struct platform_device mxc_otg_host = {
	.name = "mxc-ehci",
	.id = 0,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &otg_dmamask,
	},
	.resource = otg_resources,
	.num_resources = ARRAY_SIZE(otg_resources),
};

/* USB host 1 */

static u64 usbh1_dmamask = ~(u32)0;

static struct resource mxc_usbh1_resources[] = {
	{
		.start = MX31_OTG_BASE_ADDR + 0x200,
		.end = MX31_OTG_BASE_ADDR + 0x3ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB1,
		.end = MXC_INT_USB1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh1 = {
	.name = "mxc-ehci",
	.id = 1,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh1_dmamask,
	},
	.resource = mxc_usbh1_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
};

/* USB host 2 */
static u64 usbh2_dmamask = ~(u32)0;

static struct resource mxc_usbh2_resources[] = {
	{
		.start = MX31_OTG_BASE_ADDR + 0x400,
		.end = MX31_OTG_BASE_ADDR + 0x5ff,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_USB2,
		.end = MXC_INT_USB2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_usbh2 = {
	.name = "mxc-ehci",
	.id = 2,
	.dev = {
		.coherent_dma_mask = 0xffffffff,
		.dma_mask = &usbh2_dmamask,
	},
	.resource = mxc_usbh2_resources,
	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
};

/*
 * SPI master controller
 * 3 channels
 */
static struct resource mxc_spi_0_resources[] = {
	{
	       .start = CSPI1_BASE_ADDR,
	       .end = CSPI1_BASE_ADDR + SZ_4K - 1,
	       .flags = IORESOURCE_MEM,
	}, {
	       .start = MXC_INT_CSPI1,
	       .end = MXC_INT_CSPI1,
	       .flags = IORESOURCE_IRQ,
	},
};

static struct resource mxc_spi_1_resources[] = {
	{
		.start = CSPI2_BASE_ADDR,
		.end = CSPI2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_CSPI2,
		.end = MXC_INT_CSPI2,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxc_spi_2_resources[] = {
	{
		.start = CSPI3_BASE_ADDR,
		.end = CSPI3_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_CSPI3,
		.end = MXC_INT_CSPI3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_spi_device0 = {
	.name = "spi_imx",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_spi_0_resources),
	.resource = mxc_spi_0_resources,
};

struct platform_device mxc_spi_device1 = {
	.name = "spi_imx",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_spi_1_resources),
	.resource = mxc_spi_1_resources,
};

struct platform_device mxc_spi_device2 = {
	.name = "spi_imx",
	.id = 2,
	.num_resources = ARRAY_SIZE(mxc_spi_2_resources),
	.resource = mxc_spi_2_resources,
};

#ifdef CONFIG_ARCH_MX35
static struct resource mxc_fec_resources[] = {
	{
		.start	= MXC_FEC_BASE_ADDR,
		.end	= MXC_FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static struct resource imx_ssi_resources0[] = {
	{
		.start	= SSI1_BASE_ADDR,
		.end	= SSI1_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MX31_INT_SSI1,
		.end	= MX31_INT_SSI1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct resource imx_ssi_resources1[] = {
	{
		.start	= SSI2_BASE_ADDR,
		.end	= SSI2_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MX31_INT_SSI2,
		.end	= MX31_INT_SSI2,
		.flags	= IORESOURCE_IRQ,
	},
};

struct platform_device imx_ssi_device0 = {
	.name = "imx-ssi",
	.id = 0,
	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
	.resource = imx_ssi_resources0,
};

struct platform_device imx_ssi_device1 = {
	.name = "imx-ssi",
	.id = 1,
	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
	.resource = imx_ssi_resources1,
};

static int mx3_devices_init(void)
{
	if (cpu_is_mx31()) {
		mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
		mxc_register_device(&mxc_rnga_device, NULL);
	}
	if (cpu_is_mx35()) {
		mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
		otg_resources[0].start = MX35_OTG_BASE_ADDR;
		otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
		otg_resources[1].start = MXC_INT_USBOTG;
		otg_resources[1].end = MXC_INT_USBOTG;
		mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
		mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
		mxc_usbh1_resources[1].start = MXC_INT_USBHS;
		mxc_usbh1_resources[1].end = MXC_INT_USBHS;
		imx_ssi_resources0[1].start = MX35_INT_SSI1;
		imx_ssi_resources0[1].end = MX35_INT_SSI1;
		imx_ssi_resources1[1].start = MX35_INT_SSI2;
		imx_ssi_resources1[1].end = MX35_INT_SSI2;
	}

	return 0;
}

subsys_initcall(mx3_devices_init);
Commit	Line	Data
e3d13ff4 SH	1	/*
	2	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor,
	17	* Boston, MA 02110-1301, USA.
	18	*/
	19
eb05bbeb	20	#include <linux/dma-mapping.h>
e3d13ff4 SH	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/serial.h>
07bd1a6c	24	#include <linux/gpio.h>
a09e64fb	25	#include <mach/hardware.h>
80b02c17	26	#include <mach/irqs.h>
45001e92	27	#include <mach/common.h>
a09e64fb	28	#include <mach/imx-uart.h>
9c70e227	29	#include <mach/mx3_camera.h>
e3d13ff4	30
87bbb197 SH	31	#include "devices.h"
87bbb197 SH	32
e3d13ff4 SH	33	static struct resource uart0[] = {
	34	{
	35	.start = UART1_BASE_ADDR,
	36	.end = UART1_BASE_ADDR + 0x0B5,
	37	.flags = IORESOURCE_MEM,
	38	}, {
	39	.start = MXC_INT_UART1,
	40	.end = MXC_INT_UART1,
	41	.flags = IORESOURCE_IRQ,
	42	},
	43	};
	44
5cf09421	45	struct platform_device mxc_uart_device0 = {
e3d13ff4 SH	46	.name = "imx-uart",
	47	.id = 0,
	48	.resource = uart0,
	49	.num_resources = ARRAY_SIZE(uart0),
	50	};
	51
	52	static struct resource uart1[] = {
	53	{
	54	.start = UART2_BASE_ADDR,
	55	.end = UART2_BASE_ADDR + 0x0B5,
	56	.flags = IORESOURCE_MEM,
	57	}, {
	58	.start = MXC_INT_UART2,
	59	.end = MXC_INT_UART2,
	60	.flags = IORESOURCE_IRQ,
	61	},
	62	};
	63
5cf09421	64	struct platform_device mxc_uart_device1 = {
e3d13ff4 SH	65	.name = "imx-uart",
	66	.id = 1,
	67	.resource = uart1,
	68	.num_resources = ARRAY_SIZE(uart1),
	69	};
	70
	71	static struct resource uart2[] = {
	72	{
	73	.start = UART3_BASE_ADDR,
	74	.end = UART3_BASE_ADDR + 0x0B5,
	75	.flags = IORESOURCE_MEM,
	76	}, {
	77	.start = MXC_INT_UART3,
	78	.end = MXC_INT_UART3,
	79	.flags = IORESOURCE_IRQ,
	80	},
	81	};
	82
5cf09421	83	struct platform_device mxc_uart_device2 = {
e3d13ff4 SH	84	.name = "imx-uart",
	85	.id = 2,
	86	.resource = uart2,
	87	.num_resources = ARRAY_SIZE(uart2),
	88	};
	89
9536ff33	90	#ifdef CONFIG_ARCH_MX31
e3d13ff4 SH	91	static struct resource uart3[] = {
	92	{
	93	.start = UART4_BASE_ADDR,
	94	.end = UART4_BASE_ADDR + 0x0B5,
	95	.flags = IORESOURCE_MEM,
	96	}, {
	97	.start = MXC_INT_UART4,
	98	.end = MXC_INT_UART4,
	99	.flags = IORESOURCE_IRQ,
	100	},
	101	};
	102
5cf09421	103	struct platform_device mxc_uart_device3 = {
e3d13ff4 SH	104	.name = "imx-uart",
	105	.id = 3,
	106	.resource = uart3,
	107	.num_resources = ARRAY_SIZE(uart3),
	108	};
	109
	110	static struct resource uart4[] = {
	111	{
	112	.start = UART5_BASE_ADDR,
	113	.end = UART5_BASE_ADDR + 0x0B5,
	114	.flags = IORESOURCE_MEM,
	115	}, {
	116	.start = MXC_INT_UART5,
	117	.end = MXC_INT_UART5,
	118	.flags = IORESOURCE_IRQ,
	119	},
	120	};
	121
5cf09421	122	struct platform_device mxc_uart_device4 = {
e3d13ff4 SH	123	.name = "imx-uart",
	124	.id = 4,
	125	.resource = uart4,
	126	.num_resources = ARRAY_SIZE(uart4),
	127	};
9536ff33	128	#endif /* CONFIG_ARCH_MX31 */
e3d13ff4	129
07bd1a6c JB	130	/* GPIO port description */
07bd1a6c JB	131	static struct mxc_gpio_port imx_gpio_ports[] = {
3f4f54b4	132	{
07bd1a6c JB	133	.chip.label = "gpio-0",
	134	.base = IO_ADDRESS(GPIO1_BASE_ADDR),
	135	.irq = MXC_INT_GPIO1,
9d631b83	136	.virtual_irq_start = MXC_GPIO_IRQ_START,
3f4f54b4	137	}, {
07bd1a6c JB	138	.chip.label = "gpio-1",
	139	.base = IO_ADDRESS(GPIO2_BASE_ADDR),
	140	.irq = MXC_INT_GPIO2,
9d631b83	141	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
3f4f54b4	142	}, {
07bd1a6c JB	143	.chip.label = "gpio-2",
	144	.base = IO_ADDRESS(GPIO3_BASE_ADDR),
	145	.irq = MXC_INT_GPIO3,
9d631b83	146	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
07bd1a6c JB	147	}
	148	};
	149
	150	int __init mxc_register_gpios(void)
	151	{
	152	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	153	}
a8405929 SH	154
	155	static struct resource mxc_w1_master_resources[] = {
	156	{
	157	.start = OWIRE_BASE_ADDR,
	158	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	159	.flags = IORESOURCE_MEM,
	160	},
	161	};
	162
	163	struct platform_device mxc_w1_master_device = {
	164	.name = "mxc_w1",
	165	.id = 0,
	166	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	167	.resource = mxc_w1_master_resources,
	168	};
cb96cf1a SH	169
	170	static struct resource mxc_nand_resources[] = {
	171	{
9536ff33 SH	172	.start = 0, /* runtime dependent */
9536ff33 SH	173	.end = 0,
3f4f54b4	174	.flags = IORESOURCE_MEM,
cb96cf1a SH	175	}, {
	176	.start = MXC_INT_NANDFC,
	177	.end = MXC_INT_NANDFC,
3f4f54b4	178	.flags = IORESOURCE_IRQ,
cb96cf1a SH	179	},
	180	};
	181
	182	struct platform_device mxc_nand_device = {
	183	.name = "mxc_nand",
	184	.id = 0,
	185	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	186	.resource = mxc_nand_resources,
	187	};
39d1dc06 MB	188
	189	static struct resource mxc_i2c0_resources[] = {
	190	{
	191	.start = I2C_BASE_ADDR,
	192	.end = I2C_BASE_ADDR + SZ_4K - 1,
	193	.flags = IORESOURCE_MEM,
3f4f54b4	194	}, {
39d1dc06 MB	195	.start = MXC_INT_I2C,
	196	.end = MXC_INT_I2C,
	197	.flags = IORESOURCE_IRQ,
	198	},
	199	};
	200
	201	struct platform_device mxc_i2c_device0 = {
	202	.name = "imx-i2c",
	203	.id = 0,
	204	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	205	.resource = mxc_i2c0_resources,
	206	};
	207
	208	static struct resource mxc_i2c1_resources[] = {
	209	{
	210	.start = I2C2_BASE_ADDR,
	211	.end = I2C2_BASE_ADDR + SZ_4K - 1,
	212	.flags = IORESOURCE_MEM,
3f4f54b4	213	}, {
39d1dc06 MB	214	.start = MXC_INT_I2C2,
	215	.end = MXC_INT_I2C2,
	216	.flags = IORESOURCE_IRQ,
	217	},
	218	};
	219
	220	struct platform_device mxc_i2c_device1 = {
	221	.name = "imx-i2c",
	222	.id = 1,
	223	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	224	.resource = mxc_i2c1_resources,
	225	};
	226
	227	static struct resource mxc_i2c2_resources[] = {
	228	{
	229	.start = I2C3_BASE_ADDR,
	230	.end = I2C3_BASE_ADDR + SZ_4K - 1,
	231	.flags = IORESOURCE_MEM,
3f4f54b4	232	}, {
39d1dc06 MB	233	.start = MXC_INT_I2C3,
	234	.end = MXC_INT_I2C3,
	235	.flags = IORESOURCE_IRQ,
	236	},
	237	};
	238
	239	struct platform_device mxc_i2c_device2 = {
	240	.name = "imx-i2c",
	241	.id = 2,
	242	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	243	.resource = mxc_i2c2_resources,
	244	};
ca489f8e	245
2adc1d65 SH	246	#ifdef CONFIG_ARCH_MX31
	247	static struct resource mxcsdhc0_resources[] = {
	248	{
	249	.start = MMC_SDHC1_BASE_ADDR,
	250	.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
	251	.flags = IORESOURCE_MEM,
	252	}, {
	253	.start = MXC_INT_MMC_SDHC1,
	254	.end = MXC_INT_MMC_SDHC1,
	255	.flags = IORESOURCE_IRQ,
	256	},
	257	};
	258
	259	static struct resource mxcsdhc1_resources[] = {
	260	{
	261	.start = MMC_SDHC2_BASE_ADDR,
	262	.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
	263	.flags = IORESOURCE_MEM,
	264	}, {
	265	.start = MXC_INT_MMC_SDHC2,
	266	.end = MXC_INT_MMC_SDHC2,
	267	.flags = IORESOURCE_IRQ,
	268	},
	269	};
	270
	271	struct platform_device mxcsdhc_device0 = {
	272	.name = "mxc-mmc",
	273	.id = 0,
	274	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	275	.resource = mxcsdhc0_resources,
	276	};
	277
	278	struct platform_device mxcsdhc_device1 = {
	279	.name = "mxc-mmc",
	280	.id = 1,
	281	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	282	.resource = mxcsdhc1_resources,
	283	};
45001e92 ACA	284
	285	static struct resource rnga_resources[] = {
	286	{
	287	.start = RNGA_BASE_ADDR,
	288	.end = RNGA_BASE_ADDR + 0x28,
	289	.flags = IORESOURCE_MEM,
	290	},
	291	};
	292
	293	struct platform_device mxc_rnga_device = {
	294	.name = "mxc_rnga",
	295	.id = -1,
	296	.num_resources = 1,
	297	.resource = rnga_resources,
	298	};
2adc1d65 SH	299	#endif /* CONFIG_ARCH_MX31 */
2adc1d65 SH	300
ca489f8e VL	301	/* i.MX31 Image Processing Unit */
	302
	303	/* The resource order is important! */
	304	static struct resource mx3_ipu_rsrc[] = {
	305	{
	306	.start = IPU_CTRL_BASE_ADDR,
	307	.end = IPU_CTRL_BASE_ADDR + 0x5F,
	308	.flags = IORESOURCE_MEM,
	309	}, {
	310	.start = IPU_CTRL_BASE_ADDR + 0x88,
	311	.end = IPU_CTRL_BASE_ADDR + 0xB3,
	312	.flags = IORESOURCE_MEM,
	313	}, {
	314	.start = MXC_INT_IPU_SYN,
	315	.end = MXC_INT_IPU_SYN,
	316	.flags = IORESOURCE_IRQ,
	317	}, {
	318	.start = MXC_INT_IPU_ERR,
	319	.end = MXC_INT_IPU_ERR,
	320	.flags = IORESOURCE_IRQ,
	321	},
	322	};
	323
	324	struct platform_device mx3_ipu = {
	325	.name = "ipu-core",
	326	.id = -1,
	327	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	328	.resource = mx3_ipu_rsrc,
	329	};
	330
	331	static struct resource fb_resources[] = {
	332	{
	333	.start = IPU_CTRL_BASE_ADDR + 0xB4,
	334	.end = IPU_CTRL_BASE_ADDR + 0x1BF,
	335	.flags = IORESOURCE_MEM,
	336	},
	337	};
	338
	339	struct platform_device mx3_fb = {
	340	.name = "mx3_sdc_fb",
	341	.id = -1,
	342	.num_resources = ARRAY_SIZE(fb_resources),
	343	.resource = fb_resources,
	344	.dev = {
9c70e227	345	.coherent_dma_mask = DMA_BIT_MASK(32),
ca489f8e VL	346	},
ca489f8e VL	347	};
9536ff33	348
9c70e227 VL	349	static struct resource camera_resources[] = {
	350	{
	351	.start = IPU_CTRL_BASE_ADDR + 0x60,
	352	.end = IPU_CTRL_BASE_ADDR + 0x87,
	353	.flags = IORESOURCE_MEM,
	354	},
	355	};
	356
	357	struct platform_device mx3_camera = {
	358	.name = "mx3-camera",
	359	.id = 0,
	360	.num_resources = ARRAY_SIZE(camera_resources),
	361	.resource = camera_resources,
	362	.dev = {
	363	.coherent_dma_mask = DMA_BIT_MASK(32),
	364	},
	365	};
	366
eb05bbeb GL	367	static struct resource otg_resources[] = {
eb05bbeb GL	368	{
7bc07ebc SH	369	.start = MX31_OTG_BASE_ADDR,
7bc07ebc SH	370	.end = MX31_OTG_BASE_ADDR + 0x1ff,
eb05bbeb GL	371	.flags = IORESOURCE_MEM,
	372	}, {
	373	.start = MXC_INT_USB3,
	374	.end = MXC_INT_USB3,
	375	.flags = IORESOURCE_IRQ,
	376	},
	377	};
	378
	379	static u64 otg_dmamask = DMA_BIT_MASK(32);
	380
	381	/* OTG gadget device */
	382	struct platform_device mxc_otg_udc_device = {
	383	.name = "fsl-usb2-udc",
	384	.id = -1,
	385	.dev = {
	386	.dma_mask = &otg_dmamask,
	387	.coherent_dma_mask = DMA_BIT_MASK(32),
	388	},
	389	.resource = otg_resources,
	390	.num_resources = ARRAY_SIZE(otg_resources),
	391	};
	392
c13a482c DM	393	/* OTG host */
	394	struct platform_device mxc_otg_host = {
	395	.name = "mxc-ehci",
	396	.id = 0,
	397	.dev = {
	398	.coherent_dma_mask = 0xffffffff,
	399	.dma_mask = &otg_dmamask,
	400	},
	401	.resource = otg_resources,
	402	.num_resources = ARRAY_SIZE(otg_resources),
	403	};
	404
	405	/* USB host 1 */
	406
	407	static u64 usbh1_dmamask = ~(u32)0;
	408
	409	static struct resource mxc_usbh1_resources[] = {
	410	{
7bc07ebc SH	411	.start = MX31_OTG_BASE_ADDR + 0x200,
7bc07ebc SH	412	.end = MX31_OTG_BASE_ADDR + 0x3ff,
c13a482c DM	413	.flags = IORESOURCE_MEM,
	414	}, {
	415	.start = MXC_INT_USB1,
	416	.end = MXC_INT_USB1,
	417	.flags = IORESOURCE_IRQ,
	418	},
	419	};
	420
	421	struct platform_device mxc_usbh1 = {
	422	.name = "mxc-ehci",
	423	.id = 1,
	424	.dev = {
	425	.coherent_dma_mask = 0xffffffff,
	426	.dma_mask = &usbh1_dmamask,
	427	},
	428	.resource = mxc_usbh1_resources,
	429	.num_resources = ARRAY_SIZE(mxc_usbh1_resources),
	430	};
	431
	432	/* USB host 2 */
	433	static u64 usbh2_dmamask = ~(u32)0;
	434
	435	static struct resource mxc_usbh2_resources[] = {
	436	{
7bc07ebc SH	437	.start = MX31_OTG_BASE_ADDR + 0x400,
7bc07ebc SH	438	.end = MX31_OTG_BASE_ADDR + 0x5ff,
c13a482c DM	439	.flags = IORESOURCE_MEM,
	440	}, {
	441	.start = MXC_INT_USB2,
	442	.end = MXC_INT_USB2,
	443	.flags = IORESOURCE_IRQ,
	444	},
	445	};
	446
	447	struct platform_device mxc_usbh2 = {
	448	.name = "mxc-ehci",
	449	.id = 2,
	450	.dev = {
	451	.coherent_dma_mask = 0xffffffff,
	452	.dma_mask = &usbh2_dmamask,
	453	},
	454	.resource = mxc_usbh2_resources,
	455	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
	456	};
	457
d37ba97d SH	458	/*
	459	* SPI master controller
	460	* 3 channels
	461	*/
d9e8b884	462	static struct resource mxc_spi_0_resources[] = {
d37ba97d SH	463	{
	464	.start = CSPI1_BASE_ADDR,
	465	.end = CSPI1_BASE_ADDR + SZ_4K - 1,
	466	.flags = IORESOURCE_MEM,
	467	}, {
	468	.start = MXC_INT_CSPI1,
	469	.end = MXC_INT_CSPI1,
	470	.flags = IORESOURCE_IRQ,
	471	},
	472	};
	473
d9e8b884	474	static struct resource mxc_spi_1_resources[] = {
d37ba97d SH	475	{
	476	.start = CSPI2_BASE_ADDR,
	477	.end = CSPI2_BASE_ADDR + SZ_4K - 1,
	478	.flags = IORESOURCE_MEM,
	479	}, {
	480	.start = MXC_INT_CSPI2,
	481	.end = MXC_INT_CSPI2,
	482	.flags = IORESOURCE_IRQ,
	483	},
	484	};
	485
d9e8b884	486	static struct resource mxc_spi_2_resources[] = {
d37ba97d SH	487	{
	488	.start = CSPI3_BASE_ADDR,
	489	.end = CSPI3_BASE_ADDR + SZ_4K - 1,
	490	.flags = IORESOURCE_MEM,
	491	}, {
	492	.start = MXC_INT_CSPI3,
	493	.end = MXC_INT_CSPI3,
	494	.flags = IORESOURCE_IRQ,
	495	},
	496	};
	497
d9e8b884	498	struct platform_device mxc_spi_device0 = {
d37ba97d SH	499	.name = "spi_imx",
d37ba97d SH	500	.id = 0,
d9e8b884 GL	501	.num_resources = ARRAY_SIZE(mxc_spi_0_resources),
d9e8b884 GL	502	.resource = mxc_spi_0_resources,
d37ba97d SH	503	};
d37ba97d SH	504
d9e8b884	505	struct platform_device mxc_spi_device1 = {
d37ba97d SH	506	.name = "spi_imx",
d37ba97d SH	507	.id = 1,
d9e8b884 GL	508	.num_resources = ARRAY_SIZE(mxc_spi_1_resources),
d9e8b884 GL	509	.resource = mxc_spi_1_resources,
d37ba97d SH	510	};
d37ba97d SH	511
d9e8b884	512	struct platform_device mxc_spi_device2 = {
d37ba97d SH	513	.name = "spi_imx",
d37ba97d SH	514	.id = 2,
d9e8b884 GL	515	.num_resources = ARRAY_SIZE(mxc_spi_2_resources),
d9e8b884 GL	516	.resource = mxc_spi_2_resources,
d37ba97d SH	517	};
d37ba97d SH	518
9536ff33 SH	519	#ifdef CONFIG_ARCH_MX35
	520	static struct resource mxc_fec_resources[] = {
	521	{
	522	.start = MXC_FEC_BASE_ADDR,
	523	.end = MXC_FEC_BASE_ADDR + 0xfff,
3f4f54b4	524	.flags = IORESOURCE_MEM,
9536ff33 SH	525	}, {
	526	.start = MXC_INT_FEC,
	527	.end = MXC_INT_FEC,
3f4f54b4	528	.flags = IORESOURCE_IRQ,
9536ff33 SH	529	},
	530	};
	531
	532	struct platform_device mxc_fec_device = {
	533	.name = "fec",
	534	.id = 0,
	535	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	536	.resource = mxc_fec_resources,
	537	};
	538	#endif
	539
d8d982b1 SH	540	static struct resource imx_ssi_resources0[] = {
	541	{
	542	.start = SSI1_BASE_ADDR,
	543	.end = SSI1_BASE_ADDR + 0xfff,
	544	.flags = IORESOURCE_MEM,
	545	}, {
	546	.start = MX31_INT_SSI1,
	547	.end = MX31_INT_SSI1,
	548	.flags = IORESOURCE_IRQ,
	549	},
	550	};
	551
	552	static struct resource imx_ssi_resources1[] = {
	553	{
	554	.start = SSI2_BASE_ADDR,
	555	.end = SSI2_BASE_ADDR + 0xfff,
	556	.flags = IORESOURCE_MEM
	557	}, {
	558	.start = MX31_INT_SSI2,
	559	.end = MX31_INT_SSI2,
	560	.flags = IORESOURCE_IRQ,
	561	},
	562	};
	563
	564	struct platform_device imx_ssi_device0 = {
	565	.name = "imx-ssi",
	566	.id = 0,
	567	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
	568	.resource = imx_ssi_resources0,
	569	};
	570
	571	struct platform_device imx_ssi_device1 = {
	572	.name = "imx-ssi",
	573	.id = 1,
	574	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
	575	.resource = imx_ssi_resources1,
	576	};
	577
9536ff33 SH	578	static int mx3_devices_init(void)
	579	{
	580	if (cpu_is_mx31()) {
	581	mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
	582	mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
45001e92	583	mxc_register_device(&mxc_rnga_device, NULL);
9536ff33 SH	584	}
	585	if (cpu_is_mx35()) {
	586	mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
fcebfc8d	587	mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
7bc07ebc SH	588	otg_resources[0].start = MX35_OTG_BASE_ADDR;
	589	otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
	590	otg_resources[1].start = MXC_INT_USBOTG;
	591	otg_resources[1].end = MXC_INT_USBOTG;
	592	mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
	593	mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
	594	mxc_usbh1_resources[1].start = MXC_INT_USBHS;
	595	mxc_usbh1_resources[1].end = MXC_INT_USBHS;
d8d982b1 SH	596	imx_ssi_resources0[1].start = MX35_INT_SSI1;
	597	imx_ssi_resources0[1].end = MX35_INT_SSI1;
	598	imx_ssi_resources1[1].start = MX35_INT_SSI2;
	599	imx_ssi_resources1[1].end = MX35_INT_SSI2;
9536ff33 SH	600	}
	601
	602	return 0;
	603	}
	604
	605	subsys_initcall(mx3_devices_init);