[deliverable/linux.git] / arch / arm / mach-mx3 / devices.c

/*
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
 * Boston, MA  02110-1301, USA.
 */

#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/mx3_camera.h>

#include "devices.h"

static struct resource uart0[] = {
	{
		.start = UART1_BASE_ADDR,
		.end = UART1_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART1,
		.end = MXC_INT_UART1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device0 = {
	.name = "imx-uart",
	.id = 0,
	.resource = uart0,
	.num_resources = ARRAY_SIZE(uart0),
};

static struct resource uart1[] = {
	{
		.start = UART2_BASE_ADDR,
		.end = UART2_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART2,
		.end = MXC_INT_UART2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device1 = {
	.name = "imx-uart",
	.id = 1,
	.resource = uart1,
	.num_resources = ARRAY_SIZE(uart1),
};

static struct resource uart2[] = {
	{
		.start = UART3_BASE_ADDR,
		.end = UART3_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART3,
		.end = MXC_INT_UART3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device2 = {
	.name = "imx-uart",
	.id = 2,
	.resource = uart2,
	.num_resources = ARRAY_SIZE(uart2),
};

#ifdef CONFIG_ARCH_MX31
static struct resource uart3[] = {
	{
		.start = UART4_BASE_ADDR,
		.end = UART4_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART4,
		.end = MXC_INT_UART4,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device3 = {
	.name = "imx-uart",
	.id = 3,
	.resource = uart3,
	.num_resources = ARRAY_SIZE(uart3),
};

static struct resource uart4[] = {
	{
		.start = UART5_BASE_ADDR,
		.end = UART5_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART5,
		.end = MXC_INT_UART5,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device4 = {
	.name = "imx-uart",
	.id = 4,
	.resource = uart4,
	.num_resources = ARRAY_SIZE(uart4),
};
#endif /* CONFIG_ARCH_MX31 */

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	[0] = {
		.chip.label = "gpio-0",
		.base = IO_ADDRESS(GPIO1_BASE_ADDR),
		.irq = MXC_INT_GPIO1,
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	},
	[1] = {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO2_BASE_ADDR),
		.irq = MXC_INT_GPIO2,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	},
	[2] = {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO3_BASE_ADDR),
		.irq = MXC_INT_GPIO3,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= 0, /* runtime dependent */
		.end	= 0,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

static struct resource mxc_i2c0_resources[] = {
	{
		.start = I2C_BASE_ADDR,
		.end = I2C_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C,
		.end = MXC_INT_I2C,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	.resource = mxc_i2c0_resources,
};

static struct resource mxc_i2c1_resources[] = {
	{
		.start = I2C2_BASE_ADDR,
		.end = I2C2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C2,
		.end = MXC_INT_I2C2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	.resource = mxc_i2c1_resources,
};

static struct resource mxc_i2c2_resources[] = {
	{
		.start = I2C3_BASE_ADDR,
		.end = I2C3_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C3,
		.end = MXC_INT_I2C3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device2 = {
	.name = "imx-i2c",
	.id = 2,
	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	.resource = mxc_i2c2_resources,
};

#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
	{
		.start = MMC_SDHC1_BASE_ADDR,
		.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC1,
		.end = MXC_INT_MMC_SDHC1,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxcsdhc1_resources[] = {
	{
		.start = MMC_SDHC2_BASE_ADDR,
		.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC2,
		.end = MXC_INT_MMC_SDHC2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxcsdhc_device0 = {
	.name = "mxc-mmc",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	.resource = mxcsdhc0_resources,
};

struct platform_device mxcsdhc_device1 = {
	.name = "mxc-mmc",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	.resource = mxcsdhc1_resources,
};

static struct resource rnga_resources[] = {
	{
		.start = RNGA_BASE_ADDR,
		.end = RNGA_BASE_ADDR + 0x28,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_rnga_device = {
	.name = "mxc_rnga",
	.id = -1,
	.num_resources = 1,
	.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */

/* i.MX31 Image Processing Unit */

/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
	{
		.start = IPU_CTRL_BASE_ADDR,
		.end = IPU_CTRL_BASE_ADDR + 0x5F,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IPU_CTRL_BASE_ADDR + 0x88,
		.end = IPU_CTRL_BASE_ADDR + 0xB3,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_IPU_SYN,
		.end = MXC_INT_IPU_SYN,
		.flags = IORESOURCE_IRQ,
	}, {
		.start = MXC_INT_IPU_ERR,
		.end = MXC_INT_IPU_ERR,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mx3_ipu = {
	.name = "ipu-core",
	.id = -1,
	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	.resource = mx3_ipu_rsrc,
};

static struct resource fb_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0xB4,
		.end	= IPU_CTRL_BASE_ADDR + 0x1BF,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_fb = {
	.name		= "mx3_sdc_fb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(fb_resources),
	.resource	= fb_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
       },
};

static struct resource camera_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0x60,
		.end	= IPU_CTRL_BASE_ADDR + 0x87,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_camera = {
	.name		= "mx3-camera",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(camera_resources),
	.resource	= camera_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

static struct resource otg_resources[] = {
	{
		.start	= OTG_BASE_ADDR,
		.end	= OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

#ifdef CONFIG_ARCH_MX35
static struct resource mxc_fec_resources[] = {
	{
		.start	= MXC_FEC_BASE_ADDR,
		.end	= MXC_FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static int mx3_devices_init(void)
{
	if (cpu_is_mx31()) {
		mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
		mxc_register_device(&mxc_rnga_device, NULL);
	}
	if (cpu_is_mx35()) {
		mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
	}

	return 0;
}

subsys_initcall(mx3_devices_init);
Commit	Line	Data
e3d13ff4 SH	1	/*
	2	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor,
	17	* Boston, MA 02110-1301, USA.
	18	*/
	19
eb05bbeb	20	#include <linux/dma-mapping.h>
e3d13ff4 SH	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/serial.h>
07bd1a6c	24	#include <linux/gpio.h>
9c70e227	25	#include <linux/dma-mapping.h>
a09e64fb	26	#include <mach/hardware.h>
80b02c17	27	#include <mach/irqs.h>
45001e92	28	#include <mach/common.h>
a09e64fb	29	#include <mach/imx-uart.h>
9c70e227	30	#include <mach/mx3_camera.h>
e3d13ff4	31
87bbb197 SH	32	#include "devices.h"
87bbb197 SH	33
e3d13ff4 SH	34	static struct resource uart0[] = {
	35	{
	36	.start = UART1_BASE_ADDR,
	37	.end = UART1_BASE_ADDR + 0x0B5,
	38	.flags = IORESOURCE_MEM,
	39	}, {
	40	.start = MXC_INT_UART1,
	41	.end = MXC_INT_UART1,
	42	.flags = IORESOURCE_IRQ,
	43	},
	44	};
	45
5cf09421	46	struct platform_device mxc_uart_device0 = {
e3d13ff4 SH	47	.name = "imx-uart",
	48	.id = 0,
	49	.resource = uart0,
	50	.num_resources = ARRAY_SIZE(uart0),
	51	};
	52
	53	static struct resource uart1[] = {
	54	{
	55	.start = UART2_BASE_ADDR,
	56	.end = UART2_BASE_ADDR + 0x0B5,
	57	.flags = IORESOURCE_MEM,
	58	}, {
	59	.start = MXC_INT_UART2,
	60	.end = MXC_INT_UART2,
	61	.flags = IORESOURCE_IRQ,
	62	},
	63	};
	64
5cf09421	65	struct platform_device mxc_uart_device1 = {
e3d13ff4 SH	66	.name = "imx-uart",
	67	.id = 1,
	68	.resource = uart1,
	69	.num_resources = ARRAY_SIZE(uart1),
	70	};
	71
	72	static struct resource uart2[] = {
	73	{
	74	.start = UART3_BASE_ADDR,
	75	.end = UART3_BASE_ADDR + 0x0B5,
	76	.flags = IORESOURCE_MEM,
	77	}, {
	78	.start = MXC_INT_UART3,
	79	.end = MXC_INT_UART3,
	80	.flags = IORESOURCE_IRQ,
	81	},
	82	};
	83
5cf09421	84	struct platform_device mxc_uart_device2 = {
e3d13ff4 SH	85	.name = "imx-uart",
	86	.id = 2,
	87	.resource = uart2,
	88	.num_resources = ARRAY_SIZE(uart2),
	89	};
	90
9536ff33	91	#ifdef CONFIG_ARCH_MX31
e3d13ff4 SH	92	static struct resource uart3[] = {
	93	{
	94	.start = UART4_BASE_ADDR,
	95	.end = UART4_BASE_ADDR + 0x0B5,
	96	.flags = IORESOURCE_MEM,
	97	}, {
	98	.start = MXC_INT_UART4,
	99	.end = MXC_INT_UART4,
	100	.flags = IORESOURCE_IRQ,
	101	},
	102	};
	103
5cf09421	104	struct platform_device mxc_uart_device3 = {
e3d13ff4 SH	105	.name = "imx-uart",
	106	.id = 3,
	107	.resource = uart3,
	108	.num_resources = ARRAY_SIZE(uart3),
	109	};
	110
	111	static struct resource uart4[] = {
	112	{
	113	.start = UART5_BASE_ADDR,
	114	.end = UART5_BASE_ADDR + 0x0B5,
	115	.flags = IORESOURCE_MEM,
	116	}, {
	117	.start = MXC_INT_UART5,
	118	.end = MXC_INT_UART5,
	119	.flags = IORESOURCE_IRQ,
	120	},
	121	};
	122
5cf09421	123	struct platform_device mxc_uart_device4 = {
e3d13ff4 SH	124	.name = "imx-uart",
	125	.id = 4,
	126	.resource = uart4,
	127	.num_resources = ARRAY_SIZE(uart4),
	128	};
9536ff33	129	#endif /* CONFIG_ARCH_MX31 */
e3d13ff4	130
07bd1a6c JB	131	/* GPIO port description */
	132	static struct mxc_gpio_port imx_gpio_ports[] = {
	133	[0] = {
	134	.chip.label = "gpio-0",
	135	.base = IO_ADDRESS(GPIO1_BASE_ADDR),
	136	.irq = MXC_INT_GPIO1,
9d631b83	137	.virtual_irq_start = MXC_GPIO_IRQ_START,
07bd1a6c JB	138	},
	139	[1] = {
	140	.chip.label = "gpio-1",
	141	.base = IO_ADDRESS(GPIO2_BASE_ADDR),
	142	.irq = MXC_INT_GPIO2,
9d631b83	143	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
07bd1a6c JB	144	},
	145	[2] = {
	146	.chip.label = "gpio-2",
	147	.base = IO_ADDRESS(GPIO3_BASE_ADDR),
	148	.irq = MXC_INT_GPIO3,
9d631b83	149	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
07bd1a6c JB	150	}
	151	};
	152
	153	int __init mxc_register_gpios(void)
	154	{
	155	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	156	}
a8405929 SH	157
	158	static struct resource mxc_w1_master_resources[] = {
	159	{
	160	.start = OWIRE_BASE_ADDR,
	161	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	162	.flags = IORESOURCE_MEM,
	163	},
	164	};
	165
	166	struct platform_device mxc_w1_master_device = {
	167	.name = "mxc_w1",
	168	.id = 0,
	169	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	170	.resource = mxc_w1_master_resources,
	171	};
cb96cf1a SH	172
	173	static struct resource mxc_nand_resources[] = {
	174	{
9536ff33 SH	175	.start = 0, /* runtime dependent */
9536ff33 SH	176	.end = 0,
cb96cf1a SH	177	.flags = IORESOURCE_MEM
	178	}, {
	179	.start = MXC_INT_NANDFC,
	180	.end = MXC_INT_NANDFC,
	181	.flags = IORESOURCE_IRQ
	182	},
	183	};
	184
	185	struct platform_device mxc_nand_device = {
	186	.name = "mxc_nand",
	187	.id = 0,
	188	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	189	.resource = mxc_nand_resources,
	190	};
39d1dc06 MB	191
	192	static struct resource mxc_i2c0_resources[] = {
	193	{
	194	.start = I2C_BASE_ADDR,
	195	.end = I2C_BASE_ADDR + SZ_4K - 1,
	196	.flags = IORESOURCE_MEM,
	197	},
	198	{
	199	.start = MXC_INT_I2C,
	200	.end = MXC_INT_I2C,
	201	.flags = IORESOURCE_IRQ,
	202	},
	203	};
	204
	205	struct platform_device mxc_i2c_device0 = {
	206	.name = "imx-i2c",
	207	.id = 0,
	208	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	209	.resource = mxc_i2c0_resources,
	210	};
	211
	212	static struct resource mxc_i2c1_resources[] = {
	213	{
	214	.start = I2C2_BASE_ADDR,
	215	.end = I2C2_BASE_ADDR + SZ_4K - 1,
	216	.flags = IORESOURCE_MEM,
	217	},
	218	{
	219	.start = MXC_INT_I2C2,
	220	.end = MXC_INT_I2C2,
	221	.flags = IORESOURCE_IRQ,
	222	},
	223	};
	224
	225	struct platform_device mxc_i2c_device1 = {
	226	.name = "imx-i2c",
	227	.id = 1,
	228	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	229	.resource = mxc_i2c1_resources,
	230	};
	231
	232	static struct resource mxc_i2c2_resources[] = {
	233	{
	234	.start = I2C3_BASE_ADDR,
	235	.end = I2C3_BASE_ADDR + SZ_4K - 1,
	236	.flags = IORESOURCE_MEM,
	237	},
	238	{
	239	.start = MXC_INT_I2C3,
	240	.end = MXC_INT_I2C3,
	241	.flags = IORESOURCE_IRQ,
	242	},
	243	};
	244
	245	struct platform_device mxc_i2c_device2 = {
	246	.name = "imx-i2c",
	247	.id = 2,
	248	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	249	.resource = mxc_i2c2_resources,
	250	};
ca489f8e	251
2adc1d65 SH	252	#ifdef CONFIG_ARCH_MX31
	253	static struct resource mxcsdhc0_resources[] = {
	254	{
	255	.start = MMC_SDHC1_BASE_ADDR,
	256	.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
	257	.flags = IORESOURCE_MEM,
	258	}, {
	259	.start = MXC_INT_MMC_SDHC1,
	260	.end = MXC_INT_MMC_SDHC1,
	261	.flags = IORESOURCE_IRQ,
	262	},
	263	};
	264
	265	static struct resource mxcsdhc1_resources[] = {
	266	{
	267	.start = MMC_SDHC2_BASE_ADDR,
	268	.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
	269	.flags = IORESOURCE_MEM,
	270	}, {
	271	.start = MXC_INT_MMC_SDHC2,
	272	.end = MXC_INT_MMC_SDHC2,
	273	.flags = IORESOURCE_IRQ,
	274	},
	275	};
	276
	277	struct platform_device mxcsdhc_device0 = {
	278	.name = "mxc-mmc",
	279	.id = 0,
	280	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	281	.resource = mxcsdhc0_resources,
	282	};
	283
	284	struct platform_device mxcsdhc_device1 = {
	285	.name = "mxc-mmc",
	286	.id = 1,
	287	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	288	.resource = mxcsdhc1_resources,
	289	};
45001e92 ACA	290
	291	static struct resource rnga_resources[] = {
	292	{
	293	.start = RNGA_BASE_ADDR,
	294	.end = RNGA_BASE_ADDR + 0x28,
	295	.flags = IORESOURCE_MEM,
	296	},
	297	};
	298
	299	struct platform_device mxc_rnga_device = {
	300	.name = "mxc_rnga",
	301	.id = -1,
	302	.num_resources = 1,
	303	.resource = rnga_resources,
	304	};
2adc1d65 SH	305	#endif /* CONFIG_ARCH_MX31 */
2adc1d65 SH	306
ca489f8e VL	307	/* i.MX31 Image Processing Unit */
	308
	309	/* The resource order is important! */
	310	static struct resource mx3_ipu_rsrc[] = {
	311	{
	312	.start = IPU_CTRL_BASE_ADDR,
	313	.end = IPU_CTRL_BASE_ADDR + 0x5F,
	314	.flags = IORESOURCE_MEM,
	315	}, {
	316	.start = IPU_CTRL_BASE_ADDR + 0x88,
	317	.end = IPU_CTRL_BASE_ADDR + 0xB3,
	318	.flags = IORESOURCE_MEM,
	319	}, {
	320	.start = MXC_INT_IPU_SYN,
	321	.end = MXC_INT_IPU_SYN,
	322	.flags = IORESOURCE_IRQ,
	323	}, {
	324	.start = MXC_INT_IPU_ERR,
	325	.end = MXC_INT_IPU_ERR,
	326	.flags = IORESOURCE_IRQ,
	327	},
	328	};
	329
	330	struct platform_device mx3_ipu = {
	331	.name = "ipu-core",
	332	.id = -1,
	333	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	334	.resource = mx3_ipu_rsrc,
	335	};
	336
	337	static struct resource fb_resources[] = {
	338	{
	339	.start = IPU_CTRL_BASE_ADDR + 0xB4,
	340	.end = IPU_CTRL_BASE_ADDR + 0x1BF,
	341	.flags = IORESOURCE_MEM,
	342	},
	343	};
	344
	345	struct platform_device mx3_fb = {
	346	.name = "mx3_sdc_fb",
	347	.id = -1,
	348	.num_resources = ARRAY_SIZE(fb_resources),
	349	.resource = fb_resources,
	350	.dev = {
9c70e227	351	.coherent_dma_mask = DMA_BIT_MASK(32),
ca489f8e VL	352	},
ca489f8e VL	353	};
9536ff33	354
9c70e227 VL	355	static struct resource camera_resources[] = {
	356	{
	357	.start = IPU_CTRL_BASE_ADDR + 0x60,
	358	.end = IPU_CTRL_BASE_ADDR + 0x87,
	359	.flags = IORESOURCE_MEM,
	360	},
	361	};
	362
	363	struct platform_device mx3_camera = {
	364	.name = "mx3-camera",
	365	.id = 0,
	366	.num_resources = ARRAY_SIZE(camera_resources),
	367	.resource = camera_resources,
	368	.dev = {
	369	.coherent_dma_mask = DMA_BIT_MASK(32),
	370	},
	371	};
	372
eb05bbeb GL	373	static struct resource otg_resources[] = {
	374	{
	375	.start = OTG_BASE_ADDR,
	376	.end = OTG_BASE_ADDR + 0x1ff,
	377	.flags = IORESOURCE_MEM,
	378	}, {
	379	.start = MXC_INT_USB3,
	380	.end = MXC_INT_USB3,
	381	.flags = IORESOURCE_IRQ,
	382	},
	383	};
	384
	385	static u64 otg_dmamask = DMA_BIT_MASK(32);
	386
	387	/* OTG gadget device */
	388	struct platform_device mxc_otg_udc_device = {
	389	.name = "fsl-usb2-udc",
	390	.id = -1,
	391	.dev = {
	392	.dma_mask = &otg_dmamask,
	393	.coherent_dma_mask = DMA_BIT_MASK(32),
	394	},
	395	.resource = otg_resources,
	396	.num_resources = ARRAY_SIZE(otg_resources),
	397	};
	398
9536ff33 SH	399	#ifdef CONFIG_ARCH_MX35
	400	static struct resource mxc_fec_resources[] = {
	401	{
	402	.start = MXC_FEC_BASE_ADDR,
	403	.end = MXC_FEC_BASE_ADDR + 0xfff,
	404	.flags = IORESOURCE_MEM
	405	}, {
	406	.start = MXC_INT_FEC,
	407	.end = MXC_INT_FEC,
	408	.flags = IORESOURCE_IRQ
	409	},
	410	};
	411
	412	struct platform_device mxc_fec_device = {
	413	.name = "fec",
	414	.id = 0,
	415	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	416	.resource = mxc_fec_resources,
	417	};
	418	#endif
	419
	420	static int mx3_devices_init(void)
	421	{
	422	if (cpu_is_mx31()) {
	423	mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
	424	mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
45001e92	425	mxc_register_device(&mxc_rnga_device, NULL);
9536ff33 SH	426	}
	427	if (cpu_is_mx35()) {
	428	mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
	429	mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
	430	}
	431
	432	return 0;
	433	}
	434
	435	subsys_initcall(mx3_devices_init);