[deliverable/linux.git] / arch / arm / mach-mx3 / devices.c

/*
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
 * Boston, MA  02110-1301, USA.
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/imx-uart.h>

#include "devices.h"

static struct resource uart0[] = {
	{
		.start = UART1_BASE_ADDR,
		.end = UART1_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART1,
		.end = MXC_INT_UART1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device0 = {
	.name = "imx-uart",
	.id = 0,
	.resource = uart0,
	.num_resources = ARRAY_SIZE(uart0),
};

static struct resource uart1[] = {
	{
		.start = UART2_BASE_ADDR,
		.end = UART2_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART2,
		.end = MXC_INT_UART2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device1 = {
	.name = "imx-uart",
	.id = 1,
	.resource = uart1,
	.num_resources = ARRAY_SIZE(uart1),
};

static struct resource uart2[] = {
	{
		.start = UART3_BASE_ADDR,
		.end = UART3_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART3,
		.end = MXC_INT_UART3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device2 = {
	.name = "imx-uart",
	.id = 2,
	.resource = uart2,
	.num_resources = ARRAY_SIZE(uart2),
};

#ifdef CONFIG_ARCH_MX31
static struct resource uart3[] = {
	{
		.start = UART4_BASE_ADDR,
		.end = UART4_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART4,
		.end = MXC_INT_UART4,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device3 = {
	.name = "imx-uart",
	.id = 3,
	.resource = uart3,
	.num_resources = ARRAY_SIZE(uart3),
};

static struct resource uart4[] = {
	{
		.start = UART5_BASE_ADDR,
		.end = UART5_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART5,
		.end = MXC_INT_UART5,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device4 = {
	.name = "imx-uart",
	.id = 4,
	.resource = uart4,
	.num_resources = ARRAY_SIZE(uart4),
};
#endif /* CONFIG_ARCH_MX31 */

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	[0] = {
		.chip.label = "gpio-0",
		.base = IO_ADDRESS(GPIO1_BASE_ADDR),
		.irq = MXC_INT_GPIO1,
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	},
	[1] = {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO2_BASE_ADDR),
		.irq = MXC_INT_GPIO2,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	},
	[2] = {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO3_BASE_ADDR),
		.irq = MXC_INT_GPIO3,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= 0, /* runtime dependent */
		.end	= 0,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

static struct resource mxc_i2c0_resources[] = {
	{
		.start = I2C_BASE_ADDR,
		.end = I2C_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C,
		.end = MXC_INT_I2C,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	.resource = mxc_i2c0_resources,
};

static struct resource mxc_i2c1_resources[] = {
	{
		.start = I2C2_BASE_ADDR,
		.end = I2C2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C2,
		.end = MXC_INT_I2C2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	.resource = mxc_i2c1_resources,
};

static struct resource mxc_i2c2_resources[] = {
	{
		.start = I2C3_BASE_ADDR,
		.end = I2C3_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C3,
		.end = MXC_INT_I2C3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device2 = {
	.name = "imx-i2c",
	.id = 2,
	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	.resource = mxc_i2c2_resources,
};

#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
	{
		.start = MMC_SDHC1_BASE_ADDR,
		.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC1,
		.end = MXC_INT_MMC_SDHC1,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxcsdhc1_resources[] = {
	{
		.start = MMC_SDHC2_BASE_ADDR,
		.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC2,
		.end = MXC_INT_MMC_SDHC2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxcsdhc_device0 = {
	.name = "mxc-mmc",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	.resource = mxcsdhc0_resources,
};

struct platform_device mxcsdhc_device1 = {
	.name = "mxc-mmc",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	.resource = mxcsdhc1_resources,
};
#endif /* CONFIG_ARCH_MX31 */

/* i.MX31 Image Processing Unit */

/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
	{
		.start = IPU_CTRL_BASE_ADDR,
		.end = IPU_CTRL_BASE_ADDR + 0x5F,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IPU_CTRL_BASE_ADDR + 0x88,
		.end = IPU_CTRL_BASE_ADDR + 0xB3,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_IPU_SYN,
		.end = MXC_INT_IPU_SYN,
		.flags = IORESOURCE_IRQ,
	}, {
		.start = MXC_INT_IPU_ERR,
		.end = MXC_INT_IPU_ERR,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mx3_ipu = {
	.name = "ipu-core",
	.id = -1,
	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	.resource = mx3_ipu_rsrc,
};

static struct resource fb_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0xB4,
		.end	= IPU_CTRL_BASE_ADDR + 0x1BF,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_fb = {
	.name		= "mx3_sdc_fb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(fb_resources),
	.resource	= fb_resources,
	.dev		= {
		.coherent_dma_mask = 0xffffffff,
       },
};

#ifdef CONFIG_ARCH_MX35
static struct resource mxc_fec_resources[] = {
	{
		.start	= MXC_FEC_BASE_ADDR,
		.end	= MXC_FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static int mx3_devices_init(void)
{
	if (cpu_is_mx31()) {
		mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
	}
	if (cpu_is_mx35()) {
		mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
	}

	return 0;
}

subsys_initcall(mx3_devices_init);
Commit	Line	Data
e3d13ff4 SH	1	/*
	2	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor,
	17	* Boston, MA 02110-1301, USA.
	18	*/
	19
	20	#include <linux/module.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/serial.h>
07bd1a6c	23	#include <linux/gpio.h>
a09e64fb	24	#include <mach/hardware.h>
80b02c17	25	#include <mach/irqs.h>
a09e64fb	26	#include <mach/imx-uart.h>
e3d13ff4	27
87bbb197 SH	28	#include "devices.h"
87bbb197 SH	29
e3d13ff4 SH	30	static struct resource uart0[] = {
	31	{
	32	.start = UART1_BASE_ADDR,
	33	.end = UART1_BASE_ADDR + 0x0B5,
	34	.flags = IORESOURCE_MEM,
	35	}, {
	36	.start = MXC_INT_UART1,
	37	.end = MXC_INT_UART1,
	38	.flags = IORESOURCE_IRQ,
	39	},
	40	};
	41
5cf09421	42	struct platform_device mxc_uart_device0 = {
e3d13ff4 SH	43	.name = "imx-uart",
	44	.id = 0,
	45	.resource = uart0,
	46	.num_resources = ARRAY_SIZE(uart0),
	47	};
	48
	49	static struct resource uart1[] = {
	50	{
	51	.start = UART2_BASE_ADDR,
	52	.end = UART2_BASE_ADDR + 0x0B5,
	53	.flags = IORESOURCE_MEM,
	54	}, {
	55	.start = MXC_INT_UART2,
	56	.end = MXC_INT_UART2,
	57	.flags = IORESOURCE_IRQ,
	58	},
	59	};
	60
5cf09421	61	struct platform_device mxc_uart_device1 = {
e3d13ff4 SH	62	.name = "imx-uart",
	63	.id = 1,
	64	.resource = uart1,
	65	.num_resources = ARRAY_SIZE(uart1),
	66	};
	67
	68	static struct resource uart2[] = {
	69	{
	70	.start = UART3_BASE_ADDR,
	71	.end = UART3_BASE_ADDR + 0x0B5,
	72	.flags = IORESOURCE_MEM,
	73	}, {
	74	.start = MXC_INT_UART3,
	75	.end = MXC_INT_UART3,
	76	.flags = IORESOURCE_IRQ,
	77	},
	78	};
	79
5cf09421	80	struct platform_device mxc_uart_device2 = {
e3d13ff4 SH	81	.name = "imx-uart",
	82	.id = 2,
	83	.resource = uart2,
	84	.num_resources = ARRAY_SIZE(uart2),
	85	};
	86
9536ff33	87	#ifdef CONFIG_ARCH_MX31
e3d13ff4 SH	88	static struct resource uart3[] = {
	89	{
	90	.start = UART4_BASE_ADDR,
	91	.end = UART4_BASE_ADDR + 0x0B5,
	92	.flags = IORESOURCE_MEM,
	93	}, {
	94	.start = MXC_INT_UART4,
	95	.end = MXC_INT_UART4,
	96	.flags = IORESOURCE_IRQ,
	97	},
	98	};
	99
5cf09421	100	struct platform_device mxc_uart_device3 = {
e3d13ff4 SH	101	.name = "imx-uart",
	102	.id = 3,
	103	.resource = uart3,
	104	.num_resources = ARRAY_SIZE(uart3),
	105	};
	106
	107	static struct resource uart4[] = {
	108	{
	109	.start = UART5_BASE_ADDR,
	110	.end = UART5_BASE_ADDR + 0x0B5,
	111	.flags = IORESOURCE_MEM,
	112	}, {
	113	.start = MXC_INT_UART5,
	114	.end = MXC_INT_UART5,
	115	.flags = IORESOURCE_IRQ,
	116	},
	117	};
	118
5cf09421	119	struct platform_device mxc_uart_device4 = {
e3d13ff4 SH	120	.name = "imx-uart",
	121	.id = 4,
	122	.resource = uart4,
	123	.num_resources = ARRAY_SIZE(uart4),
	124	};
9536ff33	125	#endif /* CONFIG_ARCH_MX31 */
e3d13ff4	126
07bd1a6c JB	127	/* GPIO port description */
	128	static struct mxc_gpio_port imx_gpio_ports[] = {
	129	[0] = {
	130	.chip.label = "gpio-0",
	131	.base = IO_ADDRESS(GPIO1_BASE_ADDR),
	132	.irq = MXC_INT_GPIO1,
9d631b83	133	.virtual_irq_start = MXC_GPIO_IRQ_START,
07bd1a6c JB	134	},
	135	[1] = {
	136	.chip.label = "gpio-1",
	137	.base = IO_ADDRESS(GPIO2_BASE_ADDR),
	138	.irq = MXC_INT_GPIO2,
9d631b83	139	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
07bd1a6c JB	140	},
	141	[2] = {
	142	.chip.label = "gpio-2",
	143	.base = IO_ADDRESS(GPIO3_BASE_ADDR),
	144	.irq = MXC_INT_GPIO3,
9d631b83	145	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
07bd1a6c JB	146	}
	147	};
	148
	149	int __init mxc_register_gpios(void)
	150	{
	151	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	152	}
a8405929 SH	153
	154	static struct resource mxc_w1_master_resources[] = {
	155	{
	156	.start = OWIRE_BASE_ADDR,
	157	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	158	.flags = IORESOURCE_MEM,
	159	},
	160	};
	161
	162	struct platform_device mxc_w1_master_device = {
	163	.name = "mxc_w1",
	164	.id = 0,
	165	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	166	.resource = mxc_w1_master_resources,
	167	};
cb96cf1a SH	168
	169	static struct resource mxc_nand_resources[] = {
	170	{
9536ff33 SH	171	.start = 0, /* runtime dependent */
9536ff33 SH	172	.end = 0,
cb96cf1a SH	173	.flags = IORESOURCE_MEM
	174	}, {
	175	.start = MXC_INT_NANDFC,
	176	.end = MXC_INT_NANDFC,
	177	.flags = IORESOURCE_IRQ
	178	},
	179	};
	180
	181	struct platform_device mxc_nand_device = {
	182	.name = "mxc_nand",
	183	.id = 0,
	184	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	185	.resource = mxc_nand_resources,
	186	};
39d1dc06 MB	187
	188	static struct resource mxc_i2c0_resources[] = {
	189	{
	190	.start = I2C_BASE_ADDR,
	191	.end = I2C_BASE_ADDR + SZ_4K - 1,
	192	.flags = IORESOURCE_MEM,
	193	},
	194	{
	195	.start = MXC_INT_I2C,
	196	.end = MXC_INT_I2C,
	197	.flags = IORESOURCE_IRQ,
	198	},
	199	};
	200
	201	struct platform_device mxc_i2c_device0 = {
	202	.name = "imx-i2c",
	203	.id = 0,
	204	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	205	.resource = mxc_i2c0_resources,
	206	};
	207
	208	static struct resource mxc_i2c1_resources[] = {
	209	{
	210	.start = I2C2_BASE_ADDR,
	211	.end = I2C2_BASE_ADDR + SZ_4K - 1,
	212	.flags = IORESOURCE_MEM,
	213	},
	214	{
	215	.start = MXC_INT_I2C2,
	216	.end = MXC_INT_I2C2,
	217	.flags = IORESOURCE_IRQ,
	218	},
	219	};
	220
	221	struct platform_device mxc_i2c_device1 = {
	222	.name = "imx-i2c",
	223	.id = 1,
	224	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	225	.resource = mxc_i2c1_resources,
	226	};
	227
	228	static struct resource mxc_i2c2_resources[] = {
	229	{
	230	.start = I2C3_BASE_ADDR,
	231	.end = I2C3_BASE_ADDR + SZ_4K - 1,
	232	.flags = IORESOURCE_MEM,
	233	},
	234	{
	235	.start = MXC_INT_I2C3,
	236	.end = MXC_INT_I2C3,
	237	.flags = IORESOURCE_IRQ,
	238	},
	239	};
	240
	241	struct platform_device mxc_i2c_device2 = {
	242	.name = "imx-i2c",
	243	.id = 2,
	244	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	245	.resource = mxc_i2c2_resources,
	246	};
ca489f8e	247
2adc1d65 SH	248	#ifdef CONFIG_ARCH_MX31
	249	static struct resource mxcsdhc0_resources[] = {
	250	{
	251	.start = MMC_SDHC1_BASE_ADDR,
	252	.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
	253	.flags = IORESOURCE_MEM,
	254	}, {
	255	.start = MXC_INT_MMC_SDHC1,
	256	.end = MXC_INT_MMC_SDHC1,
	257	.flags = IORESOURCE_IRQ,
	258	},
	259	};
	260
	261	static struct resource mxcsdhc1_resources[] = {
	262	{
	263	.start = MMC_SDHC2_BASE_ADDR,
	264	.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
	265	.flags = IORESOURCE_MEM,
	266	}, {
	267	.start = MXC_INT_MMC_SDHC2,
	268	.end = MXC_INT_MMC_SDHC2,
	269	.flags = IORESOURCE_IRQ,
	270	},
	271	};
	272
	273	struct platform_device mxcsdhc_device0 = {
	274	.name = "mxc-mmc",
	275	.id = 0,
	276	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	277	.resource = mxcsdhc0_resources,
	278	};
	279
	280	struct platform_device mxcsdhc_device1 = {
	281	.name = "mxc-mmc",
	282	.id = 1,
	283	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	284	.resource = mxcsdhc1_resources,
	285	};
	286	#endif /* CONFIG_ARCH_MX31 */
	287
ca489f8e VL	288	/* i.MX31 Image Processing Unit */
	289
	290	/* The resource order is important! */
	291	static struct resource mx3_ipu_rsrc[] = {
	292	{
	293	.start = IPU_CTRL_BASE_ADDR,
	294	.end = IPU_CTRL_BASE_ADDR + 0x5F,
	295	.flags = IORESOURCE_MEM,
	296	}, {
	297	.start = IPU_CTRL_BASE_ADDR + 0x88,
	298	.end = IPU_CTRL_BASE_ADDR + 0xB3,
	299	.flags = IORESOURCE_MEM,
	300	}, {
	301	.start = MXC_INT_IPU_SYN,
	302	.end = MXC_INT_IPU_SYN,
	303	.flags = IORESOURCE_IRQ,
	304	}, {
	305	.start = MXC_INT_IPU_ERR,
	306	.end = MXC_INT_IPU_ERR,
	307	.flags = IORESOURCE_IRQ,
	308	},
	309	};
	310
	311	struct platform_device mx3_ipu = {
	312	.name = "ipu-core",
	313	.id = -1,
	314	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	315	.resource = mx3_ipu_rsrc,
	316	};
	317
	318	static struct resource fb_resources[] = {
	319	{
	320	.start = IPU_CTRL_BASE_ADDR + 0xB4,
	321	.end = IPU_CTRL_BASE_ADDR + 0x1BF,
	322	.flags = IORESOURCE_MEM,
	323	},
	324	};
	325
	326	struct platform_device mx3_fb = {
	327	.name = "mx3_sdc_fb",
	328	.id = -1,
	329	.num_resources = ARRAY_SIZE(fb_resources),
	330	.resource = fb_resources,
	331	.dev = {
	332	.coherent_dma_mask = 0xffffffff,
	333	},
	334	};
9536ff33 SH	335
	336	#ifdef CONFIG_ARCH_MX35
	337	static struct resource mxc_fec_resources[] = {
	338	{
	339	.start = MXC_FEC_BASE_ADDR,
	340	.end = MXC_FEC_BASE_ADDR + 0xfff,
	341	.flags = IORESOURCE_MEM
	342	}, {
	343	.start = MXC_INT_FEC,
	344	.end = MXC_INT_FEC,
	345	.flags = IORESOURCE_IRQ
	346	},
	347	};
	348
	349	struct platform_device mxc_fec_device = {
	350	.name = "fec",
	351	.id = 0,
	352	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	353	.resource = mxc_fec_resources,
	354	};
	355	#endif
	356
	357	static int mx3_devices_init(void)
	358	{
	359	if (cpu_is_mx31()) {
	360	mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
	361	mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
	362	}
	363	if (cpu_is_mx35()) {
	364	mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
	365	mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
	366	}
	367
	368	return 0;
	369	}
	370
	371	subsys_initcall(mx3_devices_init);