[deliverable/linux.git] / arch / arm / mach-mx3 / devices.c

/*
 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
 * Boston, MA  02110-1301, USA.
 */

#include <linux/dma-mapping.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/mx3_camera.h>

#include "devices.h"

static struct resource uart0[] = {
	{
		.start = UART1_BASE_ADDR,
		.end = UART1_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART1,
		.end = MXC_INT_UART1,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device0 = {
	.name = "imx-uart",
	.id = 0,
	.resource = uart0,
	.num_resources = ARRAY_SIZE(uart0),
};

static struct resource uart1[] = {
	{
		.start = UART2_BASE_ADDR,
		.end = UART2_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART2,
		.end = MXC_INT_UART2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device1 = {
	.name = "imx-uart",
	.id = 1,
	.resource = uart1,
	.num_resources = ARRAY_SIZE(uart1),
};

static struct resource uart2[] = {
	{
		.start = UART3_BASE_ADDR,
		.end = UART3_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART3,
		.end = MXC_INT_UART3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device2 = {
	.name = "imx-uart",
	.id = 2,
	.resource = uart2,
	.num_resources = ARRAY_SIZE(uart2),
};

#ifdef CONFIG_ARCH_MX31
static struct resource uart3[] = {
	{
		.start = UART4_BASE_ADDR,
		.end = UART4_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART4,
		.end = MXC_INT_UART4,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device3 = {
	.name = "imx-uart",
	.id = 3,
	.resource = uart3,
	.num_resources = ARRAY_SIZE(uart3),
};

static struct resource uart4[] = {
	{
		.start = UART5_BASE_ADDR,
		.end = UART5_BASE_ADDR + 0x0B5,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_UART5,
		.end = MXC_INT_UART5,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_uart_device4 = {
	.name = "imx-uart",
	.id = 4,
	.resource = uart4,
	.num_resources = ARRAY_SIZE(uart4),
};
#endif /* CONFIG_ARCH_MX31 */

/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
	[0] = {
		.chip.label = "gpio-0",
		.base = IO_ADDRESS(GPIO1_BASE_ADDR),
		.irq = MXC_INT_GPIO1,
		.virtual_irq_start = MXC_GPIO_IRQ_START,
	},
	[1] = {
		.chip.label = "gpio-1",
		.base = IO_ADDRESS(GPIO2_BASE_ADDR),
		.irq = MXC_INT_GPIO2,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
	},
	[2] = {
		.chip.label = "gpio-2",
		.base = IO_ADDRESS(GPIO3_BASE_ADDR),
		.irq = MXC_INT_GPIO3,
		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
	}
};

int __init mxc_register_gpios(void)
{
	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}

static struct resource mxc_w1_master_resources[] = {
	{
		.start = OWIRE_BASE_ADDR,
		.end   = OWIRE_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_w1_master_device = {
	.name = "mxc_w1",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	.resource = mxc_w1_master_resources,
};

static struct resource mxc_nand_resources[] = {
	{
		.start	= 0, /* runtime dependent */
		.end	= 0,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_NANDFC,
		.end	= MXC_INT_NANDFC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_nand_device = {
	.name = "mxc_nand",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	.resource = mxc_nand_resources,
};

static struct resource mxc_i2c0_resources[] = {
	{
		.start = I2C_BASE_ADDR,
		.end = I2C_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C,
		.end = MXC_INT_I2C,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device0 = {
	.name = "imx-i2c",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	.resource = mxc_i2c0_resources,
};

static struct resource mxc_i2c1_resources[] = {
	{
		.start = I2C2_BASE_ADDR,
		.end = I2C2_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C2,
		.end = MXC_INT_I2C2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device1 = {
	.name = "imx-i2c",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	.resource = mxc_i2c1_resources,
};

static struct resource mxc_i2c2_resources[] = {
	{
		.start = I2C3_BASE_ADDR,
		.end = I2C3_BASE_ADDR + SZ_4K - 1,
		.flags = IORESOURCE_MEM,
	},
	{
		.start = MXC_INT_I2C3,
		.end = MXC_INT_I2C3,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxc_i2c_device2 = {
	.name = "imx-i2c",
	.id = 2,
	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	.resource = mxc_i2c2_resources,
};

#ifdef CONFIG_ARCH_MX31
static struct resource mxcsdhc0_resources[] = {
	{
		.start = MMC_SDHC1_BASE_ADDR,
		.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC1,
		.end = MXC_INT_MMC_SDHC1,
		.flags = IORESOURCE_IRQ,
	},
};

static struct resource mxcsdhc1_resources[] = {
	{
		.start = MMC_SDHC2_BASE_ADDR,
		.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_MMC_SDHC2,
		.end = MXC_INT_MMC_SDHC2,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mxcsdhc_device0 = {
	.name = "mxc-mmc",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	.resource = mxcsdhc0_resources,
};

struct platform_device mxcsdhc_device1 = {
	.name = "mxc-mmc",
	.id = 1,
	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	.resource = mxcsdhc1_resources,
};

static struct resource rnga_resources[] = {
	{
		.start = RNGA_BASE_ADDR,
		.end = RNGA_BASE_ADDR + 0x28,
		.flags = IORESOURCE_MEM,
	},
};

struct platform_device mxc_rnga_device = {
	.name = "mxc_rnga",
	.id = -1,
	.num_resources = 1,
	.resource = rnga_resources,
};
#endif /* CONFIG_ARCH_MX31 */

/* i.MX31 Image Processing Unit */

/* The resource order is important! */
static struct resource mx3_ipu_rsrc[] = {
	{
		.start = IPU_CTRL_BASE_ADDR,
		.end = IPU_CTRL_BASE_ADDR + 0x5F,
		.flags = IORESOURCE_MEM,
	}, {
		.start = IPU_CTRL_BASE_ADDR + 0x88,
		.end = IPU_CTRL_BASE_ADDR + 0xB3,
		.flags = IORESOURCE_MEM,
	}, {
		.start = MXC_INT_IPU_SYN,
		.end = MXC_INT_IPU_SYN,
		.flags = IORESOURCE_IRQ,
	}, {
		.start = MXC_INT_IPU_ERR,
		.end = MXC_INT_IPU_ERR,
		.flags = IORESOURCE_IRQ,
	},
};

struct platform_device mx3_ipu = {
	.name = "ipu-core",
	.id = -1,
	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	.resource = mx3_ipu_rsrc,
};

static struct resource fb_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0xB4,
		.end	= IPU_CTRL_BASE_ADDR + 0x1BF,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_fb = {
	.name		= "mx3_sdc_fb",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(fb_resources),
	.resource	= fb_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
       },
};

static struct resource camera_resources[] = {
	{
		.start	= IPU_CTRL_BASE_ADDR + 0x60,
		.end	= IPU_CTRL_BASE_ADDR + 0x87,
		.flags	= IORESOURCE_MEM,
	},
};

struct platform_device mx3_camera = {
	.name		= "mx3-camera",
	.id		= 0,
	.num_resources	= ARRAY_SIZE(camera_resources),
	.resource	= camera_resources,
	.dev		= {
		.coherent_dma_mask = DMA_BIT_MASK(32),
	},
};

static struct resource otg_resources[] = {
	{
		.start	= OTG_BASE_ADDR,
		.end	= OTG_BASE_ADDR + 0x1ff,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= MXC_INT_USB3,
		.end	= MXC_INT_USB3,
		.flags	= IORESOURCE_IRQ,
	},
};

static u64 otg_dmamask = DMA_BIT_MASK(32);

/* OTG gadget device */
struct platform_device mxc_otg_udc_device = {
	.name		= "fsl-usb2-udc",
	.id		= -1,
	.dev		= {
		.dma_mask		= &otg_dmamask,
		.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= otg_resources,
	.num_resources	= ARRAY_SIZE(otg_resources),
};

#ifdef CONFIG_ARCH_MX35
static struct resource mxc_fec_resources[] = {
	{
		.start	= MXC_FEC_BASE_ADDR,
		.end	= MXC_FEC_BASE_ADDR + 0xfff,
		.flags	= IORESOURCE_MEM
	}, {
		.start	= MXC_INT_FEC,
		.end	= MXC_INT_FEC,
		.flags	= IORESOURCE_IRQ
	},
};

struct platform_device mxc_fec_device = {
	.name = "fec",
	.id = 0,
	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	.resource = mxc_fec_resources,
};
#endif

static int mx3_devices_init(void)
{
	if (cpu_is_mx31()) {
		mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
		mxc_register_device(&mxc_rnga_device, NULL);
	}
	if (cpu_is_mx35()) {
		mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
		mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
	}

	return 0;
}

subsys_initcall(mx3_devices_init);
Commit	Line	Data
e3d13ff4 SH	1	/*
	2	* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor,
	17	* Boston, MA 02110-1301, USA.
	18	*/
	19
eb05bbeb	20	#include <linux/dma-mapping.h>
e3d13ff4 SH	21	#include <linux/module.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/serial.h>
07bd1a6c	24	#include <linux/gpio.h>
a09e64fb	25	#include <mach/hardware.h>
80b02c17	26	#include <mach/irqs.h>
45001e92	27	#include <mach/common.h>
a09e64fb	28	#include <mach/imx-uart.h>
9c70e227	29	#include <mach/mx3_camera.h>
e3d13ff4	30
87bbb197 SH	31	#include "devices.h"
87bbb197 SH	32
e3d13ff4 SH	33	static struct resource uart0[] = {
	34	{
	35	.start = UART1_BASE_ADDR,
	36	.end = UART1_BASE_ADDR + 0x0B5,
	37	.flags = IORESOURCE_MEM,
	38	}, {
	39	.start = MXC_INT_UART1,
	40	.end = MXC_INT_UART1,
	41	.flags = IORESOURCE_IRQ,
	42	},
	43	};
	44
5cf09421	45	struct platform_device mxc_uart_device0 = {
e3d13ff4 SH	46	.name = "imx-uart",
	47	.id = 0,
	48	.resource = uart0,
	49	.num_resources = ARRAY_SIZE(uart0),
	50	};
	51
	52	static struct resource uart1[] = {
	53	{
	54	.start = UART2_BASE_ADDR,
	55	.end = UART2_BASE_ADDR + 0x0B5,
	56	.flags = IORESOURCE_MEM,
	57	}, {
	58	.start = MXC_INT_UART2,
	59	.end = MXC_INT_UART2,
	60	.flags = IORESOURCE_IRQ,
	61	},
	62	};
	63
5cf09421	64	struct platform_device mxc_uart_device1 = {
e3d13ff4 SH	65	.name = "imx-uart",
	66	.id = 1,
	67	.resource = uart1,
	68	.num_resources = ARRAY_SIZE(uart1),
	69	};
	70
	71	static struct resource uart2[] = {
	72	{
	73	.start = UART3_BASE_ADDR,
	74	.end = UART3_BASE_ADDR + 0x0B5,
	75	.flags = IORESOURCE_MEM,
	76	}, {
	77	.start = MXC_INT_UART3,
	78	.end = MXC_INT_UART3,
	79	.flags = IORESOURCE_IRQ,
	80	},
	81	};
	82
5cf09421	83	struct platform_device mxc_uart_device2 = {
e3d13ff4 SH	84	.name = "imx-uart",
	85	.id = 2,
	86	.resource = uart2,
	87	.num_resources = ARRAY_SIZE(uart2),
	88	};
	89
9536ff33	90	#ifdef CONFIG_ARCH_MX31
e3d13ff4 SH	91	static struct resource uart3[] = {
	92	{
	93	.start = UART4_BASE_ADDR,
	94	.end = UART4_BASE_ADDR + 0x0B5,
	95	.flags = IORESOURCE_MEM,
	96	}, {
	97	.start = MXC_INT_UART4,
	98	.end = MXC_INT_UART4,
	99	.flags = IORESOURCE_IRQ,
	100	},
	101	};
	102
5cf09421	103	struct platform_device mxc_uart_device3 = {
e3d13ff4 SH	104	.name = "imx-uart",
	105	.id = 3,
	106	.resource = uart3,
	107	.num_resources = ARRAY_SIZE(uart3),
	108	};
	109
	110	static struct resource uart4[] = {
	111	{
	112	.start = UART5_BASE_ADDR,
	113	.end = UART5_BASE_ADDR + 0x0B5,
	114	.flags = IORESOURCE_MEM,
	115	}, {
	116	.start = MXC_INT_UART5,
	117	.end = MXC_INT_UART5,
	118	.flags = IORESOURCE_IRQ,
	119	},
	120	};
	121
5cf09421	122	struct platform_device mxc_uart_device4 = {
e3d13ff4 SH	123	.name = "imx-uart",
	124	.id = 4,
	125	.resource = uart4,
	126	.num_resources = ARRAY_SIZE(uart4),
	127	};
9536ff33	128	#endif /* CONFIG_ARCH_MX31 */
e3d13ff4	129
07bd1a6c JB	130	/* GPIO port description */
	131	static struct mxc_gpio_port imx_gpio_ports[] = {
	132	[0] = {
	133	.chip.label = "gpio-0",
	134	.base = IO_ADDRESS(GPIO1_BASE_ADDR),
	135	.irq = MXC_INT_GPIO1,
9d631b83	136	.virtual_irq_start = MXC_GPIO_IRQ_START,
07bd1a6c JB	137	},
	138	[1] = {
	139	.chip.label = "gpio-1",
	140	.base = IO_ADDRESS(GPIO2_BASE_ADDR),
	141	.irq = MXC_INT_GPIO2,
9d631b83	142	.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
07bd1a6c JB	143	},
	144	[2] = {
	145	.chip.label = "gpio-2",
	146	.base = IO_ADDRESS(GPIO3_BASE_ADDR),
	147	.irq = MXC_INT_GPIO3,
9d631b83	148	.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
07bd1a6c JB	149	}
	150	};
	151
	152	int __init mxc_register_gpios(void)
	153	{
	154	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
	155	}
a8405929 SH	156
	157	static struct resource mxc_w1_master_resources[] = {
	158	{
	159	.start = OWIRE_BASE_ADDR,
	160	.end = OWIRE_BASE_ADDR + SZ_4K - 1,
	161	.flags = IORESOURCE_MEM,
	162	},
	163	};
	164
	165	struct platform_device mxc_w1_master_device = {
	166	.name = "mxc_w1",
	167	.id = 0,
	168	.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
	169	.resource = mxc_w1_master_resources,
	170	};
cb96cf1a SH	171
	172	static struct resource mxc_nand_resources[] = {
	173	{
9536ff33 SH	174	.start = 0, /* runtime dependent */
9536ff33 SH	175	.end = 0,
cb96cf1a SH	176	.flags = IORESOURCE_MEM
	177	}, {
	178	.start = MXC_INT_NANDFC,
	179	.end = MXC_INT_NANDFC,
	180	.flags = IORESOURCE_IRQ
	181	},
	182	};
	183
	184	struct platform_device mxc_nand_device = {
	185	.name = "mxc_nand",
	186	.id = 0,
	187	.num_resources = ARRAY_SIZE(mxc_nand_resources),
	188	.resource = mxc_nand_resources,
	189	};
39d1dc06 MB	190
	191	static struct resource mxc_i2c0_resources[] = {
	192	{
	193	.start = I2C_BASE_ADDR,
	194	.end = I2C_BASE_ADDR + SZ_4K - 1,
	195	.flags = IORESOURCE_MEM,
	196	},
	197	{
	198	.start = MXC_INT_I2C,
	199	.end = MXC_INT_I2C,
	200	.flags = IORESOURCE_IRQ,
	201	},
	202	};
	203
	204	struct platform_device mxc_i2c_device0 = {
	205	.name = "imx-i2c",
	206	.id = 0,
	207	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
	208	.resource = mxc_i2c0_resources,
	209	};
	210
	211	static struct resource mxc_i2c1_resources[] = {
	212	{
	213	.start = I2C2_BASE_ADDR,
	214	.end = I2C2_BASE_ADDR + SZ_4K - 1,
	215	.flags = IORESOURCE_MEM,
	216	},
	217	{
	218	.start = MXC_INT_I2C2,
	219	.end = MXC_INT_I2C2,
	220	.flags = IORESOURCE_IRQ,
	221	},
	222	};
	223
	224	struct platform_device mxc_i2c_device1 = {
	225	.name = "imx-i2c",
	226	.id = 1,
	227	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
	228	.resource = mxc_i2c1_resources,
	229	};
	230
	231	static struct resource mxc_i2c2_resources[] = {
	232	{
	233	.start = I2C3_BASE_ADDR,
	234	.end = I2C3_BASE_ADDR + SZ_4K - 1,
	235	.flags = IORESOURCE_MEM,
	236	},
	237	{
	238	.start = MXC_INT_I2C3,
	239	.end = MXC_INT_I2C3,
	240	.flags = IORESOURCE_IRQ,
	241	},
	242	};
	243
	244	struct platform_device mxc_i2c_device2 = {
	245	.name = "imx-i2c",
	246	.id = 2,
	247	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
	248	.resource = mxc_i2c2_resources,
	249	};
ca489f8e	250
2adc1d65 SH	251	#ifdef CONFIG_ARCH_MX31
	252	static struct resource mxcsdhc0_resources[] = {
	253	{
	254	.start = MMC_SDHC1_BASE_ADDR,
	255	.end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
	256	.flags = IORESOURCE_MEM,
	257	}, {
	258	.start = MXC_INT_MMC_SDHC1,
	259	.end = MXC_INT_MMC_SDHC1,
	260	.flags = IORESOURCE_IRQ,
	261	},
	262	};
	263
	264	static struct resource mxcsdhc1_resources[] = {
	265	{
	266	.start = MMC_SDHC2_BASE_ADDR,
	267	.end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
	268	.flags = IORESOURCE_MEM,
	269	}, {
	270	.start = MXC_INT_MMC_SDHC2,
	271	.end = MXC_INT_MMC_SDHC2,
	272	.flags = IORESOURCE_IRQ,
	273	},
	274	};
	275
	276	struct platform_device mxcsdhc_device0 = {
	277	.name = "mxc-mmc",
	278	.id = 0,
	279	.num_resources = ARRAY_SIZE(mxcsdhc0_resources),
	280	.resource = mxcsdhc0_resources,
	281	};
	282
	283	struct platform_device mxcsdhc_device1 = {
	284	.name = "mxc-mmc",
	285	.id = 1,
	286	.num_resources = ARRAY_SIZE(mxcsdhc1_resources),
	287	.resource = mxcsdhc1_resources,
	288	};
45001e92 ACA	289
	290	static struct resource rnga_resources[] = {
	291	{
	292	.start = RNGA_BASE_ADDR,
	293	.end = RNGA_BASE_ADDR + 0x28,
	294	.flags = IORESOURCE_MEM,
	295	},
	296	};
	297
	298	struct platform_device mxc_rnga_device = {
	299	.name = "mxc_rnga",
	300	.id = -1,
	301	.num_resources = 1,
	302	.resource = rnga_resources,
	303	};
2adc1d65 SH	304	#endif /* CONFIG_ARCH_MX31 */
2adc1d65 SH	305
ca489f8e VL	306	/* i.MX31 Image Processing Unit */
	307
	308	/* The resource order is important! */
	309	static struct resource mx3_ipu_rsrc[] = {
	310	{
	311	.start = IPU_CTRL_BASE_ADDR,
	312	.end = IPU_CTRL_BASE_ADDR + 0x5F,
	313	.flags = IORESOURCE_MEM,
	314	}, {
	315	.start = IPU_CTRL_BASE_ADDR + 0x88,
	316	.end = IPU_CTRL_BASE_ADDR + 0xB3,
	317	.flags = IORESOURCE_MEM,
	318	}, {
	319	.start = MXC_INT_IPU_SYN,
	320	.end = MXC_INT_IPU_SYN,
	321	.flags = IORESOURCE_IRQ,
	322	}, {
	323	.start = MXC_INT_IPU_ERR,
	324	.end = MXC_INT_IPU_ERR,
	325	.flags = IORESOURCE_IRQ,
	326	},
	327	};
	328
	329	struct platform_device mx3_ipu = {
	330	.name = "ipu-core",
	331	.id = -1,
	332	.num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
	333	.resource = mx3_ipu_rsrc,
	334	};
	335
	336	static struct resource fb_resources[] = {
	337	{
	338	.start = IPU_CTRL_BASE_ADDR + 0xB4,
	339	.end = IPU_CTRL_BASE_ADDR + 0x1BF,
	340	.flags = IORESOURCE_MEM,
	341	},
	342	};
	343
	344	struct platform_device mx3_fb = {
	345	.name = "mx3_sdc_fb",
	346	.id = -1,
	347	.num_resources = ARRAY_SIZE(fb_resources),
	348	.resource = fb_resources,
	349	.dev = {
9c70e227	350	.coherent_dma_mask = DMA_BIT_MASK(32),
ca489f8e VL	351	},
ca489f8e VL	352	};
9536ff33	353
9c70e227 VL	354	static struct resource camera_resources[] = {
	355	{
	356	.start = IPU_CTRL_BASE_ADDR + 0x60,
	357	.end = IPU_CTRL_BASE_ADDR + 0x87,
	358	.flags = IORESOURCE_MEM,
	359	},
	360	};
	361
	362	struct platform_device mx3_camera = {
	363	.name = "mx3-camera",
	364	.id = 0,
	365	.num_resources = ARRAY_SIZE(camera_resources),
	366	.resource = camera_resources,
	367	.dev = {
	368	.coherent_dma_mask = DMA_BIT_MASK(32),
	369	},
	370	};
	371
eb05bbeb GL	372	static struct resource otg_resources[] = {
	373	{
	374	.start = OTG_BASE_ADDR,
	375	.end = OTG_BASE_ADDR + 0x1ff,
	376	.flags = IORESOURCE_MEM,
	377	}, {
	378	.start = MXC_INT_USB3,
	379	.end = MXC_INT_USB3,
	380	.flags = IORESOURCE_IRQ,
	381	},
	382	};
	383
	384	static u64 otg_dmamask = DMA_BIT_MASK(32);
	385
	386	/* OTG gadget device */
	387	struct platform_device mxc_otg_udc_device = {
	388	.name = "fsl-usb2-udc",
	389	.id = -1,
	390	.dev = {
	391	.dma_mask = &otg_dmamask,
	392	.coherent_dma_mask = DMA_BIT_MASK(32),
	393	},
	394	.resource = otg_resources,
	395	.num_resources = ARRAY_SIZE(otg_resources),
	396	};
	397
9536ff33 SH	398	#ifdef CONFIG_ARCH_MX35
	399	static struct resource mxc_fec_resources[] = {
	400	{
	401	.start = MXC_FEC_BASE_ADDR,
	402	.end = MXC_FEC_BASE_ADDR + 0xfff,
	403	.flags = IORESOURCE_MEM
	404	}, {
	405	.start = MXC_INT_FEC,
	406	.end = MXC_INT_FEC,
	407	.flags = IORESOURCE_IRQ
	408	},
	409	};
	410
	411	struct platform_device mxc_fec_device = {
	412	.name = "fec",
	413	.id = 0,
	414	.num_resources = ARRAY_SIZE(mxc_fec_resources),
	415	.resource = mxc_fec_resources,
	416	};
	417	#endif
	418
	419	static int mx3_devices_init(void)
	420	{
	421	if (cpu_is_mx31()) {
	422	mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
	423	mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
45001e92	424	mxc_register_device(&mxc_rnga_device, NULL);
9536ff33 SH	425	}
	426	if (cpu_is_mx35()) {
	427	mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
	428	mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
	429	}
	430
	431	return 0;
	432	}
	433
	434	subsys_initcall(mx3_devices_init);