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ARM i.MX ehci: do ehci init in board specific functions
[deliverable/linux.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
1553a1ec
FE		 16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/irq.h>
135cad36 20#include <linux/gpio.h>
2b0c3677 21#include <linux/platform_device.h>
ae7a3f13
AP		 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h>
24#include <linux/regulator/machine.h>
1c50e672
FE		 25#include <linux/usb/otg.h>
26#include <linux/usb/ulpi.h>
1553a1ec
FE		 27
28#include <mach/hardware.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/time.h>
32#include <asm/memory.h>
33#include <asm/mach/map.h>
34#include <mach/common.h>
1553a1ec 35#include <mach/iomux-mx3.h>
c5d38f08 36#include <mach/3ds_debugboard.h>
1c50e672 37#include <mach/ulpi.h>
a2ceeef5
UKK		 38
39#include "devices-imx31.h"
1553a1ec
FE		 40#include "devices.h"
41
b396dc45
UKK		 42/* CPLD IRQ line for external uart, external ethernet etc */
43#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
44
b396dc45
UKK		 45/*
46 * This file contains the board-specific initialization routines.
1553a1ec
FE		 47 */
48
11a332ad 49static int mx31_3ds_pins[] = {
153fa1d8 50 /* UART1 */
63d97667
VL		 51 MX31_PIN_CTS1__CTS1,
52 MX31_PIN_RTS1__RTS1,
53 MX31_PIN_TXD1__TXD1,
135cad36
ML		 54 MX31_PIN_RXD1__RXD1,
55 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
a1ac4424
AP		 56 /* SPI 1 */
57 MX31_PIN_CSPI2_SCLK__SCLK,
58 MX31_PIN_CSPI2_MOSI__MOSI,
59 MX31_PIN_CSPI2_MISO__MISO,
60 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
61 MX31_PIN_CSPI2_SS0__SS0,
62 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 63 /* MC13783 IRQ */
64 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 65 /* USB OTG reset */
66 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
67 /* USB OTG */
68 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
69 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
70 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
71 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
72 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
73 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
74 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
75 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
76 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
77 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
78 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
79 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 80 /*Keyboard*/
81 MX31_PIN_KEY_ROW0_KEY_ROW0,
82 MX31_PIN_KEY_ROW1_KEY_ROW1,
83 MX31_PIN_KEY_ROW2_KEY_ROW2,
84 MX31_PIN_KEY_COL0_KEY_COL0,
85 MX31_PIN_KEY_COL1_KEY_COL1,
86 MX31_PIN_KEY_COL2_KEY_COL2,
87 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 88 /* USB Host 2 */
89 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
90 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
91 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
92 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
93 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
94 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
95 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
96 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
97 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
98 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
99 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
100 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
101 /* USB Host2 reset */
102 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
54c1f636
AP		 103};
104
105/*
106 * Matrix keyboard
107 */
108
109static const uint32_t mx31_3ds_keymap[] = {
110 KEY(0, 0, KEY_UP),
111 KEY(0, 1, KEY_DOWN),
112 KEY(1, 0, KEY_RIGHT),
113 KEY(1, 1, KEY_LEFT),
114 KEY(1, 2, KEY_ENTER),
115 KEY(2, 0, KEY_F6),
116 KEY(2, 1, KEY_F8),
117 KEY(2, 2, KEY_F9),
118 KEY(2, 3, KEY_F10),
119};
120
d690b4c4 121static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 122 .keymap = mx31_3ds_keymap,
123 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 124};
125
126/* Regulators */
127static struct regulator_init_data pwgtx_init = {
128 .constraints = {
129 .boot_on = 1,
130 .always_on = 1,
131 },
132};
133
0d95b75e
FE		 134static struct regulator_init_data gpo_init = {
135 .constraints = {
136 .boot_on = 1,
137 .always_on = 1,
138 }
139};
140
5836372e 141static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 142 {
57c78e35 143 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 144 .init_data = &pwgtx_init,
145 }, {
57c78e35 146 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 147 .init_data = &pwgtx_init,
0d95b75e
FE		 148 }, {
149
c97b7393 150 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 151 .init_data = &gpo_init,
152 }, {
c97b7393 153 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 154 .init_data = &gpo_init,
ae7a3f13
AP		 155 },
156};
157
158/* MC13783 */
5836372e 159static struct mc13xxx_platform_data mc13783_pdata __initdata = {
ae7a3f13
AP		 160 .regulators = mx31_3ds_regulators,
161 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
5836372e 162 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
a1ac4424
AP		 163};
164
165/* SPI */
166static int spi1_internal_chipselect[] = {
167 MXC_SPI_CS(0),
168 MXC_SPI_CS(2),
169};
170
06606ff1 171static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 172 .chipselect = spi1_internal_chipselect,
173 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 174};
175
ae7a3f13
AP		 176static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
177 {
178 .modalias = "mc13783",
179 .max_speed_hz = 1000000,
180 .bus_num = 1,
181 .chip_select = 1, /* SS2 */
182 .platform_data = &mc13783_pdata,
183 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
184 .mode = SPI_CS_HIGH,
185 },
186};
187
a1b67b95
AP		 188/*
189 * NAND Flash
190 */
a2ceeef5
UKK		 191static const struct mxc_nand_platform_data
192mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 193 .width = 1,
194 .hw_ecc = 1,
195#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
196 .flash_bbt = 1,
197#endif
198};
199
a2ef4562
ML		 200/*
201 * USB OTG
202 */
203
204#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
205 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
206
207#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 208#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 209
41f63475 210static int mx31_3ds_usbotg_init(void)
a2ef4562 211{
41f63475
FE		 212 int err;
213
a2ef4562
ML		 214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
216 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
217 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
218 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
219 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
220 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
221 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
222 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
223 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
224 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
225 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
226
41f63475
FE		 227 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
228 if (err) {
229 pr_err("Failed to request the USB OTG reset gpio\n");
230 return err;
231 }
232
233 err = gpio_direction_output(USBOTG_RST_B, 0);
234 if (err) {
235 pr_err("Failed to drive the USB OTG reset gpio\n");
236 goto usbotg_free_reset;
237 }
238
a2ef4562
ML		 239 mdelay(1);
240 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 241 return 0;
242
243usbotg_free_reset:
244 gpio_free(USBOTG_RST_B);
245 return err;
a2ef4562
ML		 246}
247
4bd597b6
SH		 248#if defined(CONFIG_USB_ULPI)
249static int mx31_3ds_otg_init(struct platform_device *pdev)
250{
251 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
252}
253
254static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 255{
256 int err;
257
258 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
259 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
260 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
261 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
262 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
263 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
264 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
265 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
266 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
267 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
268 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
269 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
270
271 err = gpio_request(USBH2_RST_B, "usbh2-reset");
272 if (err) {
273 pr_err("Failed to request the USB Host 2 reset gpio\n");
274 return err;
275 }
276
277 err = gpio_direction_output(USBH2_RST_B, 0);
278 if (err) {
279 pr_err("Failed to drive the USB Host 2 reset gpio\n");
280 goto usbotg_free_reset;
281 }
282
283 mdelay(1);
284 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 285
286 mdelay(10);
287
288 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 289
290usbotg_free_reset:
291 gpio_free(USBH2_RST_B);
292 return err;
293}
294
1c50e672 295static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 296 .init = mx31_3ds_otg_init,
1c50e672 297 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 298};
0d95b75e
FE		 299
300static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
301 .init = mx31_3ds_host2_init,
302 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 303};
1c50e672
FE		 304#endif
305
9e1dde33 306static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 307 .operating_mode = FSL_USB2_DR_DEVICE,
308 .phy_mode = FSL_USB2_PHY_ULPI,
309};
310
1c50e672
FE		 311static int otg_mode_host;
312
313static int __init mx31_3ds_otg_mode(char *options)
314{
315 if (!strcmp(options, "host"))
316 otg_mode_host = 1;
317 else if (!strcmp(options, "device"))
318 otg_mode_host = 0;
319 else
320 pr_info("otg_mode neither \"host\" nor \"device\". "
321 "Defaulting to device\n");
322 return 0;
323}
324__setup("otg_mode=", mx31_3ds_otg_mode);
325
16cf5c41 326static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 327 .flags = IMXUART_HAVE_RTSCTS,
328};
1553a1ec 329
1553a1ec
FE		 330/*!
331 * Board specific initialization.
332 */
333static void __init mxc_board_init(void)
334{
11a332ad
AP		 335 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
336 "mx31_3ds");
153fa1d8 337
16cf5c41 338 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 339 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 340
4a74bddc 341 imx31_add_spi_imx1(&spi1_pdata);
ae7a3f13
AP		 342 spi_register_board_info(mx31_3ds_spi_devs,
343 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 344
d690b4c4 345 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 346
a2ef4562 347 mx31_3ds_usbotg_init();
1c50e672
FE		 348#if defined(CONFIG_USB_ULPI)
349 if (otg_mode_host) {
350 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
351 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
352
353 imx31_add_mxc_ehci_otg(&otg_pdata);
354 }
0d95b75e
FE		 355 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
356 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
357 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
1c50e672
FE		 358#endif
359 if (!otg_mode_host)
360 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 361
b8be7b9a
RP		 362 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
363 printk(KERN_WARNING "Init of the debug board failed, all "
364 "devices on the debug board are unusable.\n");
bfdde3a9 365 imx31_add_imx2_wdt(NULL);
1553a1ec
FE		 366}
367
11a332ad 368static void __init mx31_3ds_timer_init(void)
1553a1ec 369{
30c730f8 370 mx31_clocks_init(26000000);
1553a1ec
FE		 371}
372
11a332ad
AP		 373static struct sys_timer mx31_3ds_timer = {
374 .init = mx31_3ds_timer_init,
1553a1ec
FE		 375};
376
377/*
378 * The following uses standard kernel macros defined in arch.h in order to
11a332ad 379 * initialize __mach_desc_MX31_3DS data structure.
1553a1ec
FE		 380 */
381MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
382 /* Maintainer: Freescale Semiconductor, Inc. */
97976e22
UKK		 383 .boot_params = MX3x_PHYS_OFFSET + 0x100,
384 .map_io = mx31_map_io,
385 .init_early = imx31_init_early,
386 .init_irq = mx31_init_irq,
387 .timer = &mx31_3ds_timer,
388 .init_machine = mxc_board_init,
1553a1ec 389MACHINE_END
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