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1553a1ec FE |
1 | /* |
2 | * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
1553a1ec FE |
13 | */ |
14 | ||
a2ef4562 | 15 | #include <linux/delay.h> |
1553a1ec FE |
16 | #include <linux/types.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/irq.h> | |
135cad36 | 20 | #include <linux/gpio.h> |
2b0c3677 | 21 | #include <linux/platform_device.h> |
ae7a3f13 AP |
22 | #include <linux/mfd/mc13783.h> |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/regulator/machine.h> | |
54c1f636 | 25 | #include <linux/input/matrix_keypad.h> |
1553a1ec FE |
26 | |
27 | #include <mach/hardware.h> | |
28 | #include <asm/mach-types.h> | |
29 | #include <asm/mach/arch.h> | |
30 | #include <asm/mach/time.h> | |
31 | #include <asm/memory.h> | |
32 | #include <asm/mach/map.h> | |
33 | #include <mach/common.h> | |
1553a1ec | 34 | #include <mach/iomux-mx3.h> |
c5d38f08 | 35 | #include <mach/3ds_debugboard.h> |
a2ceeef5 UKK |
36 | |
37 | #include "devices-imx31.h" | |
1553a1ec FE |
38 | #include "devices.h" |
39 | ||
b396dc45 UKK |
40 | /* CPLD IRQ line for external uart, external ethernet etc */ |
41 | #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1) | |
42 | ||
b396dc45 UKK |
43 | /* |
44 | * This file contains the board-specific initialization routines. | |
1553a1ec FE |
45 | */ |
46 | ||
11a332ad | 47 | static int mx31_3ds_pins[] = { |
153fa1d8 | 48 | /* UART1 */ |
63d97667 VL |
49 | MX31_PIN_CTS1__CTS1, |
50 | MX31_PIN_RTS1__RTS1, | |
51 | MX31_PIN_TXD1__TXD1, | |
135cad36 ML |
52 | MX31_PIN_RXD1__RXD1, |
53 | IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), | |
a1ac4424 AP |
54 | /* SPI 1 */ |
55 | MX31_PIN_CSPI2_SCLK__SCLK, | |
56 | MX31_PIN_CSPI2_MOSI__MOSI, | |
57 | MX31_PIN_CSPI2_MISO__MISO, | |
58 | MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, | |
59 | MX31_PIN_CSPI2_SS0__SS0, | |
60 | MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ | |
ae7a3f13 AP |
61 | /* MC13783 IRQ */ |
62 | IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), | |
a2ef4562 ML |
63 | /* USB OTG reset */ |
64 | IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), | |
65 | /* USB OTG */ | |
66 | MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, | |
67 | MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, | |
68 | MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, | |
69 | MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, | |
70 | MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, | |
71 | MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, | |
72 | MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, | |
73 | MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, | |
74 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, | |
75 | MX31_PIN_USBOTG_DIR__USBOTG_DIR, | |
76 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, | |
77 | MX31_PIN_USBOTG_STP__USBOTG_STP, | |
54c1f636 AP |
78 | /*Keyboard*/ |
79 | MX31_PIN_KEY_ROW0_KEY_ROW0, | |
80 | MX31_PIN_KEY_ROW1_KEY_ROW1, | |
81 | MX31_PIN_KEY_ROW2_KEY_ROW2, | |
82 | MX31_PIN_KEY_COL0_KEY_COL0, | |
83 | MX31_PIN_KEY_COL1_KEY_COL1, | |
84 | MX31_PIN_KEY_COL2_KEY_COL2, | |
85 | MX31_PIN_KEY_COL3_KEY_COL3, | |
86 | }; | |
87 | ||
88 | /* | |
89 | * Matrix keyboard | |
90 | */ | |
91 | ||
92 | static const uint32_t mx31_3ds_keymap[] = { | |
93 | KEY(0, 0, KEY_UP), | |
94 | KEY(0, 1, KEY_DOWN), | |
95 | KEY(1, 0, KEY_RIGHT), | |
96 | KEY(1, 1, KEY_LEFT), | |
97 | KEY(1, 2, KEY_ENTER), | |
98 | KEY(2, 0, KEY_F6), | |
99 | KEY(2, 1, KEY_F8), | |
100 | KEY(2, 2, KEY_F9), | |
101 | KEY(2, 3, KEY_F10), | |
102 | }; | |
103 | ||
104 | static struct matrix_keymap_data mx31_3ds_keymap_data = { | |
105 | .keymap = mx31_3ds_keymap, | |
106 | .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), | |
ae7a3f13 AP |
107 | }; |
108 | ||
109 | /* Regulators */ | |
110 | static struct regulator_init_data pwgtx_init = { | |
111 | .constraints = { | |
112 | .boot_on = 1, | |
113 | .always_on = 1, | |
114 | }, | |
115 | }; | |
116 | ||
117 | static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { | |
118 | { | |
119 | .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */ | |
120 | .init_data = &pwgtx_init, | |
121 | }, { | |
122 | .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */ | |
123 | .init_data = &pwgtx_init, | |
124 | }, | |
125 | }; | |
126 | ||
127 | /* MC13783 */ | |
128 | static struct mc13783_platform_data mc13783_pdata __initdata = { | |
129 | .regulators = mx31_3ds_regulators, | |
130 | .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), | |
131 | .flags = MC13783_USE_REGULATOR, | |
a1ac4424 AP |
132 | }; |
133 | ||
134 | /* SPI */ | |
135 | static int spi1_internal_chipselect[] = { | |
136 | MXC_SPI_CS(0), | |
137 | MXC_SPI_CS(2), | |
138 | }; | |
139 | ||
06606ff1 | 140 | static const struct spi_imx_master spi1_pdata __initconst = { |
a1ac4424 AP |
141 | .chipselect = spi1_internal_chipselect, |
142 | .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect), | |
63d97667 VL |
143 | }; |
144 | ||
ae7a3f13 AP |
145 | static struct spi_board_info mx31_3ds_spi_devs[] __initdata = { |
146 | { | |
147 | .modalias = "mc13783", | |
148 | .max_speed_hz = 1000000, | |
149 | .bus_num = 1, | |
150 | .chip_select = 1, /* SS2 */ | |
151 | .platform_data = &mc13783_pdata, | |
152 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), | |
153 | .mode = SPI_CS_HIGH, | |
154 | }, | |
155 | }; | |
156 | ||
a1b67b95 AP |
157 | /* |
158 | * NAND Flash | |
159 | */ | |
a2ceeef5 UKK |
160 | static const struct mxc_nand_platform_data |
161 | mx31_3ds_nand_board_info __initconst = { | |
a1b67b95 AP |
162 | .width = 1, |
163 | .hw_ecc = 1, | |
164 | #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT | |
165 | .flash_bbt = 1, | |
166 | #endif | |
167 | }; | |
168 | ||
a2ef4562 ML |
169 | /* |
170 | * USB OTG | |
171 | */ | |
172 | ||
173 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | |
174 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | |
175 | ||
176 | #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) | |
177 | ||
41f63475 | 178 | static int mx31_3ds_usbotg_init(void) |
a2ef4562 | 179 | { |
41f63475 FE |
180 | int err; |
181 | ||
a2ef4562 ML |
182 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); |
183 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); | |
184 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); | |
185 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); | |
186 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); | |
187 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); | |
188 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); | |
189 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); | |
190 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); | |
191 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); | |
192 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); | |
193 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); | |
194 | ||
41f63475 FE |
195 | err = gpio_request(USBOTG_RST_B, "otgusb-reset"); |
196 | if (err) { | |
197 | pr_err("Failed to request the USB OTG reset gpio\n"); | |
198 | return err; | |
199 | } | |
200 | ||
201 | err = gpio_direction_output(USBOTG_RST_B, 0); | |
202 | if (err) { | |
203 | pr_err("Failed to drive the USB OTG reset gpio\n"); | |
204 | goto usbotg_free_reset; | |
205 | } | |
206 | ||
a2ef4562 ML |
207 | mdelay(1); |
208 | gpio_set_value(USBOTG_RST_B, 1); | |
41f63475 FE |
209 | return 0; |
210 | ||
211 | usbotg_free_reset: | |
212 | gpio_free(USBOTG_RST_B); | |
213 | return err; | |
a2ef4562 ML |
214 | } |
215 | ||
9e1dde33 | 216 | static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { |
a2ef4562 ML |
217 | .operating_mode = FSL_USB2_DR_DEVICE, |
218 | .phy_mode = FSL_USB2_PHY_ULPI, | |
219 | }; | |
220 | ||
16cf5c41 | 221 | static const struct imxuart_platform_data uart_pdata __initconst = { |
153fa1d8 ML |
222 | .flags = IMXUART_HAVE_RTSCTS, |
223 | }; | |
1553a1ec | 224 | |
135cad36 ML |
225 | /* |
226 | * Set up static virtual mappings. | |
227 | */ | |
11a332ad | 228 | static void __init mx31_3ds_map_io(void) |
135cad36 ML |
229 | { |
230 | mx31_map_io(); | |
135cad36 ML |
231 | } |
232 | ||
1553a1ec FE |
233 | /*! |
234 | * Board specific initialization. | |
235 | */ | |
236 | static void __init mxc_board_init(void) | |
237 | { | |
11a332ad AP |
238 | mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins), |
239 | "mx31_3ds"); | |
153fa1d8 | 240 | |
16cf5c41 | 241 | imx31_add_imx_uart0(&uart_pdata); |
a2ceeef5 | 242 | imx31_add_mxc_nand(&mx31_3ds_nand_board_info); |
ae7a3f13 | 243 | |
4a74bddc | 244 | imx31_add_spi_imx1(&spi1_pdata); |
ae7a3f13 AP |
245 | spi_register_board_info(mx31_3ds_spi_devs, |
246 | ARRAY_SIZE(mx31_3ds_spi_devs)); | |
135cad36 | 247 | |
54c1f636 AP |
248 | mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); |
249 | ||
a2ef4562 | 250 | mx31_3ds_usbotg_init(); |
9e1dde33 | 251 | imx31_add_fsl_usb2_udc(&usbotg_pdata); |
a2ef4562 | 252 | |
b8be7b9a RP |
253 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
254 | printk(KERN_WARNING "Init of the debug board failed, all " | |
255 | "devices on the debug board are unusable.\n"); | |
1553a1ec FE |
256 | } |
257 | ||
11a332ad | 258 | static void __init mx31_3ds_timer_init(void) |
1553a1ec | 259 | { |
30c730f8 | 260 | mx31_clocks_init(26000000); |
1553a1ec FE |
261 | } |
262 | ||
11a332ad AP |
263 | static struct sys_timer mx31_3ds_timer = { |
264 | .init = mx31_3ds_timer_init, | |
1553a1ec FE |
265 | }; |
266 | ||
267 | /* | |
268 | * The following uses standard kernel macros defined in arch.h in order to | |
11a332ad | 269 | * initialize __mach_desc_MX31_3DS data structure. |
1553a1ec FE |
270 | */ |
271 | MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") | |
272 | /* Maintainer: Freescale Semiconductor, Inc. */ | |
34101237 | 273 | .boot_params = MX3x_PHYS_OFFSET + 0x100, |
11a332ad | 274 | .map_io = mx31_3ds_map_io, |
c5aa0ad0 | 275 | .init_irq = mx31_init_irq, |
1553a1ec | 276 | .init_machine = mxc_board_init, |
11a332ad | 277 | .timer = &mx31_3ds_timer, |
1553a1ec | 278 | MACHINE_END |