[deliverable/linux.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c

/*
 *  Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/platform_device.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31_3ds.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/mxc_nand.h>
#include "devices.h"

/*!
 * @file mx31_3ds.c
 *
 * @brief This file contains the board-specific initialization routines.
 *
 * @ingroup System
 */

static int mx31_3ds_pins[] = {
	/* UART1 */
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
};

/*
 * NAND Flash
 */
static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
	.width		= 1,
	.hw_ecc		= 1,
#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	.flash_bbt	= 1,
#endif
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

/*
 * Support for the SMSC9217 on the Debug board.
 */

static struct smsc911x_platform_config smsc911x_config = {
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= LAN9217_BASE_ADDR,
		.end		= LAN9217_BASE_ADDR + 0xff,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= EXPIO_INT_ENET,
		.end		= EXPIO_INT_ENET,
		.flags		= IORESOURCE_IRQ,
	},
};

static struct platform_device smsc911x_device = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_config,
	},
};

/*
 * Routines for the CPLD on the debug board. It contains a CPLD handling
 * LEDs, switches, interrupts for Ethernet.
 */

static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
{
	uint32_t imr_val;
	uint32_t int_valid;
	uint32_t expio_irq;

	imr_val = __raw_readw(CPLD_INT_MASK_REG);
	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;

	expio_irq = MXC_EXP_IO_BASE;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;
		generic_handle_irq(expio_irq);
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param irq           an expio virtual irq number
 */
static void expio_mask_irq(uint32_t irq)
{
	uint16_t reg;
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* mask the interrupt */
	reg = __raw_readw(CPLD_INT_MASK_REG);
	reg |= 1 << expio;
	__raw_writew(reg, CPLD_INT_MASK_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param irq           an expanded io virtual irq number
 */
static void expio_ack_irq(uint32_t irq)
{
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* clear the interrupt status */
	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
	__raw_writew(0, CPLD_INT_RESET_REG);
	/* mask the interrupt */
	expio_mask_irq(irq);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param irq           a expio virtual irq number
 */
static void expio_unmask_irq(uint32_t irq)
{
	uint16_t reg;
	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);

	/* unmask the interrupt */
	reg = __raw_readw(CPLD_INT_MASK_REG);
	reg &= ~(1 << expio);
	__raw_writew(reg, CPLD_INT_MASK_REG);
}

static struct irq_chip expio_irq_chip = {
	.ack = expio_ack_irq,
	.mask = expio_mask_irq,
	.unmask = expio_unmask_irq,
};

static int __init mx31_3ds_init_expio(void)
{
	int i;
	int ret;

	/* Check if there's a debug board connected */
	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
		/* No Debug board found */
		return -ENODEV;
	}

	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
		__raw_readw(CPLD_CODE_VER_REG));

	/*
	 * Configure INT line as GPIO input
	 */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
	if (ret)
		pr_warning("could not get LAN irq gpio\n");
	else
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));

	/* Disable the interrupts and clear the status */
	__raw_writew(0, CPLD_INT_MASK_REG);
	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
	__raw_writew(0, CPLD_INT_RESET_REG);
	__raw_writew(0x1F, CPLD_INT_MASK_REG);
	for (i = MXC_EXP_IO_BASE;
	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);

	return 0;
}

/*
 * This structure defines the MX31 memory map.
 */
static struct map_desc mx31_3ds_io_desc[] __initdata = {
	{
		.virtual = MX31_CS5_BASE_ADDR_VIRT,
		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
		.length = MX31_CS5_SIZE,
		.type = MT_DEVICE,
	},
};

/*
 * Set up static virtual mappings.
 */
static void __init mx31_3ds_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
				      "mx31_3ds");

	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);

	if (!mx31_3ds_init_expio())
		platform_device_register(&smsc911x_device);
}

static void __init mx31_3ds_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31_3ds_timer = {
	.init	= mx31_3ds_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31_3DS data structure.
 */
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.phys_io	= MX31_AIPS1_BASE_ADDR,
	.io_pg_offst	= (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31_3ds_map_io,
	.init_irq       = mx31_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31_3ds_timer,
MACHINE_END
Commit	Line	Data
1553a1ec FE	1	/*
	2	* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#include <linux/types.h>
	20	#include <linux/init.h>
	21	#include <linux/clk.h>
	22	#include <linux/irq.h>
135cad36	23	#include <linux/gpio.h>
2b0c3677 ML	24	#include <linux/smsc911x.h>
2b0c3677 ML	25	#include <linux/platform_device.h>
1553a1ec FE	26
	27	#include <mach/hardware.h>
	28	#include <asm/mach-types.h>
	29	#include <asm/mach/arch.h>
	30	#include <asm/mach/time.h>
	31	#include <asm/memory.h>
	32	#include <asm/mach/map.h>
	33	#include <mach/common.h>
11a332ad	34	#include <mach/board-mx31_3ds.h>
1553a1ec FE	35	#include <mach/imx-uart.h>
1553a1ec FE	36	#include <mach/iomux-mx3.h>
a1b67b95	37	#include <mach/mxc_nand.h>
1553a1ec FE	38	#include "devices.h"
	39
	40	/*!
11a332ad	41	* @file mx31_3ds.c
1553a1ec FE	42	*
	43	* @brief This file contains the board-specific initialization routines.
	44	*
	45	* @ingroup System
	46	*/
	47
11a332ad	48	static int mx31_3ds_pins[] = {
153fa1d8	49	/* UART1 */
63d97667 VL	50	MX31_PIN_CTS1__CTS1,
	51	MX31_PIN_RTS1__RTS1,
	52	MX31_PIN_TXD1__TXD1,
135cad36 ML	53	MX31_PIN_RXD1__RXD1,
135cad36 ML	54	IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
63d97667 VL	55	};
63d97667 VL	56
a1b67b95 AP	57	/*
	58	* NAND Flash
	59	*/
	60	static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
	61	.width = 1,
	62	.hw_ecc = 1,
	63	#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
	64	.flash_bbt = 1,
	65	#endif
	66	};
	67
153fa1d8 ML	68	static struct imxuart_platform_data uart_pdata = {
	69	.flags = IMXUART_HAVE_RTSCTS,
	70	};
1553a1ec	71
2b0c3677 ML	72	/*
	73	* Support for the SMSC9217 on the Debug board.
	74	*/
	75
	76	static struct smsc911x_platform_config smsc911x_config = {
	77	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	78	.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
	79	.flags = SMSC911X_USE_16BIT \| SMSC911X_FORCE_INTERNAL_PHY,
	80	.phy_interface = PHY_INTERFACE_MODE_MII,
	81	};
	82
	83	static struct resource smsc911x_resources[] = {
	84	{
	85	.start = LAN9217_BASE_ADDR,
	86	.end = LAN9217_BASE_ADDR + 0xff,
	87	.flags = IORESOURCE_MEM,
	88	}, {
	89	.start = EXPIO_INT_ENET,
	90	.end = EXPIO_INT_ENET,
	91	.flags = IORESOURCE_IRQ,
	92	},
	93	};
	94
	95	static struct platform_device smsc911x_device = {
	96	.name = "smsc911x",
	97	.id = -1,
	98	.num_resources = ARRAY_SIZE(smsc911x_resources),
	99	.resource = smsc911x_resources,
	100	.dev = {
	101	.platform_data = &smsc911x_config,
	102	},
	103	};
	104
135cad36 ML	105	/*
	106	* Routines for the CPLD on the debug board. It contains a CPLD handling
	107	* LEDs, switches, interrupts for Ethernet.
	108	*/
	109
11a332ad	110	static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
135cad36 ML	111	{
	112	uint32_t imr_val;
	113	uint32_t int_valid;
	114	uint32_t expio_irq;
	115
	116	imr_val = __raw_readw(CPLD_INT_MASK_REG);
	117	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
	118
	119	expio_irq = MXC_EXP_IO_BASE;
	120	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	121	if ((int_valid & 1) == 0)
	122	continue;
	123	generic_handle_irq(expio_irq);
	124	}
	125	}
	126
	127	/*
	128	* Disable an expio pin's interrupt by setting the bit in the imr.
	129	* @param irq an expio virtual irq number
	130	*/
	131	static void expio_mask_irq(uint32_t irq)
	132	{
	133	uint16_t reg;
	134	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	135
	136	/* mask the interrupt */
	137	reg = __raw_readw(CPLD_INT_MASK_REG);
	138	reg \|= 1 << expio;
	139	__raw_writew(reg, CPLD_INT_MASK_REG);
	140	}
	141
	142	/*
	143	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
	144	* @param irq an expanded io virtual irq number
	145	*/
	146	static void expio_ack_irq(uint32_t irq)
	147	{
	148	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	149
	150	/* clear the interrupt status */
	151	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
	152	__raw_writew(0, CPLD_INT_RESET_REG);
	153	/* mask the interrupt */
	154	expio_mask_irq(irq);
	155	}
	156
	157	/*
	158	* Enable a expio pin's interrupt by clearing the bit in the imr.
	159	* @param irq a expio virtual irq number
	160	*/
	161	static void expio_unmask_irq(uint32_t irq)
	162	{
	163	uint16_t reg;
	164	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
	165
	166	/* unmask the interrupt */
	167	reg = __raw_readw(CPLD_INT_MASK_REG);
	168	reg &= ~(1 << expio);
	169	__raw_writew(reg, CPLD_INT_MASK_REG);
	170	}
	171
	172	static struct irq_chip expio_irq_chip = {
	173	.ack = expio_ack_irq,
	174	.mask = expio_mask_irq,
175	.unmask = expio_unmask_irq,
176	};
177
11a332ad	178	static int __init mx31_3ds_init_expio(void)
135cad36 ML	179	{
	180	int i;
	181	int ret;
	182
	183	/* Check if there's a debug board connected */
	184	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) \|\|
	185	(__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) \|\|
	186	(__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
	187	/* No Debug board found */
	188	return -ENODEV;
	189	}
	190
11a332ad	191	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
135cad36 ML	192	__raw_readw(CPLD_CODE_VER_REG));
	193
	194	/*
	195	* Configure INT line as GPIO input
	196	*/
	197	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
	198	if (ret)
	199	pr_warning("could not get LAN irq gpio\n");
	200	else
	201	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
	202
	203	/* Disable the interrupts and clear the status */
	204	__raw_writew(0, CPLD_INT_MASK_REG);
	205	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
	206	__raw_writew(0, CPLD_INT_RESET_REG);
	207	__raw_writew(0x1F, CPLD_INT_MASK_REG);
	208	for (i = MXC_EXP_IO_BASE;
	209	i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	210	i++) {
	211	set_irq_chip(i, &expio_irq_chip);
	212	set_irq_handler(i, handle_level_irq);
	213	set_irq_flags(i, IRQF_VALID);
	214	}
	215	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
11a332ad	216	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
135cad36 ML	217
	218	return 0;
	219	}
	220
	221	/*
	222	* This structure defines the MX31 memory map.
	223	*/
11a332ad	224	static struct map_desc mx31_3ds_io_desc[] __initdata = {
135cad36	225	{
f568dd7f UKK	226	.virtual = MX31_CS5_BASE_ADDR_VIRT,
	227	.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
	228	.length = MX31_CS5_SIZE,
135cad36 ML	229	.type = MT_DEVICE,
	230	},
	231	};
	232
	233	/*
	234	* Set up static virtual mappings.
	235	*/
11a332ad	236	static void __init mx31_3ds_map_io(void)
135cad36 ML	237	{
135cad36 ML	238	mx31_map_io();
11a332ad	239	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
135cad36 ML	240	}
135cad36 ML	241
1553a1ec FE	242	/*!
	243	* Board specific initialization.
	244	*/
	245	static void __init mxc_board_init(void)
	246	{
11a332ad AP	247	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
11a332ad AP	248	"mx31_3ds");
153fa1d8 ML	249
153fa1d8 ML	250	mxc_register_device(&mxc_uart_device0, &uart_pdata);
a1b67b95	251	mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
135cad36	252
11a332ad	253	if (!mx31_3ds_init_expio())
2b0c3677	254	platform_device_register(&smsc911x_device);
1553a1ec FE	255	}
1553a1ec FE	256
11a332ad	257	static void __init mx31_3ds_timer_init(void)
1553a1ec	258	{
30c730f8	259	mx31_clocks_init(26000000);
1553a1ec FE	260	}
1553a1ec FE	261
11a332ad AP	262	static struct sys_timer mx31_3ds_timer = {
11a332ad AP	263	.init = mx31_3ds_timer_init,
1553a1ec FE	264	};
	265
	266	/*
	267	* The following uses standard kernel macros defined in arch.h in order to
11a332ad	268	* initialize __mach_desc_MX31_3DS data structure.
1553a1ec FE	269	*/
	270	MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
	271	/* Maintainer: Freescale Semiconductor, Inc. */
f568dd7f	272	.phys_io = MX31_AIPS1_BASE_ADDR,
321ed164	273	.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237	274	.boot_params = MX3x_PHYS_OFFSET + 0x100,
11a332ad	275	.map_io = mx31_3ds_map_io,
c5aa0ad0	276	.init_irq = mx31_init_irq,
1553a1ec	277	.init_machine = mxc_board_init,
11a332ad	278	.timer = &mx31_3ds_timer,
1553a1ec	279	MACHINE_END