[deliverable/linux.git] / arch / arm / mach-mx3 / mach-mx31ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif

#include "devices-imx31.h"
#include "devices.h"

/* Base address of PBC controller */
#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
/* Offsets for the PBC Controller register */

/* PBC Board interrupt status register */
#define PBC_INTSTATUS           0x000016

/* PBC Board interrupt current status register */
#define PBC_INTCURR_STATUS      0x000018

/* PBC Interrupt mask register set address */
#define PBC_INTMASK_SET         0x00001A

/* PBC Interrupt mask register clear address */
#define PBC_INTMASK_CLEAR       0x00001C

/* External UART A */
#define PBC_SC16C652_UARTA      0x010000

/* External UART B */
#define PBC_SC16C652_UARTB      0x010010

#define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)

#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)

#define EXPIO_INT_XUART_INTA	(MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_XUART_INTB	(MXC_EXP_IO_BASE + 11)

#define MXC_MAX_EXP_IO_LINES	16
/*
 * This file contains the board-specific initialization routines.
 */

#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/*!
 * The serial port definition structure.
 */
static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
		.irq      = EXPIO_INT_XUART_INTA,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	}, {
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
		.irq      = EXPIO_INT_XUART_INTB,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	},
	{},
};

static struct platform_device serial_device = {
	.name	= "serial8250",
	.id	= 0,
	.dev	= {
		.platform_data = serial_platform_data,
	},
};

static int __init mxc_init_extuart(void)
{
	return platform_device_register(&serial_device);
}
#else
static inline int mxc_init_extuart(void)
{
	return 0;
}
#endif

#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static unsigned int uart_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1
};

static inline void mxc_init_imx_uart(void)
{
	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
	mxc_register_device(&mxc_uart_device0, &uart_pdata);
}
#else /* !SERIAL_IMX */
static inline void mxc_init_imx_uart(void)
{
}
#endif /* !SERIAL_IMX */

static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 imr_val;
	u32 int_valid;
	u32 expio_irq;

	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;

	expio_irq = MXC_EXP_IO_BASE;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;

		generic_handle_irq(expio_irq);
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param irq           an expio virtual irq number
 */
static void expio_mask_irq(u32 irq)
{
	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	/* mask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	__raw_readw(PBC_INTMASK_CLEAR_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param irq           an expanded io virtual irq number
 */
static void expio_ack_irq(u32 irq)
{
	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	/* clear the interrupt status */
	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param irq           a expio virtual irq number
 */
static void expio_unmask_irq(u32 irq)
{
	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	/* unmask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}

static struct irq_chip expio_irq_chip = {
	.name = "EXPIO(CPLD)",
	.ack = expio_ack_irq,
	.mask = expio_mask_irq,
	.unmask = expio_unmask_irq,
};

static void __init mx31ads_init_expio(void)
{
	int i;

	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");

	/*
	 * Configure INT line as GPIO input
	 */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");

	/* disable the interrupt and clear the status */
	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
}

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
/* This section defines setup for the Wolfson Microelectronics
 * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 * regulator definitions may be shared with them, but for now they can
 * only be used with this board so would generate warnings about
 * unused statics and some of the configuration is specific to this
 * module.
 */

/* CPU */
static struct regulator_consumer_supply sw1a_consumers[] = {
	{
		.supply = "cpu_vcc",
	}
};

static struct regulator_init_data sw1a_data = {
	.constraints = {
		.name = "SW1A",
		.min_uV = 1275000,
		.max_uV = 1600000,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
				  REGULATOR_CHANGE_MODE,
		.valid_modes_mask = REGULATOR_MODE_NORMAL |
				    REGULATOR_MODE_FAST,
		.state_mem = {
			 .uV = 1400000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	.consumer_supplies = sw1a_consumers,
};

/* System IO - High */
static struct regulator_init_data viohi_data = {
	.constraints = {
		.name = "VIOHO",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.state_mem = {
			 .uV = 2800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* System IO - Low */
static struct regulator_init_data violo_data = {
	.constraints = {
		.name = "VIOLO",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* DDR RAM */
static struct regulator_init_data sw2a_data = {
	.constraints = {
		.name = "SW2A",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.state_disk = {
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 0,
		 },
		.always_on = 1,
		.boot_on = 1,
		.initial_state = PM_SUSPEND_MEM,
	},
};

static struct regulator_init_data ldo1_data = {
	.constraints = {
		.name = "VCAM/VMMC1/VMMC2",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
};

static struct regulator_consumer_supply ldo2_consumers[] = {
	{ .supply = "AVDD", .dev_name = "1-001a" },
	{ .supply = "HPVDD", .dev_name = "1-001a" },
};

/* CODEC and SIM */
static struct regulator_init_data ldo2_data = {
	.constraints = {
		.name = "VESIM/VSIM/AVDD",
		.min_uV = 3300000,
		.max_uV = 3300000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	.consumer_supplies = ldo2_consumers,
};

/* General */
static struct regulator_init_data vdig_data = {
	.constraints = {
		.name = "VDIG",
		.min_uV = 1500000,
		.max_uV = 1500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* Tranceivers */
static struct regulator_init_data ldo4_data = {
	.constraints = {
		.name = "VRF1/CVDD_2.775",
		.min_uV = 2500000,
		.max_uV = 2500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

static struct wm8350_led_platform_data wm8350_led_data = {
	.name            = "wm8350:white",
	.default_trigger = "heartbeat",
	.max_uA          = 27899,
};

static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	.vmid_discharge_msecs = 1000,
	.drain_msecs = 30,
	.cap_discharge_msecs = 700,
	.vmid_charge_msecs = 700,
	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	.dis_out4 = WM8350_DISCHARGE_SLOW,
	.dis_out3 = WM8350_DISCHARGE_SLOW,
	.dis_out2 = WM8350_DISCHARGE_SLOW,
	.dis_out1 = WM8350_DISCHARGE_SLOW,
	.vroi_out4 = WM8350_TIE_OFF_500R,
	.vroi_out3 = WM8350_TIE_OFF_500R,
	.vroi_out2 = WM8350_TIE_OFF_500R,
	.vroi_out1 = WM8350_TIE_OFF_500R,
	.vroi_enable = 0,
	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
};

static int mx31_wm8350_init(struct wm8350 *wm8350)
{
	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);

	/* LEDs */
	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
			     WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
			       WM8350_ISINK_FLASH_DISABLE,
			       WM8350_ISINK_FLASH_TRIG_BIT,
			       WM8350_ISINK_FLASH_DUR_32MS,
			       WM8350_ISINK_FLASH_ON_INSTANT,
			       WM8350_ISINK_FLASH_OFF_INSTANT,
			       WM8350_ISINK_FLASH_MODE_EN);
	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
			       WM8350_ISINK_MODE_BOOST,
			       WM8350_ISINK_ILIM_NORMAL,
			       WM8350_DC5_RMP_20V,
			       WM8350_DC5_FBSRC_ISINKA);
	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
			    &wm8350_led_data);

	wm8350->codec.platform_data = &imx32ads_wm8350_setup;

	regulator_has_full_constraints();

	return 0;
}

static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	.init = mx31_wm8350_init,
	.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
};
#endif

#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	{
		I2C_BOARD_INFO("wm8350", 0x1a),
		.platform_data = &mx31_wm8350_pdata,
		.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	},
#endif
};

static void mxc_init_i2c(void)
{
	i2c_register_board_info(1, mx31ads_i2c1_devices,
				ARRAY_SIZE(mx31ads_i2c1_devices));

	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));

	imx31_add_imx_i2c1(NULL);
}
#else
static void mxc_init_i2c(void)
{
}
#endif

static unsigned int ssi_pins[] = {
	MX31_PIN_SFS5__SFS5,
	MX31_PIN_SCK5__SCK5,
	MX31_PIN_SRXD5__SRXD5,
	MX31_PIN_STXD5__STXD5,
};

static void mxc_init_audio(void)
{
	mxc_register_device(&imx_ssi_device0, NULL);
	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
}

/*!
 * This structure defines static mappings for the i.MX31ADS board.
 */
static struct map_desc mx31ads_io_desc[] __initdata = {
	{
		.virtual	= MX31_CS4_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length		= MX31_CS4_SIZE / 2,
		.type		= MT_DEVICE
	},
};

/*!
 * Set up static virtual mappings.
 */
static void __init mx31ads_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
}

static void __init mx31ads_init_irq(void)
{
	mx31_init_irq();
	mx31ads_init_expio();
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_init_extuart();
	mxc_init_imx_uart();
	mxc_init_i2c();
	mxc_init_audio();
}

static void __init mx31ads_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31ads_timer = {
	.init	= mx31ads_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31ADS data structure.
 */
MACHINE_START(MX31ADS, "Freescale MX31ADS")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.phys_io	= MX31_AIPS1_BASE_ADDR,
	.io_pg_offst	= (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31ads_map_io,
	.init_irq       = mx31ads_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31ads_timer,
MACHINE_END
Commit	Line	Data
52c543f9 QJ	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
52c543f9 QJ	15	*/
	16
	17	#include <linux/types.h>
	18	#include <linux/init.h>
	19	#include <linux/clk.h>
	20	#include <linux/serial_8250.h>
fe7316bf MB	21	#include <linux/gpio.h>
fe7316bf MB	22	#include <linux/i2c.h>
d7568f79	23	#include <linux/irq.h>
52c543f9	24
a09e64fb	25	#include <mach/hardware.h>
52c543f9 QJ	26	#include <asm/mach-types.h>
52c543f9 QJ	27	#include <asm/mach/arch.h>
d0f349fb	28	#include <asm/mach/time.h>
52c543f9 QJ	29	#include <asm/memory.h>
52c543f9 QJ	30	#include <asm/mach/map.h>
a09e64fb	31	#include <mach/common.h>
0741794c GC	32	#include <mach/imx-uart.h>
0741794c GC	33	#include <mach/iomux-mx3.h>
52c543f9	34
fe7316bf MB	35	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	36	#include <linux/mfd/wm8350/audio.h>
	37	#include <linux/mfd/wm8350/core.h>
	38	#include <linux/mfd/wm8350/pmic.h>
	39	#endif
	40
4a9b8b0b	41	#include "devices-imx31.h"
2eca047b SH	42	#include "devices.h"
2eca047b SH	43
ccfa7c26 UKK	44	/* Base address of PBC controller */
	45	#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
	46	/* Offsets for the PBC Controller register */
	47
	48	/* PBC Board interrupt status register */
	49	#define PBC_INTSTATUS 0x000016
	50
	51	/* PBC Board interrupt current status register */
	52	#define PBC_INTCURR_STATUS 0x000018
	53
	54	/* PBC Interrupt mask register set address */
	55	#define PBC_INTMASK_SET 0x00001A
	56
	57	/* PBC Interrupt mask register clear address */
	58	#define PBC_INTMASK_CLEAR 0x00001C
	59
	60	/* External UART A */
	61	#define PBC_SC16C652_UARTA 0x010000
	62
	63	/* External UART B */
	64	#define PBC_SC16C652_UARTB 0x010010
	65
	66	#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
	67	#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
	68	#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
	69	#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
	70
	71	#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
	72	#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
	73
	74	#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
	75	#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
	76
	77	#define MXC_MAX_EXP_IO_LINES 16
	78	/*
	79	* This file contains the board-specific initialization routines.
52c543f9 QJ	80	*/
	81
	82	#if defined(CONFIG_SERIAL_8250) \|\| defined(CONFIG_SERIAL_8250_MODULE)
	83	/*!
	84	* The serial port definition structure.
	85	*/
	86	static struct plat_serial8250_port serial_platform_data[] = {
	87	{
	88	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
f568dd7f	89	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
52c543f9 QJ	90	.irq = EXPIO_INT_XUART_INTA,
	91	.uartclk = 14745600,
	92	.regshift = 0,
	93	.iotype = UPIO_MEM,
	94	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	95	}, {
	96	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
f568dd7f	97	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
52c543f9 QJ	98	.irq = EXPIO_INT_XUART_INTB,
	99	.uartclk = 14745600,
	100	.regshift = 0,
	101	.iotype = UPIO_MEM,
	102	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	103	},
	104	{},
	105	};
	106
	107	static struct platform_device serial_device = {
	108	.name = "serial8250",
	109	.id = 0,
	110	.dev = {
	111	.platform_data = serial_platform_data,
	112	},
	113	};
	114
	115	static int __init mxc_init_extuart(void)
	116	{
	117	return platform_device_register(&serial_device);
	118	}
	119	#else
	120	static inline int mxc_init_extuart(void)
	121	{
	122	return 0;
	123	}
	124	#endif
	125
0741794c GC	126	#if defined(CONFIG_SERIAL_IMX) \|\| defined(CONFIG_SERIAL_IMX_MODULE)
	127	static struct imxuart_platform_data uart_pdata = {
	128	.flags = IMXUART_HAVE_RTSCTS,
	129	};
	130
9070e7af	131	static unsigned int uart_pins[] = {
945c10b8 VL	132	MX31_PIN_CTS1__CTS1,
	133	MX31_PIN_RTS1__RTS1,
	134	MX31_PIN_TXD1__TXD1,
	135	MX31_PIN_RXD1__RXD1
	136	};
	137
0741794c GC	138	static inline void mxc_init_imx_uart(void)
0741794c GC	139	{
945c10b8	140	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
0741794c GC	141	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	142	}
	143	#else /* !SERIAL_IMX */
	144	static inline void mxc_init_imx_uart(void)
	145	{
	146	}
	147	#endif /* !SERIAL_IMX */
	148
d7568f79 GC	149	static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
	150	{
	151	u32 imr_val;
	152	u32 int_valid;
	153	u32 expio_irq;
	154
	155	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	156	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
	157
	158	expio_irq = MXC_EXP_IO_BASE;
	159	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	160	if ((int_valid & 1) == 0)
	161	continue;
	162
	163	generic_handle_irq(expio_irq);
	164	}
	165	}
	166
	167	/*
	168	* Disable an expio pin's interrupt by setting the bit in the imr.
	169	* @param irq an expio virtual irq number
	170	*/
	171	static void expio_mask_irq(u32 irq)
	172	{
	173	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	174	/* mask the interrupt */
	175	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	176	__raw_readw(PBC_INTMASK_CLEAR_REG);
	177	}
	178
	179	/*
	180	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
	181	* @param irq an expanded io virtual irq number
	182	*/
	183	static void expio_ack_irq(u32 irq)
	184	{
	185	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	186	/* clear the interrupt status */
	187	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
	188	}
	189
	190	/*
	191	* Enable a expio pin's interrupt by clearing the bit in the imr.
	192	* @param irq a expio virtual irq number
	193	*/
	194	static void expio_unmask_irq(u32 irq)
	195	{
	196	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	197	/* unmask the interrupt */
	198	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
	199	}
	200
	201	static struct irq_chip expio_irq_chip = {
bd02acdb	202	.name = "EXPIO(CPLD)",
d7568f79 GC	203	.ack = expio_ack_irq,
	204	.mask = expio_mask_irq,
	205	.unmask = expio_unmask_irq,
	206	};
	207
	208	static void __init mx31ads_init_expio(void)
	209	{
	210	int i;
	211
	212	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
	213
	214	/*
	215	* Configure INT line as GPIO input
	216	*/
4f163eb8	217	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
d7568f79 GC	218
	219	/* disable the interrupt and clear the status */
	220	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	221	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	222	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	223	i++) {
	224	set_irq_chip(i, &expio_irq_chip);
	225	set_irq_handler(i, handle_level_irq);
	226	set_irq_flags(i, IRQF_VALID);
	227	}
	228	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	229	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
	230	}
	231
fe7316bf MB	232	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	233	/* This section defines setup for the Wolfson Microelectronics
	234	* 1133-EV1 PMU/audio board. When other PMU boards are supported the
	235	* regulator definitions may be shared with them, but for now they can
	236	* only be used with this board so would generate warnings about
	237	* unused statics and some of the configuration is specific to this
	238	* module.
	239	*/
	240
	241	/* CPU */
	242	static struct regulator_consumer_supply sw1a_consumers[] = {
	243	{
	244	.supply = "cpu_vcc",
	245	}
	246	};
	247
	248	static struct regulator_init_data sw1a_data = {
	249	.constraints = {
	250	.name = "SW1A",
	251	.min_uV = 1275000,
	252	.max_uV = 1600000,
	253	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	254	REGULATOR_CHANGE_MODE,
	255	.valid_modes_mask = REGULATOR_MODE_NORMAL \|
	256	REGULATOR_MODE_FAST,
	257	.state_mem = {
	258	.uV = 1400000,
	259	.mode = REGULATOR_MODE_NORMAL,
	260	.enabled = 1,
	261	},
	262	.initial_state = PM_SUSPEND_MEM,
	263	.always_on = 1,
	264	.boot_on = 1,
	265	},
	266	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	267	.consumer_supplies = sw1a_consumers,
	268	};
	269
	270	/* System IO - High */
	271	static struct regulator_init_data viohi_data = {
	272	.constraints = {
	273	.name = "VIOHO",
	274	.min_uV = 2800000,
	275	.max_uV = 2800000,
	276	.state_mem = {
	277	.uV = 2800000,
	278	.mode = REGULATOR_MODE_NORMAL,
	279	.enabled = 1,
	280	},
	281	.initial_state = PM_SUSPEND_MEM,
	282	.always_on = 1,
	283	.boot_on = 1,
	284	},
	285	};
	286
	287	/* System IO - Low */
	288	static struct regulator_init_data violo_data = {
	289	.constraints = {
	290	.name = "VIOLO",
	291	.min_uV = 1800000,
	292	.max_uV = 1800000,
	293	.state_mem = {
	294	.uV = 1800000,
	295	.mode = REGULATOR_MODE_NORMAL,
296	.enabled = 1,
297	},
298	.initial_state = PM_SUSPEND_MEM,
299	.always_on = 1,
300	.boot_on = 1,
301	},
302	};
303
304	/* DDR RAM */
305	static struct regulator_init_data sw2a_data = {
306	.constraints = {
307	.name = "SW2A",
308	.min_uV = 1800000,
309	.max_uV = 1800000,
310	.valid_modes_mask = REGULATOR_MODE_NORMAL,
311	.state_mem = {
312	.uV = 1800000,
313	.mode = REGULATOR_MODE_NORMAL,
314	.enabled = 1,
315	},
316	.state_disk = {
317	.mode = REGULATOR_MODE_NORMAL,
318	.enabled = 0,
319	},
320	.always_on = 1,
321	.boot_on = 1,
322	.initial_state = PM_SUSPEND_MEM,
323	},
324	};
325
326	static struct regulator_init_data ldo1_data = {
327	.constraints = {
328	.name = "VCAM/VMMC1/VMMC2",
329	.min_uV = 2800000,
330	.max_uV = 2800000,
331	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	332	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	333	.apply_uV = 1,
	334	},
	335	};
	336
	337	static struct regulator_consumer_supply ldo2_consumers[] = {
edc34a90 MB	338	{ .supply = "AVDD", .dev_name = "1-001a" },
edc34a90 MB	339	{ .supply = "HPVDD", .dev_name = "1-001a" },
fe7316bf MB	340	};
	341
	342	/* CODEC and SIM */
	343	static struct regulator_init_data ldo2_data = {
	344	.constraints = {
	345	.name = "VESIM/VSIM/AVDD",
	346	.min_uV = 3300000,
	347	.max_uV = 3300000,
	348	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	349	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	350	.apply_uV = 1,
	351	},
	352	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	353	.consumer_supplies = ldo2_consumers,
	354	};
	355
	356	/* General */
	357	static struct regulator_init_data vdig_data = {
	358	.constraints = {
	359	.name = "VDIG",
	360	.min_uV = 1500000,
	361	.max_uV = 1500000,
	362	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	363	.apply_uV = 1,
	364	.always_on = 1,
	365	.boot_on = 1,
	366	},
	367	};
	368
	369	/* Tranceivers */
	370	static struct regulator_init_data ldo4_data = {
	371	.constraints = {
	372	.name = "VRF1/CVDD_2.775",
	373	.min_uV = 2500000,
	374	.max_uV = 2500000,
	375	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	376	.apply_uV = 1,
	377	.always_on = 1,
	378	.boot_on = 1,
	379	},
	380	};
	381
	382	static struct wm8350_led_platform_data wm8350_led_data = {
	383	.name = "wm8350:white",
	384	.default_trigger = "heartbeat",
	385	.max_uA = 27899,
	386	};
	387
	388	static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	389	.vmid_discharge_msecs = 1000,
	390	.drain_msecs = 30,
	391	.cap_discharge_msecs = 700,
	392	.vmid_charge_msecs = 700,
	393	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	394	.dis_out4 = WM8350_DISCHARGE_SLOW,
	395	.dis_out3 = WM8350_DISCHARGE_SLOW,
	396	.dis_out2 = WM8350_DISCHARGE_SLOW,
	397	.dis_out1 = WM8350_DISCHARGE_SLOW,
	398	.vroi_out4 = WM8350_TIE_OFF_500R,
	399	.vroi_out3 = WM8350_TIE_OFF_500R,
	400	.vroi_out2 = WM8350_TIE_OFF_500R,
	401	.vroi_out1 = WM8350_TIE_OFF_500R,
	402	.vroi_enable = 0,
	403	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	404	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	405	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
	406	};
	407
	408	static int mx31_wm8350_init(struct wm8350 *wm8350)
	409	{
fe7316bf MB	410	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
	411	WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
	412	WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
	413	WM8350_GPIO_DEBOUNCE_ON);
	414
	415	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
	416	WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
	417	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	418	WM8350_GPIO_DEBOUNCE_ON);
	419
	420	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
	421	WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
	422	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	423	WM8350_GPIO_DEBOUNCE_OFF);
	424
	425	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
	426	WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
	427	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	428	WM8350_GPIO_DEBOUNCE_OFF);
	429
	430	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
	431	WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
	432	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	433	WM8350_GPIO_DEBOUNCE_OFF);
	434
	435	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
	436	WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	437	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	438	WM8350_GPIO_DEBOUNCE_OFF);
	439
	440	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
	441	WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	442	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	443	WM8350_GPIO_DEBOUNCE_OFF);
	444
fe7316bf MB	445	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	446	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	447	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	448	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	449	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	450	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	451	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	452	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
	453
	454	/* LEDs */
	455	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
	456	WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	457	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
	458	WM8350_ISINK_FLASH_DISABLE,
	459	WM8350_ISINK_FLASH_TRIG_BIT,
	460	WM8350_ISINK_FLASH_DUR_32MS,
	461	WM8350_ISINK_FLASH_ON_INSTANT,
	462	WM8350_ISINK_FLASH_OFF_INSTANT,
	463	WM8350_ISINK_FLASH_MODE_EN);
	464	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
	465	WM8350_ISINK_MODE_BOOST,
	466	WM8350_ISINK_ILIM_NORMAL,
	467	WM8350_DC5_RMP_20V,
	468	WM8350_DC5_FBSRC_ISINKA);
	469	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
	470	&wm8350_led_data);
	471
	472	wm8350->codec.platform_data = &imx32ads_wm8350_setup;
	473
0ac402fd MB	474	regulator_has_full_constraints();
0ac402fd MB	475
fe7316bf MB	476	return 0;
	477	}
	478
	479	static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	480	.init = mx31_wm8350_init,
3d661ac1	481	.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
fe7316bf MB	482	};
	483	#endif
	484
	485	#if defined(CONFIG_I2C_IMX) \|\| defined(CONFIG_I2C_IMX_MODULE)
	486	static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
	487	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	488	{
	489	I2C_BOARD_INFO("wm8350", 0x1a),
	490	.platform_data = &mx31_wm8350_pdata,
	491	.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	492	},
	493	#endif
	494	};
	495
	496	static void mxc_init_i2c(void)
	497	{
	498	i2c_register_board_info(1, mx31ads_i2c1_devices,
	499	ARRAY_SIZE(mx31ads_i2c1_devices));
	500
	501	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	502	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
	503
4a9b8b0b	504	imx31_add_imx_i2c1(NULL);
fe7316bf MB	505	}
	506	#else
	507	static void mxc_init_i2c(void)
	508	{
	509	}
	510	#endif
	511
cd6eb980 MB	512	static unsigned int ssi_pins[] = {
	513	MX31_PIN_SFS5__SFS5,
	514	MX31_PIN_SCK5__SCK5,
	515	MX31_PIN_SRXD5__SRXD5,
	516	MX31_PIN_STXD5__STXD5,
	517	};
	518
	519	static void mxc_init_audio(void)
	520	{
	521	mxc_register_device(&imx_ssi_device0, NULL);
	522	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
	523	}
	524
52c543f9 QJ	525	/*!
	526	* This structure defines static mappings for the i.MX31ADS board.
	527	*/
	528	static struct map_desc mx31ads_io_desc[] __initdata = {
	529	{
f568dd7f UKK	530	.virtual = MX31_CS4_BASE_ADDR_VIRT,
	531	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
	532	.length = MX31_CS4_SIZE / 2,
52c543f9 QJ	533	.type = MT_DEVICE
	534	},
	535	};
	536
	537	/*!
	538	* Set up static virtual mappings.
	539	*/
8b785b9d	540	static void __init mx31ads_map_io(void)
52c543f9	541	{
cd4a05f9	542	mx31_map_io();
52c543f9 QJ	543	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
	544	}
	545
8b785b9d	546	static void __init mx31ads_init_irq(void)
d7568f79	547	{
c5aa0ad0	548	mx31_init_irq();
d7568f79 GC	549	mx31ads_init_expio();
	550	}
	551
52c543f9 QJ	552	/*!
	553	* Board specific initialization.
	554	*/
	555	static void __init mxc_board_init(void)
	556	{
	557	mxc_init_extuart();
0741794c	558	mxc_init_imx_uart();
fe7316bf	559	mxc_init_i2c();
cd6eb980	560	mxc_init_audio();
52c543f9 QJ	561	}
52c543f9 QJ	562
d0f349fb JB	563	static void __init mx31ads_timer_init(void)
d0f349fb JB	564	{
30c730f8	565	mx31_clocks_init(26000000);
d0f349fb JB	566	}
d0f349fb JB	567
8b785b9d	568	static struct sys_timer mx31ads_timer = {
d0f349fb JB	569	.init = mx31ads_timer_init,
	570	};
	571
52c543f9 QJ	572	/*
	573	* The following uses standard kernel macros defined in arch.h in order to
	574	* initialize __mach_desc_MX31ADS data structure.
	575	*/
	576	MACHINE_START(MX31ADS, "Freescale MX31ADS")
	577	/* Maintainer: Freescale Semiconductor, Inc. */
f568dd7f	578	.phys_io = MX31_AIPS1_BASE_ADDR,
321ed164	579	.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237	580	.boot_params = MX3x_PHYS_OFFSET + 0x100,
52c543f9	581	.map_io = mx31ads_map_io,
d7568f79	582	.init_irq = mx31ads_init_irq,
52c543f9	583	.init_machine = mxc_board_init,
d0f349fb	584	.timer = &mx31ads_timer,
52c543f9	585	MACHINE_END