[deliverable/linux.git] / arch / arm / mach-mx3 / mach-mx31ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31ads.h>
#include <mach/iomux-mx3.h>

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif

#include "devices-imx31.h"
#include "devices.h"

/* PBC Board interrupt status register */
#define PBC_INTSTATUS           0x000016

/* PBC Board interrupt current status register */
#define PBC_INTCURR_STATUS      0x000018

/* PBC Interrupt mask register set address */
#define PBC_INTMASK_SET         0x00001A

/* PBC Interrupt mask register clear address */
#define PBC_INTMASK_CLEAR       0x00001C

/* External UART A */
#define PBC_SC16C652_UARTA      0x010000

/* External UART B */
#define PBC_SC16C652_UARTB      0x010010

#define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)

#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)

#define EXPIO_INT_XUART_INTA	(MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_XUART_INTB	(MXC_EXP_IO_BASE + 11)

#define MXC_MAX_EXP_IO_LINES	16
/*
 * This file contains the board-specific initialization routines.
 */

/*
 * The serial port definition structure.
 */
static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
		.irq      = EXPIO_INT_XUART_INTA,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	}, {
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
		.irq      = EXPIO_INT_XUART_INTB,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	},
	{},
};

static struct platform_device serial_device = {
	.name	= "serial8250",
	.id	= 0,
	.dev	= {
		.platform_data = serial_platform_data,
	},
};

static int __init mxc_init_extuart(void)
{
	return platform_device_register(&serial_device);
}

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static unsigned int uart_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1
};

static inline void mxc_init_imx_uart(void)
{
	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
	imx31_add_imx_uart0(&uart_pdata);
}

static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 imr_val;
	u32 int_valid;
	u32 expio_irq;

	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;

	expio_irq = MXC_EXP_IO_BASE;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;

		generic_handle_irq(expio_irq);
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param irq           an expio virtual irq number
 */
static void expio_mask_irq(struct irq_data *d)
{
	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
	/* mask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	__raw_readw(PBC_INTMASK_CLEAR_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param irq           an expanded io virtual irq number
 */
static void expio_ack_irq(struct irq_data *d)
{
	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
	/* clear the interrupt status */
	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param irq           a expio virtual irq number
 */
static void expio_unmask_irq(struct irq_data *d)
{
	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
	/* unmask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}

static struct irq_chip expio_irq_chip = {
	.name = "EXPIO(CPLD)",
	.irq_ack = expio_ack_irq,
	.irq_mask = expio_mask_irq,
	.irq_unmask = expio_unmask_irq,
};

static void __init mx31ads_init_expio(void)
{
	int i;

	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");

	/*
	 * Configure INT line as GPIO input
	 */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");

	/* disable the interrupt and clear the status */
	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
}

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
/* This section defines setup for the Wolfson Microelectronics
 * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 * regulator definitions may be shared with them, but for now they can
 * only be used with this board so would generate warnings about
 * unused statics and some of the configuration is specific to this
 * module.
 */

/* CPU */
static struct regulator_consumer_supply sw1a_consumers[] = {
	{
		.supply = "cpu_vcc",
	}
};

static struct regulator_init_data sw1a_data = {
	.constraints = {
		.name = "SW1A",
		.min_uV = 1275000,
		.max_uV = 1600000,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
				  REGULATOR_CHANGE_MODE,
		.valid_modes_mask = REGULATOR_MODE_NORMAL |
				    REGULATOR_MODE_FAST,
		.state_mem = {
			 .uV = 1400000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	.consumer_supplies = sw1a_consumers,
};

/* System IO - High */
static struct regulator_init_data viohi_data = {
	.constraints = {
		.name = "VIOHO",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.state_mem = {
			 .uV = 2800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* System IO - Low */
static struct regulator_init_data violo_data = {
	.constraints = {
		.name = "VIOLO",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* DDR RAM */
static struct regulator_init_data sw2a_data = {
	.constraints = {
		.name = "SW2A",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.state_disk = {
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 0,
		 },
		.always_on = 1,
		.boot_on = 1,
		.initial_state = PM_SUSPEND_MEM,
	},
};

static struct regulator_init_data ldo1_data = {
	.constraints = {
		.name = "VCAM/VMMC1/VMMC2",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
};

static struct regulator_consumer_supply ldo2_consumers[] = {
	{ .supply = "AVDD", .dev_name = "1-001a" },
	{ .supply = "HPVDD", .dev_name = "1-001a" },
};

/* CODEC and SIM */
static struct regulator_init_data ldo2_data = {
	.constraints = {
		.name = "VESIM/VSIM/AVDD",
		.min_uV = 3300000,
		.max_uV = 3300000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	.consumer_supplies = ldo2_consumers,
};

/* General */
static struct regulator_init_data vdig_data = {
	.constraints = {
		.name = "VDIG",
		.min_uV = 1500000,
		.max_uV = 1500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* Tranceivers */
static struct regulator_init_data ldo4_data = {
	.constraints = {
		.name = "VRF1/CVDD_2.775",
		.min_uV = 2500000,
		.max_uV = 2500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

static struct wm8350_led_platform_data wm8350_led_data = {
	.name            = "wm8350:white",
	.default_trigger = "heartbeat",
	.max_uA          = 27899,
};

static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	.vmid_discharge_msecs = 1000,
	.drain_msecs = 30,
	.cap_discharge_msecs = 700,
	.vmid_charge_msecs = 700,
	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	.dis_out4 = WM8350_DISCHARGE_SLOW,
	.dis_out3 = WM8350_DISCHARGE_SLOW,
	.dis_out2 = WM8350_DISCHARGE_SLOW,
	.dis_out1 = WM8350_DISCHARGE_SLOW,
	.vroi_out4 = WM8350_TIE_OFF_500R,
	.vroi_out3 = WM8350_TIE_OFF_500R,
	.vroi_out2 = WM8350_TIE_OFF_500R,
	.vroi_out1 = WM8350_TIE_OFF_500R,
	.vroi_enable = 0,
	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
};

static int mx31_wm8350_init(struct wm8350 *wm8350)
{
	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);

	/* LEDs */
	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
			     WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
			       WM8350_ISINK_FLASH_DISABLE,
			       WM8350_ISINK_FLASH_TRIG_BIT,
			       WM8350_ISINK_FLASH_DUR_32MS,
			       WM8350_ISINK_FLASH_ON_INSTANT,
			       WM8350_ISINK_FLASH_OFF_INSTANT,
			       WM8350_ISINK_FLASH_MODE_EN);
	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
			       WM8350_ISINK_MODE_BOOST,
			       WM8350_ISINK_ILIM_NORMAL,
			       WM8350_DC5_RMP_20V,
			       WM8350_DC5_FBSRC_ISINKA);
	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
			    &wm8350_led_data);

	wm8350->codec.platform_data = &imx32ads_wm8350_setup;

	regulator_has_full_constraints();

	return 0;
}

static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	.init = mx31_wm8350_init,
	.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
};
#endif

static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	{
		I2C_BOARD_INFO("wm8350", 0x1a),
		.platform_data = &mx31_wm8350_pdata,
		.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	},
#endif
};

static void mxc_init_i2c(void)
{
	i2c_register_board_info(1, mx31ads_i2c1_devices,
				ARRAY_SIZE(mx31ads_i2c1_devices));

	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));

	imx31_add_imx_i2c1(NULL);
}

static unsigned int ssi_pins[] = {
	MX31_PIN_SFS5__SFS5,
	MX31_PIN_SCK5__SCK5,
	MX31_PIN_SRXD5__SRXD5,
	MX31_PIN_STXD5__STXD5,
};

static void mxc_init_audio(void)
{
	imx31_add_imx_ssi(0, NULL);
	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
}

/*!
 * This structure defines static mappings for the i.MX31ADS board.
 */
static struct map_desc mx31ads_io_desc[] __initdata = {
	{
		.virtual	= MX31_CS4_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length		= MX31_CS4_SIZE / 2,
		.type		= MT_DEVICE
	},
};

/*!
 * Set up static virtual mappings.
 */
static void __init mx31ads_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
}

static void __init mx31ads_init_irq(void)
{
	mx31_init_irq();
	mx31ads_init_expio();
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_init_extuart();
	mxc_init_imx_uart();
	mxc_init_i2c();
	mxc_init_audio();
}

static void __init mx31ads_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31ads_timer = {
	.init	= mx31ads_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31ADS data structure.
 */
MACHINE_START(MX31ADS, "Freescale MX31ADS")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.boot_params = MX3x_PHYS_OFFSET + 0x100,
	.map_io = mx31ads_map_io,
	.init_early = imx31_init_early,
	.init_irq = mx31ads_init_irq,
	.timer = &mx31ads_timer,
	.init_machine = mxc_board_init,
MACHINE_END
Commit	Line	Data
52c543f9 QJ	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
52c543f9 QJ	15	*/
	16
	17	#include <linux/types.h>
	18	#include <linux/init.h>
	19	#include <linux/clk.h>
	20	#include <linux/serial_8250.h>
fe7316bf MB	21	#include <linux/gpio.h>
fe7316bf MB	22	#include <linux/i2c.h>
d7568f79	23	#include <linux/irq.h>
52c543f9	24
52c543f9 QJ	25	#include <asm/mach-types.h>
52c543f9 QJ	26	#include <asm/mach/arch.h>
d0f349fb	27	#include <asm/mach/time.h>
52c543f9 QJ	28	#include <asm/memory.h>
52c543f9 QJ	29	#include <asm/mach/map.h>
a09e64fb	30	#include <mach/common.h>
d24d96e0	31	#include <mach/board-mx31ads.h>
0741794c	32	#include <mach/iomux-mx3.h>
52c543f9	33
fe7316bf MB	34	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	35	#include <linux/mfd/wm8350/audio.h>
	36	#include <linux/mfd/wm8350/core.h>
	37	#include <linux/mfd/wm8350/pmic.h>
	38	#endif
	39
4a9b8b0b	40	#include "devices-imx31.h"
2eca047b SH	41	#include "devices.h"
2eca047b SH	42
ccfa7c26 UKK	43	/* PBC Board interrupt status register */
	44	#define PBC_INTSTATUS 0x000016
	45
	46	/* PBC Board interrupt current status register */
	47	#define PBC_INTCURR_STATUS 0x000018
	48
	49	/* PBC Interrupt mask register set address */
	50	#define PBC_INTMASK_SET 0x00001A
	51
	52	/* PBC Interrupt mask register clear address */
	53	#define PBC_INTMASK_CLEAR 0x00001C
	54
	55	/* External UART A */
	56	#define PBC_SC16C652_UARTA 0x010000
	57
	58	/* External UART B */
	59	#define PBC_SC16C652_UARTB 0x010010
	60
	61	#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
	62	#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
	63	#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
	64	#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
	65
ccfa7c26 UKK	66	#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
	67
	68	#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
	69	#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
	70
	71	#define MXC_MAX_EXP_IO_LINES 16
	72	/*
	73	* This file contains the board-specific initialization routines.
52c543f9 QJ	74	*/
52c543f9 QJ	75
9f43e44b	76	/*
52c543f9 QJ	77	* The serial port definition structure.
	78	*/
	79	static struct plat_serial8250_port serial_platform_data[] = {
	80	{
	81	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
f568dd7f	82	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
52c543f9 QJ	83	.irq = EXPIO_INT_XUART_INTA,
	84	.uartclk = 14745600,
	85	.regshift = 0,
	86	.iotype = UPIO_MEM,
	87	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	88	}, {
	89	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
f568dd7f	90	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
52c543f9 QJ	91	.irq = EXPIO_INT_XUART_INTB,
	92	.uartclk = 14745600,
	93	.regshift = 0,
	94	.iotype = UPIO_MEM,
	95	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	96	},
	97	{},
	98	};
	99
	100	static struct platform_device serial_device = {
	101	.name = "serial8250",
	102	.id = 0,
	103	.dev = {
	104	.platform_data = serial_platform_data,
	105	},
	106	};
	107
	108	static int __init mxc_init_extuart(void)
	109	{
	110	return platform_device_register(&serial_device);
	111	}
52c543f9	112
16cf5c41	113	static const struct imxuart_platform_data uart_pdata __initconst = {
0741794c GC	114	.flags = IMXUART_HAVE_RTSCTS,
	115	};
	116
9070e7af	117	static unsigned int uart_pins[] = {
945c10b8 VL	118	MX31_PIN_CTS1__CTS1,
	119	MX31_PIN_RTS1__RTS1,
	120	MX31_PIN_TXD1__TXD1,
	121	MX31_PIN_RXD1__RXD1
	122	};
	123
0741794c GC	124	static inline void mxc_init_imx_uart(void)
0741794c GC	125	{
945c10b8	126	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
16cf5c41	127	imx31_add_imx_uart0(&uart_pdata);
0741794c	128	}
0741794c	129
d7568f79 GC	130	static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
	131	{
	132	u32 imr_val;
	133	u32 int_valid;
	134	u32 expio_irq;
	135
	136	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	137	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
	138
	139	expio_irq = MXC_EXP_IO_BASE;
	140	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	141	if ((int_valid & 1) == 0)
	142	continue;
	143
	144	generic_handle_irq(expio_irq);
	145	}
	146	}
	147
	148	/*
	149	* Disable an expio pin's interrupt by setting the bit in the imr.
	150	* @param irq an expio virtual irq number
	151	*/
e981a302	152	static void expio_mask_irq(struct irq_data *d)
d7568f79	153	{
e981a302	154	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
d7568f79 GC	155	/* mask the interrupt */
	156	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	157	__raw_readw(PBC_INTMASK_CLEAR_REG);
	158	}
	159
	160	/*
	161	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
	162	* @param irq an expanded io virtual irq number
	163	*/
e981a302	164	static void expio_ack_irq(struct irq_data *d)
d7568f79	165	{
e981a302	166	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
d7568f79 GC	167	/* clear the interrupt status */
	168	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
	169	}
	170
	171	/*
	172	* Enable a expio pin's interrupt by clearing the bit in the imr.
	173	* @param irq a expio virtual irq number
	174	*/
e981a302	175	static void expio_unmask_irq(struct irq_data *d)
d7568f79	176	{
e981a302	177	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
d7568f79 GC	178	/* unmask the interrupt */
	179	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
	180	}
	181
	182	static struct irq_chip expio_irq_chip = {
bd02acdb	183	.name = "EXPIO(CPLD)",
e981a302 LB	184	.irq_ack = expio_ack_irq,
	185	.irq_mask = expio_mask_irq,
	186	.irq_unmask = expio_unmask_irq,
d7568f79 GC	187	};
	188
	189	static void __init mx31ads_init_expio(void)
	190	{
	191	int i;
	192
	193	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
	194
	195	/*
	196	* Configure INT line as GPIO input
	197	*/
4f163eb8	198	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
d7568f79 GC	199
	200	/* disable the interrupt and clear the status */
	201	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	202	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	203	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	204	i++) {
	205	set_irq_chip(i, &expio_irq_chip);
	206	set_irq_handler(i, handle_level_irq);
	207	set_irq_flags(i, IRQF_VALID);
	208	}
	209	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	210	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
	211	}
	212
fe7316bf MB	213	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	214	/* This section defines setup for the Wolfson Microelectronics
	215	* 1133-EV1 PMU/audio board. When other PMU boards are supported the
	216	* regulator definitions may be shared with them, but for now they can
	217	* only be used with this board so would generate warnings about
	218	* unused statics and some of the configuration is specific to this
	219	* module.
	220	*/
	221
	222	/* CPU */
	223	static struct regulator_consumer_supply sw1a_consumers[] = {
	224	{
	225	.supply = "cpu_vcc",
	226	}
	227	};
	228
	229	static struct regulator_init_data sw1a_data = {
	230	.constraints = {
	231	.name = "SW1A",
	232	.min_uV = 1275000,
	233	.max_uV = 1600000,
	234	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	235	REGULATOR_CHANGE_MODE,
	236	.valid_modes_mask = REGULATOR_MODE_NORMAL \|
	237	REGULATOR_MODE_FAST,
	238	.state_mem = {
	239	.uV = 1400000,
	240	.mode = REGULATOR_MODE_NORMAL,
	241	.enabled = 1,
	242	},
	243	.initial_state = PM_SUSPEND_MEM,
	244	.always_on = 1,
	245	.boot_on = 1,
	246	},
	247	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	248	.consumer_supplies = sw1a_consumers,
	249	};
	250
	251	/* System IO - High */
	252	static struct regulator_init_data viohi_data = {
	253	.constraints = {
	254	.name = "VIOHO",
	255	.min_uV = 2800000,
	256	.max_uV = 2800000,
	257	.state_mem = {
	258	.uV = 2800000,
	259	.mode = REGULATOR_MODE_NORMAL,
	260	.enabled = 1,
	261	},
	262	.initial_state = PM_SUSPEND_MEM,
	263	.always_on = 1,
	264	.boot_on = 1,
	265	},
	266	};
	267
	268	/* System IO - Low */
	269	static struct regulator_init_data violo_data = {
	270	.constraints = {
	271	.name = "VIOLO",
	272	.min_uV = 1800000,
	273	.max_uV = 1800000,
	274	.state_mem = {
	275	.uV = 1800000,
	276	.mode = REGULATOR_MODE_NORMAL,
277	.enabled = 1,
278	},
279	.initial_state = PM_SUSPEND_MEM,
280	.always_on = 1,
281	.boot_on = 1,
282	},
283	};
284
285	/* DDR RAM */
286	static struct regulator_init_data sw2a_data = {
287	.constraints = {
288	.name = "SW2A",
289	.min_uV = 1800000,
290	.max_uV = 1800000,
291	.valid_modes_mask = REGULATOR_MODE_NORMAL,
292	.state_mem = {
293	.uV = 1800000,
294	.mode = REGULATOR_MODE_NORMAL,
295	.enabled = 1,
296	},
297	.state_disk = {
298	.mode = REGULATOR_MODE_NORMAL,
299	.enabled = 0,
300	},
301	.always_on = 1,
302	.boot_on = 1,
303	.initial_state = PM_SUSPEND_MEM,
304	},
305	};
306
307	static struct regulator_init_data ldo1_data = {
308	.constraints = {
309	.name = "VCAM/VMMC1/VMMC2",
310	.min_uV = 2800000,
311	.max_uV = 2800000,
312	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	313	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	314	.apply_uV = 1,
	315	},
	316	};
	317
	318	static struct regulator_consumer_supply ldo2_consumers[] = {
edc34a90 MB	319	{ .supply = "AVDD", .dev_name = "1-001a" },
edc34a90 MB	320	{ .supply = "HPVDD", .dev_name = "1-001a" },
fe7316bf MB	321	};
	322
	323	/* CODEC and SIM */
	324	static struct regulator_init_data ldo2_data = {
	325	.constraints = {
	326	.name = "VESIM/VSIM/AVDD",
	327	.min_uV = 3300000,
	328	.max_uV = 3300000,
	329	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	330	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	331	.apply_uV = 1,
	332	},
	333	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	334	.consumer_supplies = ldo2_consumers,
	335	};
	336
	337	/* General */
	338	static struct regulator_init_data vdig_data = {
	339	.constraints = {
	340	.name = "VDIG",
	341	.min_uV = 1500000,
	342	.max_uV = 1500000,
	343	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	344	.apply_uV = 1,
	345	.always_on = 1,
	346	.boot_on = 1,
	347	},
	348	};
	349
	350	/* Tranceivers */
	351	static struct regulator_init_data ldo4_data = {
	352	.constraints = {
	353	.name = "VRF1/CVDD_2.775",
	354	.min_uV = 2500000,
	355	.max_uV = 2500000,
	356	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	357	.apply_uV = 1,
	358	.always_on = 1,
	359	.boot_on = 1,
	360	},
	361	};
	362
	363	static struct wm8350_led_platform_data wm8350_led_data = {
	364	.name = "wm8350:white",
	365	.default_trigger = "heartbeat",
	366	.max_uA = 27899,
	367	};
	368
	369	static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	370	.vmid_discharge_msecs = 1000,
	371	.drain_msecs = 30,
	372	.cap_discharge_msecs = 700,
	373	.vmid_charge_msecs = 700,
	374	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	375	.dis_out4 = WM8350_DISCHARGE_SLOW,
	376	.dis_out3 = WM8350_DISCHARGE_SLOW,
	377	.dis_out2 = WM8350_DISCHARGE_SLOW,
	378	.dis_out1 = WM8350_DISCHARGE_SLOW,
	379	.vroi_out4 = WM8350_TIE_OFF_500R,
	380	.vroi_out3 = WM8350_TIE_OFF_500R,
	381	.vroi_out2 = WM8350_TIE_OFF_500R,
	382	.vroi_out1 = WM8350_TIE_OFF_500R,
	383	.vroi_enable = 0,
	384	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	385	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	386	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
	387	};
	388
	389	static int mx31_wm8350_init(struct wm8350 *wm8350)
	390	{
fe7316bf MB	391	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
	392	WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
	393	WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
	394	WM8350_GPIO_DEBOUNCE_ON);
	395
	396	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
	397	WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
	398	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	399	WM8350_GPIO_DEBOUNCE_ON);
	400
	401	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
	402	WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
	403	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	404	WM8350_GPIO_DEBOUNCE_OFF);
	405
	406	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
	407	WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
	408	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	409	WM8350_GPIO_DEBOUNCE_OFF);
	410
	411	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
	412	WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
	413	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	414	WM8350_GPIO_DEBOUNCE_OFF);
	415
	416	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
	417	WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	418	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	419	WM8350_GPIO_DEBOUNCE_OFF);
	420
	421	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
	422	WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	423	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	424	WM8350_GPIO_DEBOUNCE_OFF);
	425
fe7316bf MB	426	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	427	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	428	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	429	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	430	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	431	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	432	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	433	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
	434
	435	/* LEDs */
	436	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
	437	WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	438	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
	439	WM8350_ISINK_FLASH_DISABLE,
	440	WM8350_ISINK_FLASH_TRIG_BIT,
	441	WM8350_ISINK_FLASH_DUR_32MS,
	442	WM8350_ISINK_FLASH_ON_INSTANT,
	443	WM8350_ISINK_FLASH_OFF_INSTANT,
	444	WM8350_ISINK_FLASH_MODE_EN);
	445	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
	446	WM8350_ISINK_MODE_BOOST,
	447	WM8350_ISINK_ILIM_NORMAL,
	448	WM8350_DC5_RMP_20V,
	449	WM8350_DC5_FBSRC_ISINKA);
	450	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
	451	&wm8350_led_data);
	452
	453	wm8350->codec.platform_data = &imx32ads_wm8350_setup;
	454
0ac402fd MB	455	regulator_has_full_constraints();
0ac402fd MB	456
fe7316bf MB	457	return 0;
	458	}
	459
	460	static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	461	.init = mx31_wm8350_init,
3d661ac1	462	.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
fe7316bf MB	463	};
	464	#endif
	465
fe7316bf MB	466	static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
	467	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	468	{
	469	I2C_BOARD_INFO("wm8350", 0x1a),
	470	.platform_data = &mx31_wm8350_pdata,
	471	.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	472	},
	473	#endif
	474	};
	475
	476	static void mxc_init_i2c(void)
	477	{
	478	i2c_register_board_info(1, mx31ads_i2c1_devices,
	479	ARRAY_SIZE(mx31ads_i2c1_devices));
	480
	481	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	482	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
	483
4a9b8b0b	484	imx31_add_imx_i2c1(NULL);
fe7316bf	485	}
fe7316bf	486
cd6eb980 MB	487	static unsigned int ssi_pins[] = {
	488	MX31_PIN_SFS5__SFS5,
	489	MX31_PIN_SCK5__SCK5,
	490	MX31_PIN_SRXD5__SRXD5,
	491	MX31_PIN_STXD5__STXD5,
	492	};
	493
	494	static void mxc_init_audio(void)
	495	{
4697bb92	496	imx31_add_imx_ssi(0, NULL);
cd6eb980 MB	497	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
	498	}
	499
52c543f9 QJ	500	/*!
	501	* This structure defines static mappings for the i.MX31ADS board.
	502	*/
	503	static struct map_desc mx31ads_io_desc[] __initdata = {
	504	{
f568dd7f UKK	505	.virtual = MX31_CS4_BASE_ADDR_VIRT,
	506	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
	507	.length = MX31_CS4_SIZE / 2,
52c543f9 QJ	508	.type = MT_DEVICE
	509	},
	510	};
	511
	512	/*!
	513	* Set up static virtual mappings.
	514	*/
8b785b9d	515	static void __init mx31ads_map_io(void)
52c543f9	516	{
cd4a05f9	517	mx31_map_io();
52c543f9 QJ	518	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
	519	}
	520
8b785b9d	521	static void __init mx31ads_init_irq(void)
d7568f79	522	{
c5aa0ad0	523	mx31_init_irq();
d7568f79 GC	524	mx31ads_init_expio();
	525	}
	526
52c543f9 QJ	527	/*!
	528	* Board specific initialization.
	529	*/
	530	static void __init mxc_board_init(void)
	531	{
	532	mxc_init_extuart();
0741794c	533	mxc_init_imx_uart();
fe7316bf	534	mxc_init_i2c();
cd6eb980	535	mxc_init_audio();
52c543f9 QJ	536	}
52c543f9 QJ	537
d0f349fb JB	538	static void __init mx31ads_timer_init(void)
d0f349fb JB	539	{
30c730f8	540	mx31_clocks_init(26000000);
d0f349fb JB	541	}
d0f349fb JB	542
8b785b9d	543	static struct sys_timer mx31ads_timer = {
d0f349fb JB	544	.init = mx31ads_timer_init,
	545	};
	546
52c543f9 QJ	547	/*
	548	* The following uses standard kernel macros defined in arch.h in order to
	549	* initialize __mach_desc_MX31ADS data structure.
	550	*/
	551	MACHINE_START(MX31ADS, "Freescale MX31ADS")
	552	/* Maintainer: Freescale Semiconductor, Inc. */
97976e22 UKK	553	.boot_params = MX3x_PHYS_OFFSET + 0x100,
	554	.map_io = mx31ads_map_io,
	555	.init_early = imx31_init_early,
	556	.init_irq = mx31ads_init_irq,
	557	.timer = &mx31ads_timer,
	558	.init_machine = mxc_board_init,
52c543f9	559	MACHINE_END