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ARM i.MX ehci: factor out soc specific functions
[deliverable/linux.git] / arch / arm / mach-mx3 / mach-pcm037.c
CommitLineData
ce8ffef0
SH		 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
ce8ffef0
SH		 13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
32c1ad9a 17#include <linux/dma-mapping.h>
ce8ffef0
SH		 18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
3dad21a9 20#include <linux/mtd/plat-ram.h>
ce8ffef0 21#include <linux/memory.h>
ba54b958 22#include <linux/gpio.h>
4353318e 23#include <linux/smsc911x.h>
ba54b958 24#include <linux/interrupt.h>
79206750
SH		 25#include <linux/i2c.h>
26#include <linux/i2c/at24.h>
dddd4a49
SH		 27#include <linux/delay.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
91bf9a25 30#include <linux/can/platform/sja1000.h>
ee14373c
SH		 31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h>
5a0e3ad6 33#include <linux/gfp.h>
ce8ffef0 34
32c1ad9a
GL		 35#include <media/soc_camera.h>
36
ce8ffef0
SH		 37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40#include <asm/mach/map.h>
a09e64fb 41#include <mach/common.h>
32c1ad9a 42#include <mach/hardware.h>
a09e64fb 43#include <mach/iomux-mx3.h>
a8df0ee8 44#include <mach/ipu.h>
32c1ad9a 45#include <mach/mx3_camera.h>
a8df0ee8 46#include <mach/mx3fb.h>
ee14373c 47#include <mach/ulpi.h>
ce8ffef0 48
a2ceeef5 49#include "devices-imx31.h"
5cf09421 50#include "devices.h"
574ec547
GL		 51#include "pcm037.h"
52
53static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
54
55static int __init pcm037_variant_setup(char *str)
56{
57 if (!strcmp("eet", str))
58 pcm037_instance = PCM037_EET;
59 else if (strcmp("pcm970", str))
60 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
61
62 return 1;
63}
64
65/* Supported values: "pcm970" (default) and "eet" */
66__setup("pcm037_variant=", pcm037_variant_setup);
67
68enum pcm037_board_variant pcm037_variant(void)
69{
70 return pcm037_instance;
71}
72
73/* UART1 with RTS/CTS handshake signals */
74static unsigned int pcm037_uart1_handshake_pins[] = {
75 MX31_PIN_CTS1__CTS1,
76 MX31_PIN_RTS1__RTS1,
77 MX31_PIN_TXD1__TXD1,
78 MX31_PIN_RXD1__RXD1,
79};
80
81/* UART1 without RTS/CTS handshake signals */
82static unsigned int pcm037_uart1_pins[] = {
83 MX31_PIN_TXD1__TXD1,
84 MX31_PIN_RXD1__RXD1,
85};
5cf09421 86
01ac7d58
SH		 87static unsigned int pcm037_pins[] = {
88 /* I2C */
89 MX31_PIN_CSPI2_MOSI__SCL,
90 MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a
GL		 91 MX31_PIN_CSPI2_SS2__I2C3_SDA,
92 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58
SH		 93 /* SDHC1 */
94 MX31_PIN_SD1_DATA3__SD1_DATA3,
95 MX31_PIN_SD1_DATA2__SD1_DATA2,
96 MX31_PIN_SD1_DATA1__SD1_DATA1,
97 MX31_PIN_SD1_DATA0__SD1_DATA0,
98 MX31_PIN_SD1_CLK__SD1_CLK,
99 MX31_PIN_SD1_CMD__SD1_CMD,
100 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
101 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
102 /* SPI1 */
103 MX31_PIN_CSPI1_MOSI__MOSI,
104 MX31_PIN_CSPI1_MISO__MISO,
105 MX31_PIN_CSPI1_SCLK__SCLK,
106 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
107 MX31_PIN_CSPI1_SS0__SS0,
108 MX31_PIN_CSPI1_SS1__SS1,
109 MX31_PIN_CSPI1_SS2__SS2,
01ac7d58
SH		 110 /* UART2 */
111 MX31_PIN_TXD2__TXD2,
112 MX31_PIN_RXD2__RXD2,
113 MX31_PIN_CTS2__CTS2,
114 MX31_PIN_RTS2__RTS2,
115 /* UART3 */
116 MX31_PIN_CSPI3_MOSI__RXD3,
117 MX31_PIN_CSPI3_MISO__TXD3,
118 MX31_PIN_CSPI3_SCLK__RTS3,
119 MX31_PIN_CSPI3_SPI_RDY__CTS3,
120 /* LAN9217 irq pin */
121 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
122 /* Onewire */
123 MX31_PIN_BATT_LINE__OWIRE,
124 /* Framebuffer */
125 MX31_PIN_LD0__LD0,
126 MX31_PIN_LD1__LD1,
127 MX31_PIN_LD2__LD2,
128 MX31_PIN_LD3__LD3,
129 MX31_PIN_LD4__LD4,
130 MX31_PIN_LD5__LD5,
131 MX31_PIN_LD6__LD6,
132 MX31_PIN_LD7__LD7,
133 MX31_PIN_LD8__LD8,
134 MX31_PIN_LD9__LD9,
135 MX31_PIN_LD10__LD10,
136 MX31_PIN_LD11__LD11,
137 MX31_PIN_LD12__LD12,
138 MX31_PIN_LD13__LD13,
139 MX31_PIN_LD14__LD14,
140 MX31_PIN_LD15__LD15,
141 MX31_PIN_LD16__LD16,
142 MX31_PIN_LD17__LD17,
143 MX31_PIN_VSYNC3__VSYNC3,
144 MX31_PIN_HSYNC__HSYNC,
145 MX31_PIN_FPSHIFT__FPSHIFT,
146 MX31_PIN_DRDY0__DRDY0,
147 MX31_PIN_D3_REV__D3_REV,
148 MX31_PIN_CONTRAST__CONTRAST,
149 MX31_PIN_D3_SPL__D3_SPL,
150 MX31_PIN_D3_CLS__D3_CLS,
151 MX31_PIN_LCS0__GPI03_23,
32c1ad9a
GL		 152 /* CSI */
153 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
154 MX31_PIN_CSI_D6__CSI_D6,
155 MX31_PIN_CSI_D7__CSI_D7,
156 MX31_PIN_CSI_D8__CSI_D8,
157 MX31_PIN_CSI_D9__CSI_D9,
158 MX31_PIN_CSI_D10__CSI_D10,
159 MX31_PIN_CSI_D11__CSI_D11,
160 MX31_PIN_CSI_D12__CSI_D12,
161 MX31_PIN_CSI_D13__CSI_D13,
162 MX31_PIN_CSI_D14__CSI_D14,
163 MX31_PIN_CSI_D15__CSI_D15,
164 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
165 MX31_PIN_CSI_MCLK__CSI_MCLK,
166 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
167 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
e0fd4db3
LF		 168 /* GPIO */
169 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
ee14373c 170 /* OTG */
eb05bbeb
GL		 171 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
172 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
173 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
174 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
175 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
176 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
177 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
178 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
179 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
180 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
181 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
182 MX31_PIN_USBOTG_STP__USBOTG_STP,
ee14373c
SH		 183 /* USB host 2 */
184 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
185 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
186 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
187 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
193 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
194 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
195 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
eb05bbeb
GL		 196};
197
ee14373c
SH		 198static struct physmap_flash_data pcm037_flash_data = {
199 .width = 2,
200};
eb05bbeb 201
ee14373c
SH		 202static struct resource pcm037_flash_resource = {
203 .start = 0xa0000000,
204 .end = 0xa1ffffff,
205 .flags = IORESOURCE_MEM,
eb05bbeb
GL		 206};
207
ce8ffef0
SH		 208static struct platform_device pcm037_flash = {
209 .name = "physmap-flash",
210 .id = 0,
211 .dev = {
212 .platform_data = &pcm037_flash_data,
213 },
214 .resource = &pcm037_flash_resource,
215 .num_resources = 1,
216};
217
16cf5c41 218static const struct imxuart_platform_data uart_pdata __initconst = {
a9b06233 219 .flags = IMXUART_HAVE_RTSCTS,
ce8ffef0
SH		 220};
221
4353318e 222static struct resource smsc911x_resources[] = {
3f4f54b4 223 {
f568dd7f
UKK		 224 .start = MX31_CS1_BASE_ADDR + 0x300,
225 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958 226 .flags = IORESOURCE_MEM,
3f4f54b4 227 }, {
ba54b958
GL		 228 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
229 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
4353318e 230 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
ba54b958
GL		 231 },
232};
233
4353318e
SG		 234static struct smsc911x_platform_config smsc911x_info = {
235 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
236 SMSC911X_SAVE_MAC_ADDRESS,
237 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
238 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
239 .phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958
GL		 240};
241
242static struct platform_device pcm037_eth = {
4353318e 243 .name = "smsc911x",
ba54b958 244 .id = -1,
4353318e
SG		 245 .num_resources = ARRAY_SIZE(smsc911x_resources),
246 .resource = smsc911x_resources,
ba54b958 247 .dev = {
4353318e 248 .platform_data = &smsc911x_info,
ba54b958
GL		 249 },
250};
251
3dad21a9
SH		 252static struct platdata_mtd_ram pcm038_sram_data = {
253 .bankwidth = 2,
254};
255
256static struct resource pcm038_sram_resource = {
f568dd7f
UKK		 257 .start = MX31_CS4_BASE_ADDR,
258 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9
SH		 259 .flags = IORESOURCE_MEM,
260};
261
262static struct platform_device pcm037_sram_device = {
263 .name = "mtd-ram",
264 .id = 0,
265 .dev = {
266 .platform_data = &pcm038_sram_data,
267 },
268 .num_resources = 1,
269 .resource = &pcm038_sram_resource,
270};
271
a2ceeef5
UKK		 272static const struct mxc_nand_platform_data
273pcm037_nand_board_info __initconst = {
3287abbd
SH		 274 .width = 1,
275 .hw_ecc = 1,
276};
277
4a9b8b0b 278static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
79206750 279 .bitrate = 100000,
79206750
SH		 280};
281
4a9b8b0b 282static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
32c1ad9a
GL		 283 .bitrate = 20000,
284};
285
79206750
SH		 286static struct at24_platform_data board_eeprom = {
287 .byte_len = 4096,
288 .page_size = 32,
289 .flags = AT24_FLAG_ADDR16,
290};
291
32c1ad9a
GL		 292static int pcm037_camera_power(struct device *dev, int on)
293{
294 /* disable or enable the camera in X7 or X8 PCM970 connector */
295 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
296 return 0;
297}
298
9d00278d 299static struct i2c_board_info pcm037_i2c_camera[] = {
32c1ad9a
GL		 300 {
301 I2C_BOARD_INFO("mt9t031", 0x5d),
9d00278d
GL		 302 }, {
303 I2C_BOARD_INFO("mt9v022", 0x48),
32c1ad9a
GL		 304 },
305};
306
9d00278d
GL		 307static struct soc_camera_link iclink_mt9v022 = {
308 .bus_id = 0, /* Must match with the camera ID */
309 .board_info = &pcm037_i2c_camera[1],
310 .i2c_adapter_id = 2,
9d00278d
GL		 311};
312
313static struct soc_camera_link iclink_mt9t031 = {
32c1ad9a
GL		 314 .bus_id = 0, /* Must match with the camera ID */
315 .power = pcm037_camera_power,
9d00278d 316 .board_info = &pcm037_i2c_camera[0],
32c1ad9a 317 .i2c_adapter_id = 2,
32c1ad9a
GL		 318};
319
79206750 320static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a 321 {
79206750
SH		 322 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
323 .platform_data = &board_eeprom,
324 }, {
cf87a6e2 325 I2C_BOARD_INFO("pcf8563", 0x51),
79206750
SH		 326 }
327};
32c1ad9a 328
9d00278d 329static struct platform_device pcm037_mt9t031 = {
32c1ad9a
GL		 330 .name = "soc-camera-pdrv",
331 .id = 0,
332 .dev = {
9d00278d
GL		 333 .platform_data = &iclink_mt9t031,
334 },
335};
336
337static struct platform_device pcm037_mt9v022 = {
338 .name = "soc-camera-pdrv",
339 .id = 1,
340 .dev = {
341 .platform_data = &iclink_mt9v022,
32c1ad9a
GL		 342 },
343};
79206750 344
dddd4a49
SH		 345/* Not connected by default */
346#ifdef PCM970_SDHC_RW_SWITCH
347static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f 348{
dddd4a49
SH		 349 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
350}
351#endif
352
4f163eb8
SH		 353#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
354#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
355
dddd4a49
SH		 356static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
357 void *data)
358{
359 int ret;
dddd4a49 360
4f163eb8
SH		 361 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
362 if (ret)
363 return ret;
364
365 gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49 366
4f163eb8
SH		 367#ifdef PCM970_SDHC_RW_SWITCH
368 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
369 if (ret)
370 goto err_gpio_free;
371 gpio_direction_input(SDHC1_GPIO_WP);
372#endif
dddd4a49
SH		 373
374 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
375 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
376 "sdhc-detect", data);
4f163eb8
SH		 377 if (ret)
378 goto err_gpio_free_2;
379
380 return 0;
381
382err_gpio_free_2:
383#ifdef PCM970_SDHC_RW_SWITCH
384 gpio_free(SDHC1_GPIO_WP);
385err_gpio_free:
386#endif
387 gpio_free(SDHC1_GPIO_DET);
388
dddd4a49 389 return ret;
f2cb641f
SH		 390}
391
392static void pcm970_sdhc1_exit(struct device *dev, void *data)
393{
dddd4a49 394 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
4f163eb8
SH		 395 gpio_free(SDHC1_GPIO_DET);
396 gpio_free(SDHC1_GPIO_WP);
f2cb641f
SH		 397}
398
6a697e3d 399static const struct imxmmc_platform_data sdhc_pdata __initconst = {
dddd4a49
SH		 400#ifdef PCM970_SDHC_RW_SWITCH
401 .get_ro = pcm970_sdhc1_get_ro,
402#endif
f2cb641f
SH		 403 .init = pcm970_sdhc1_init,
404 .exit = pcm970_sdhc1_exit,
405};
406
32c1ad9a
GL		 407struct mx3_camera_pdata camera_pdata = {
408 .dma_dev = &mx3_ipu.dev,
409 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
410 .mclk_10khz = 2000,
411};
412
413static int __init pcm037_camera_alloc_dma(const size_t buf_size)
414{
415 dma_addr_t dma_handle;
416 void *buf;
417 int dma;
418
419 if (buf_size < 2 * 1024 * 1024)
420 return -EINVAL;
421
422 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
423 if (!buf) {
424 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
425 return -ENOMEM;
426 }
427
428 memset(buf, 0, buf_size);
429
430 dma = dma_declare_coherent_memory(&mx3_camera.dev,
431 dma_handle, dma_handle, buf_size,
432 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
433
434 /* The way we call dma_declare_coherent_memory only a malloc can fail */
435 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
436}
437
ce8ffef0
SH		 438static struct platform_device *devices[] __initdata = {
439 &pcm037_flash,
3dad21a9 440 &pcm037_sram_device,
9d00278d
GL		 441 &pcm037_mt9t031,
442 &pcm037_mt9v022,
ce8ffef0
SH		 443};
444
a8df0ee8
GL		 445static struct ipu_platform_data mx3_ipu_data = {
446 .irq_base = MXC_IPU_IRQ_START,
447};
448
449static const struct fb_videomode fb_modedb[] = {
450 {
451 /* 240x320 @ 60 Hz Sharp */
452 .name = "Sharp-LQ035Q7DH06-QVGA",
453 .refresh = 60,
454 .xres = 240,
455 .yres = 320,
456 .pixclock = 185925,
457 .left_margin = 9,
458 .right_margin = 16,
459 .upper_margin = 7,
460 .lower_margin = 9,
461 .hsync_len = 1,
462 .vsync_len = 1,
463 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
464 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
465 .vmode = FB_VMODE_NONINTERLACED,
466 .flag = 0,
467 }, {
468 /* 240x320 @ 60 Hz */
469 .name = "TX090",
470 .refresh = 60,
471 .xres = 240,
472 .yres = 320,
473 .pixclock = 38255,
474 .left_margin = 144,
475 .right_margin = 0,
476 .upper_margin = 7,
477 .lower_margin = 40,
478 .hsync_len = 96,
479 .vsync_len = 1,
480 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
481 .vmode = FB_VMODE_NONINTERLACED,
482 .flag = 0,
574ec547
GL		 483 }, {
484 /* 240x320 @ 60 Hz */
485 .name = "CMEL-OLED",
486 .refresh = 60,
487 .xres = 240,
488 .yres = 320,
489 .pixclock = 185925,
490 .left_margin = 9,
491 .right_margin = 16,
492 .upper_margin = 7,
493 .lower_margin = 9,
494 .hsync_len = 1,
495 .vsync_len = 1,
496 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
497 .vmode = FB_VMODE_NONINTERLACED,
498 .flag = 0,
a8df0ee8
GL		 499 },
500};
501
502static struct mx3fb_platform_data mx3fb_pdata = {
503 .dma_dev = &mx3_ipu.dev,
504 .name = "Sharp-LQ035Q7DH06-QVGA",
505 .mode = fb_modedb,
506 .num_modes = ARRAY_SIZE(fb_modedb),
507};
508
91bf9a25
SH		 509static struct resource pcm970_sja1000_resources[] = {
510 {
f568dd7f
UKK		 511 .start = MX31_CS5_BASE_ADDR,
512 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25
SH		 513 .flags = IORESOURCE_MEM,
514 }, {
515 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
516 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
517 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
518 },
519};
520
521struct sja1000_platform_data pcm970_sja1000_platform_data = {
56e6943b
WG		 522 .osc_freq = 16000000,
523 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
524 .cdr = CDR_CBP,
91bf9a25
SH		 525};
526
527static struct platform_device pcm970_sja1000 = {
528 .name = "sja1000_platform",
529 .dev = {
530 .platform_data = &pcm970_sja1000_platform_data,
531 },
532 .resource = pcm970_sja1000_resources,
533 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
534};
535
c18e8fa5 536#if defined(CONFIG_USB_ULPI)
2d58de28 537static struct mxc_usbh_platform_data otg_pdata __initdata = {
ee14373c
SH		 538 .portsc = MXC_EHCI_MODE_ULPI,
539 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
540};
541
2d58de28 542static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
ee14373c
SH		 543 .portsc = MXC_EHCI_MODE_ULPI,
544 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
545};
c18e8fa5 546#endif
ee14373c 547
9e1dde33 548static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
ee14373c
SH		 549 .operating_mode = FSL_USB2_DR_DEVICE,
550 .phy_mode = FSL_USB2_PHY_ULPI,
551};
552
553static int otg_mode_host;
554
555static int __init pcm037_otg_mode(char *options)
556{
557 if (!strcmp(options, "host"))
558 otg_mode_host = 1;
559 else if (!strcmp(options, "device"))
560 otg_mode_host = 0;
561 else
562 pr_info("otg_mode neither \"host\" nor \"device\". "
563 "Defaulting to device\n");
564 return 0;
565}
566__setup("otg_mode=", pcm037_otg_mode);
567
ce8ffef0
SH		 568/*
569 * Board specific initialization.
570 */
571static void __init mxc_board_init(void)
572{
4f163eb8 573 int ret;
ee14373c
SH		 574
575 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
4f163eb8 576
01ac7d58
SH		 577 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
578 "pcm037");
579
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SH		 580#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
581 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
582
583 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
584 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
585 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
586 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
587 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
588 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
589 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
590 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
591 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
592 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
593 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
594 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
595
574ec547
GL		 596 if (pcm037_variant() == PCM037_EET)
597 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
598 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
599 else
600 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
601 ARRAY_SIZE(pcm037_uart1_handshake_pins),
602 "pcm037_uart1");
603
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SH		 604 platform_add_devices(devices, ARRAY_SIZE(devices));
605
742269e2 606 imx31_add_imx2_wdt(NULL);
16cf5c41
UKK		 607 imx31_add_imx_uart0(&uart_pdata);
608 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
609 imx31_add_imx_uart1(&uart_pdata);
610 imx31_add_imx_uart2(&uart_pdata);
d517cab1 611
ae71a562 612 imx31_add_mxc_w1(NULL);
ba54b958 613
f8e5143b 614 /* LAN9217 IRQ pin */
4f163eb8
SH		 615 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
616 if (ret)
617 pr_warning("could not get LAN irq gpio\n");
618 else {
619 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
620 platform_device_register(&pcm037_eth);
621 }
622
3287abbd 623
32c1ad9a 624 /* I2C adapters and devices */
79206750
SH		 625 i2c_register_board_info(1, pcm037_i2c_devices,
626 ARRAY_SIZE(pcm037_i2c_devices));
627
4a9b8b0b
UKK		 628 imx31_add_imx_i2c1(&pcm037_i2c1_data);
629 imx31_add_imx_i2c2(&pcm037_i2c2_data);
32c1ad9a 630
a2ceeef5 631 imx31_add_mxc_nand(&pcm037_nand_board_info);
6a697e3d 632 imx31_add_mxc_mmc(0, &sdhc_pdata);
a8df0ee8
GL		 633 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
634 mxc_register_device(&mx3_fb, &mx3fb_pdata);
32c1ad9a
GL		 635
636 /* CSI */
637 /* Camera power: default - off */
638 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
639 if (!ret)
640 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
641 else
9d00278d 642 iclink_mt9t031.power = NULL;
32c1ad9a
GL		 643
644 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
645 mxc_register_device(&mx3_camera, &camera_pdata);
91bf9a25
SH		 646
647 platform_device_register(&pcm970_sja1000);
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SH		 648
649#if defined(CONFIG_USB_ULPI)
650 if (otg_mode_host) {
651 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 652 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
ee14373c 653
2d58de28 654 imx31_add_mxc_ehci_otg(&otg_pdata);
ee14373c
SH		 655 }
656
657 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 658 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
ee14373c 659
2d58de28 660 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
ee14373c
SH		 661#endif
662 if (!otg_mode_host)
9e1dde33 663 imx31_add_fsl_usb2_udc(&otg_device_pdata);
ee14373c 664
ce8ffef0
SH		 665}
666
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SH		 667static void __init pcm037_timer_init(void)
668{
30c730f8 669 mx31_clocks_init(26000000);
ce8ffef0
SH		 670}
671
672struct sys_timer pcm037_timer = {
673 .init = pcm037_timer_init,
674};
675
676MACHINE_START(PCM037, "Phytec Phycore pcm037")
677 /* Maintainer: Pengutronix */
97976e22
UKK		 678 .boot_params = MX3x_PHYS_OFFSET + 0x100,
679 .map_io = mx31_map_io,
680 .init_early = imx31_init_early,
681 .init_irq = mx31_init_irq,
682 .timer = &pcm037_timer,
683 .init_machine = mxc_board_init,
ce8ffef0 684MACHINE_END
Linux kernel - Deliverables
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