[deliverable/linux.git] / arch / arm / mach-mx3 / mach-pcm043.c

/*
 *  Copyright (C) 2009 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>

#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/smc911x.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/iomux-mx35.h>
#include <mach/ipu.h>
#include <mach/mx3fb.h>
#include <mach/ulpi.h>
#include <mach/audmux.h>

#include "devices-imx35.h"
#include "devices.h"

static const struct fb_videomode fb_modedb[] = {
	{
		/* 240x320 @ 60 Hz */
		.name		= "Sharp-LQ035Q7",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 185925,
		.left_margin	= 9,
		.right_margin	= 16,
		.upper_margin	= 7,
		.lower_margin	= 9,
		.hsync_len	= 1,
		.vsync_len	= 1,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	}, {
		/* 240x320 @ 60 Hz */
		.name		= "TX090",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 38255,
		.left_margin	= 144,
		.right_margin	= 0,
		.upper_margin	= 7,
		.lower_margin	= 40,
		.hsync_len	= 96,
		.vsync_len	= 1,
		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	},
};

static struct ipu_platform_data mx3_ipu_data = {
	.irq_base = MXC_IPU_IRQ_START,
};

static struct mx3fb_platform_data mx3fb_pdata = {
	.dma_dev	= &mx3_ipu.dev,
	.name		= "Sharp-LQ035Q7",
	.mode		= fb_modedb,
	.num_modes	= ARRAY_SIZE(fb_modedb),
};

static struct physmap_flash_data pcm043_flash_data = {
	.width  = 2,
};

static struct resource pcm043_flash_resource = {
	.start	= 0xa0000000,
	.end	= 0xa1ffffff,
	.flags	= IORESOURCE_MEM,
};

static struct platform_device pcm043_flash = {
	.name	= "physmap-flash",
	.id	= 0,
	.dev	= {
		.platform_data  = &pcm043_flash_data,
	},
	.resource = &pcm043_flash_resource,
	.num_resources = 1,
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
	.bitrate = 50000,
};

static struct at24_platform_data board_eeprom = {
	.byte_len = 4096,
	.page_size = 32,
	.flags = AT24_FLAG_ADDR16,
};

static struct i2c_board_info pcm043_i2c_devices[] = {
       {
		I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
		.platform_data = &board_eeprom,
	}, {
		I2C_BOARD_INFO("pcf8563", 0x51),
	}
};

static struct platform_device *devices[] __initdata = {
	&pcm043_flash,
};

static iomux_v3_cfg_t pcm043_pads[] = {
	/* UART1 */
	MX35_PAD_CTS1__UART1_CTS,
	MX35_PAD_RTS1__UART1_RTS,
	MX35_PAD_TXD1__UART1_TXD_MUX,
	MX35_PAD_RXD1__UART1_RXD_MUX,
	/* UART2 */
	MX35_PAD_CTS2__UART2_CTS,
	MX35_PAD_RTS2__UART2_RTS,
	MX35_PAD_TXD2__UART2_TXD_MUX,
	MX35_PAD_RXD2__UART2_RXD_MUX,
	/* FEC */
	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
	MX35_PAD_FEC_COL__FEC_COL,
	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
	MX35_PAD_FEC_MDC__FEC_MDC,
	MX35_PAD_FEC_MDIO__FEC_MDIO,
	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
	MX35_PAD_FEC_CRS__FEC_CRS,
	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
	/* I2C1 */
	MX35_PAD_I2C1_CLK__I2C1_SCL,
	MX35_PAD_I2C1_DAT__I2C1_SDA,
	/* Display */
	MX35_PAD_LD0__IPU_DISPB_DAT_0,
	MX35_PAD_LD1__IPU_DISPB_DAT_1,
	MX35_PAD_LD2__IPU_DISPB_DAT_2,
	MX35_PAD_LD3__IPU_DISPB_DAT_3,
	MX35_PAD_LD4__IPU_DISPB_DAT_4,
	MX35_PAD_LD5__IPU_DISPB_DAT_5,
	MX35_PAD_LD6__IPU_DISPB_DAT_6,
	MX35_PAD_LD7__IPU_DISPB_DAT_7,
	MX35_PAD_LD8__IPU_DISPB_DAT_8,
	MX35_PAD_LD9__IPU_DISPB_DAT_9,
	MX35_PAD_LD10__IPU_DISPB_DAT_10,
	MX35_PAD_LD11__IPU_DISPB_DAT_11,
	MX35_PAD_LD12__IPU_DISPB_DAT_12,
	MX35_PAD_LD13__IPU_DISPB_DAT_13,
	MX35_PAD_LD14__IPU_DISPB_DAT_14,
	MX35_PAD_LD15__IPU_DISPB_DAT_15,
	MX35_PAD_LD16__IPU_DISPB_DAT_16,
	MX35_PAD_LD17__IPU_DISPB_DAT_17,
	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
	/* gpio */
	MX35_PAD_ATA_CS0__GPIO2_6,
	/* USB host */
	MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
	MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
	/* SSI */
	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
	MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
	MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
	/* CAN2 */
	MX35_PAD_TX5_RX0__CAN2_TXCAN,
	MX35_PAD_TX4_RX1__CAN2_RXCAN,
	/* esdhc */
	MX35_PAD_SD1_CMD__ESDHC1_CMD,
	MX35_PAD_SD1_CLK__ESDHC1_CLK,
	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
	MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
	MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
};

#define AC97_GPIO_TXFS	IMX_GPIO_NR(2, 31)
#define AC97_GPIO_TXD	IMX_GPIO_NR(2, 28)
#define AC97_GPIO_RESET	IMX_GPIO_NR(2, 0)
#define SD1_GPIO_WP	IMX_GPIO_NR(2, 23)
#define SD1_GPIO_CD	IMX_GPIO_NR(2, 24)

static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
{
	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
	int ret;

	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	if (ret) {
		printk("failed to get GPIO_TXFS: %d\n", ret);
		return;
	}

	mxc_iomux_v3_setup_pad(txfs_gpio);

	/* warm reset */
	gpio_direction_output(AC97_GPIO_TXFS, 1);
	udelay(2);
	gpio_set_value(AC97_GPIO_TXFS, 0);

	gpio_free(AC97_GPIO_TXFS);
	mxc_iomux_v3_setup_pad(txfs);
}

static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
{
	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
	iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
	iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
	iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
	int ret;

	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	if (ret)
		goto err1;

	ret = gpio_request(AC97_GPIO_TXD, "SSI");
	if (ret)
		goto err2;

	ret = gpio_request(AC97_GPIO_RESET, "SSI");
	if (ret)
		goto err3;

	mxc_iomux_v3_setup_pad(txfs_gpio);
	mxc_iomux_v3_setup_pad(txd_gpio);
	mxc_iomux_v3_setup_pad(reset_gpio);

	gpio_direction_output(AC97_GPIO_TXFS, 0);
	gpio_direction_output(AC97_GPIO_TXD, 0);

	/* cold reset */
	gpio_direction_output(AC97_GPIO_RESET, 0);
	udelay(10);
	gpio_direction_output(AC97_GPIO_RESET, 1);

	mxc_iomux_v3_setup_pad(txd);
	mxc_iomux_v3_setup_pad(txfs);

	gpio_free(AC97_GPIO_RESET);
err3:
	gpio_free(AC97_GPIO_TXD);
err2:
	gpio_free(AC97_GPIO_TXFS);
err1:
	if (ret)
		printk("%s failed with %d\n", __func__, ret);
	mdelay(1);
}

static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
	.ac97_reset = pcm043_ac97_cold_reset,
	.ac97_warm_reset = pcm043_ac97_warm_reset,
	.flags = IMX_SSI_USE_AC97,
};

static const struct mxc_nand_platform_data
pcm037_nand_board_info __initconst = {
	.width = 1,
	.hw_ecc = 1,
};

static int pcm043_otg_init(struct platform_device *pdev)
{
	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}

static struct mxc_usbh_platform_data otg_pdata __initdata = {
	.init	= pcm043_otg_init,
	.portsc	= MXC_EHCI_MODE_UTMI,
};

static int pcm043_usbh1_init(struct platform_device *pdev)
{
	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
			MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
}

static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
	.init	= pcm043_usbh1_init,
	.portsc	= MXC_EHCI_MODE_SERIAL,
};

static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
	.operating_mode = FSL_USB2_DR_DEVICE,
	.phy_mode       = FSL_USB2_PHY_UTMI,
};

static int otg_mode_host;

static int __init pcm043_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = 1;
	else if (!strcmp(options, "device"))
		otg_mode_host = 0;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 0;
}
__setup("otg_mode=", pcm043_otg_mode);

static struct esdhc_platform_data sd1_pdata = {
	.wp_gpio = SD1_GPIO_WP,
	.cd_gpio = SD1_GPIO_CD,
};

/*
 * Board specific initialization.
 */
static void __init pcm043_init(void)
{
	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));

	mxc_audmux_v2_configure_port(3,
			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
			MXC_AUDMUX_V2_PTCR_TFSEL(0) |
			MXC_AUDMUX_V2_PTCR_TFSDIR,
			MXC_AUDMUX_V2_PDCR_RXDSEL(0));

	mxc_audmux_v2_configure_port(0,
			MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
			MXC_AUDMUX_V2_PTCR_TCSEL(3) |
			MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
			MXC_AUDMUX_V2_PDCR_RXDSEL(3));

	imx35_add_fec(NULL);
	platform_add_devices(devices, ARRAY_SIZE(devices));
	imx35_add_imx2_wdt(NULL);

	imx35_add_imx_uart0(&uart_pdata);
	imx35_add_mxc_nand(&pcm037_nand_board_info);
	imx35_add_imx_ssi(0, &pcm043_ssi_pdata);

	imx35_add_imx_uart1(&uart_pdata);

	i2c_register_board_info(0, pcm043_i2c_devices,
			ARRAY_SIZE(pcm043_i2c_devices));

	imx35_add_imx_i2c0(&pcm043_i2c0_data);

	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
	mxc_register_device(&mx3_fb, &mx3fb_pdata);

	if (otg_mode_host) {
		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
				ULPI_OTG_DRVVBUS_EXT);
		if (otg_pdata.otg)
			imx35_add_mxc_ehci_otg(&otg_pdata);
	}
	imx35_add_mxc_ehci_hs(&usbh1_pdata);

	if (!otg_mode_host)
		imx35_add_fsl_usb2_udc(&otg_device_pdata);

	imx35_add_flexcan1(NULL);
	imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
}

static void __init pcm043_timer_init(void)
{
	mx35_clocks_init();
}

struct sys_timer pcm043_timer = {
	.init	= pcm043_timer_init,
};

MACHINE_START(PCM043, "Phytec Phycore pcm043")
	/* Maintainer: Pengutronix */
	.boot_params = MX3x_PHYS_OFFSET + 0x100,
	.map_io = mx35_map_io,
	.init_early = imx35_init_early,
	.init_irq = mx35_init_irq,
	.timer = &pcm043_timer,
	.init_machine = pcm043_init,
MACHINE_END
Commit	Line	Data
54df5268 SH	1	/*
	2	* Copyright (C) 2009 Sascha Hauer, Pengutronix
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
54df5268 SH	13	*/
	14
	15	#include <linux/types.h>
	16	#include <linux/init.h>
	17
	18	#include <linux/platform_device.h>
	19	#include <linux/mtd/physmap.h>
	20	#include <linux/mtd/plat-ram.h>
	21	#include <linux/memory.h>
	22	#include <linux/gpio.h>
	23	#include <linux/smc911x.h>
	24	#include <linux/interrupt.h>
d2831d1f	25	#include <linux/delay.h>
54df5268 SH	26	#include <linux/i2c.h>
54df5268 SH	27	#include <linux/i2c/at24.h>
cb2dc111 SH	28	#include <linux/usb/otg.h>
cb2dc111 SH	29	#include <linux/usb/ulpi.h>
54df5268 SH	30
	31	#include <asm/mach-types.h>
	32	#include <asm/mach/arch.h>
	33	#include <asm/mach/time.h>
	34	#include <asm/mach/map.h>
	35
	36	#include <mach/hardware.h>
	37	#include <mach/common.h>
54df5268 SH	38	#include <mach/iomux-mx35.h>
	39	#include <mach/ipu.h>
	40	#include <mach/mx3fb.h>
cb2dc111	41	#include <mach/ulpi.h>
d2831d1f	42	#include <mach/audmux.h>
54df5268	43
e2611ba4	44	#include "devices-imx35.h"
54df5268 SH	45	#include "devices.h"
	46
	47	static const struct fb_videomode fb_modedb[] = {
	48	{
	49	/* 240x320 @ 60 Hz */
	50	.name = "Sharp-LQ035Q7",
	51	.refresh = 60,
	52	.xres = 240,
	53	.yres = 320,
	54	.pixclock = 185925,
	55	.left_margin = 9,
	56	.right_margin = 16,
	57	.upper_margin = 7,
	58	.lower_margin = 9,
	59	.hsync_len = 1,
	60	.vsync_len = 1,
	61	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_SHARP_MODE \| FB_SYNC_CLK_INVERT \| FB_SYNC_CLK_IDLE_EN,
	62	.vmode = FB_VMODE_NONINTERLACED,
	63	.flag = 0,
	64	}, {
	65	/* 240x320 @ 60 Hz */
	66	.name = "TX090",
	67	.refresh = 60,
	68	.xres = 240,
	69	.yres = 320,
	70	.pixclock = 38255,
	71	.left_margin = 144,
	72	.right_margin = 0,
	73	.upper_margin = 7,
	74	.lower_margin = 40,
	75	.hsync_len = 96,
	76	.vsync_len = 1,
	77	.sync = FB_SYNC_VERT_HIGH_ACT \| FB_SYNC_OE_ACT_HIGH,
	78	.vmode = FB_VMODE_NONINTERLACED,
	79	.flag = 0,
	80	},
	81	};
	82
	83	static struct ipu_platform_data mx3_ipu_data = {
	84	.irq_base = MXC_IPU_IRQ_START,
	85	};
	86
	87	static struct mx3fb_platform_data mx3fb_pdata = {
	88	.dma_dev = &mx3_ipu.dev,
	89	.name = "Sharp-LQ035Q7",
	90	.mode = fb_modedb,
	91	.num_modes = ARRAY_SIZE(fb_modedb),
	92	};
	93
	94	static struct physmap_flash_data pcm043_flash_data = {
	95	.width = 2,
	96	};
	97
	98	static struct resource pcm043_flash_resource = {
	99	.start = 0xa0000000,
	100	.end = 0xa1ffffff,
	101	.flags = IORESOURCE_MEM,
	102	};
	103
	104	static struct platform_device pcm043_flash = {
	105	.name = "physmap-flash",
	106	.id = 0,
	107	.dev = {
	108	.platform_data = &pcm043_flash_data,
109	},
110	.resource = &pcm043_flash_resource,
111	.num_resources = 1,
112	};
113
6eafde5f	114	static const struct imxuart_platform_data uart_pdata __initconst = {
54df5268 SH	115	.flags = IMXUART_HAVE_RTSCTS,
	116	};
	117
7cdc8fa7	118	static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
54df5268 SH	119	.bitrate = 50000,
	120	};
	121
	122	static struct at24_platform_data board_eeprom = {
	123	.byte_len = 4096,
	124	.page_size = 32,
	125	.flags = AT24_FLAG_ADDR16,
	126	};
	127
	128	static struct i2c_board_info pcm043_i2c_devices[] = {
	129	{
	130	I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
	131	.platform_data = &board_eeprom,
	132	}, {
cf87a6e2	133	I2C_BOARD_INFO("pcf8563", 0x51),
54df5268 SH	134	}
54df5268 SH	135	};
54df5268 SH	136
	137	static struct platform_device *devices[] __initdata = {
	138	&pcm043_flash,
54df5268 SH	139	};
54df5268 SH	140
8f5260c8	141	static iomux_v3_cfg_t pcm043_pads[] = {
54df5268 SH	142	/* UART1 */
	143	MX35_PAD_CTS1__UART1_CTS,
	144	MX35_PAD_RTS1__UART1_RTS,
	145	MX35_PAD_TXD1__UART1_TXD_MUX,
	146	MX35_PAD_RXD1__UART1_RXD_MUX,
	147	/* UART2 */
	148	MX35_PAD_CTS2__UART2_CTS,
	149	MX35_PAD_RTS2__UART2_RTS,
	150	MX35_PAD_TXD2__UART2_TXD_MUX,
	151	MX35_PAD_RXD2__UART2_RXD_MUX,
	152	/* FEC */
	153	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
	154	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
	155	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
	156	MX35_PAD_FEC_COL__FEC_COL,
	157	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
	158	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
	159	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
	160	MX35_PAD_FEC_MDC__FEC_MDC,
	161	MX35_PAD_FEC_MDIO__FEC_MDIO,
	162	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
	163	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
	164	MX35_PAD_FEC_CRS__FEC_CRS,
	165	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
	166	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
	167	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
	168	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
	169	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
	170	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
	171	/* I2C1 */
	172	MX35_PAD_I2C1_CLK__I2C1_SCL,
	173	MX35_PAD_I2C1_DAT__I2C1_SDA,
	174	/* Display */
	175	MX35_PAD_LD0__IPU_DISPB_DAT_0,
	176	MX35_PAD_LD1__IPU_DISPB_DAT_1,
	177	MX35_PAD_LD2__IPU_DISPB_DAT_2,
	178	MX35_PAD_LD3__IPU_DISPB_DAT_3,
	179	MX35_PAD_LD4__IPU_DISPB_DAT_4,
	180	MX35_PAD_LD5__IPU_DISPB_DAT_5,
	181	MX35_PAD_LD6__IPU_DISPB_DAT_6,
	182	MX35_PAD_LD7__IPU_DISPB_DAT_7,
	183	MX35_PAD_LD8__IPU_DISPB_DAT_8,
	184	MX35_PAD_LD9__IPU_DISPB_DAT_9,
	185	MX35_PAD_LD10__IPU_DISPB_DAT_10,
	186	MX35_PAD_LD11__IPU_DISPB_DAT_11,
	187	MX35_PAD_LD12__IPU_DISPB_DAT_12,
	188	MX35_PAD_LD13__IPU_DISPB_DAT_13,
	189	MX35_PAD_LD14__IPU_DISPB_DAT_14,
	190	MX35_PAD_LD15__IPU_DISPB_DAT_15,
	191	MX35_PAD_LD16__IPU_DISPB_DAT_16,
	192	MX35_PAD_LD17__IPU_DISPB_DAT_17,
	193	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
	194	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
	195	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
	196	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
	197	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
	198	MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
	199	MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
8d5c1ed3 LF	200	/* gpio */
8d5c1ed3 LF	201	MX35_PAD_ATA_CS0__GPIO2_6,
cb2dc111 SH	202	/* USB host */
	203	MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
	204	MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
d2831d1f SH	205	/* SSI */
	206	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
	207	MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
	208	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
	209	MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
da92e42b MKB	210	/* CAN2 */
	211	MX35_PAD_TX5_RX0__CAN2_TXCAN,
	212	MX35_PAD_TX4_RX1__CAN2_RXCAN,
9a545943 WS	213	/* esdhc */
	214	MX35_PAD_SD1_CMD__ESDHC1_CMD,
	215	MX35_PAD_SD1_CLK__ESDHC1_CLK,
	216	MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
	217	MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
	218	MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
	219	MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
a10aabd5 WS	220	MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
a10aabd5 WS	221	MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
d2831d1f SH	222	};
d2831d1f SH	223
d4abe933 WS	224	#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
	225	#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
	226	#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
a10aabd5 WS	227	#define SD1_GPIO_WP IMX_GPIO_NR(2, 23)
a10aabd5 WS	228	#define SD1_GPIO_CD IMX_GPIO_NR(2, 24)
d2831d1f SH	229
	230	static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
	231	{
8f5260c8 LW	232	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
8f5260c8 LW	233	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
d2831d1f SH	234	int ret;
	235
	236	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	237	if (ret) {
	238	printk("failed to get GPIO_TXFS: %d\n", ret);
	239	return;
	240	}
	241
96f3e256	242	mxc_iomux_v3_setup_pad(txfs_gpio);
d2831d1f SH	243
	244	/* warm reset */
	245	gpio_direction_output(AC97_GPIO_TXFS, 1);
	246	udelay(2);
	247	gpio_set_value(AC97_GPIO_TXFS, 0);
	248
	249	gpio_free(AC97_GPIO_TXFS);
96f3e256	250	mxc_iomux_v3_setup_pad(txfs);
d2831d1f SH	251	}
	252
	253	static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
	254	{
8f5260c8 LW	255	iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
	256	iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
	257	iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
	258	iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
	259	iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
d2831d1f SH	260	int ret;
	261
	262	ret = gpio_request(AC97_GPIO_TXFS, "SSI");
	263	if (ret)
	264	goto err1;
	265
	266	ret = gpio_request(AC97_GPIO_TXD, "SSI");
	267	if (ret)
	268	goto err2;
	269
	270	ret = gpio_request(AC97_GPIO_RESET, "SSI");
	271	if (ret)
	272	goto err3;
	273
96f3e256 LW	274	mxc_iomux_v3_setup_pad(txfs_gpio);
	275	mxc_iomux_v3_setup_pad(txd_gpio);
	276	mxc_iomux_v3_setup_pad(reset_gpio);
d2831d1f SH	277
	278	gpio_direction_output(AC97_GPIO_TXFS, 0);
	279	gpio_direction_output(AC97_GPIO_TXD, 0);
	280
	281	/* cold reset */
	282	gpio_direction_output(AC97_GPIO_RESET, 0);
	283	udelay(10);
	284	gpio_direction_output(AC97_GPIO_RESET, 1);
	285
96f3e256 LW	286	mxc_iomux_v3_setup_pad(txd);
96f3e256 LW	287	mxc_iomux_v3_setup_pad(txfs);
d2831d1f SH	288
	289	gpio_free(AC97_GPIO_RESET);
	290	err3:
	291	gpio_free(AC97_GPIO_TXD);
	292	err2:
	293	gpio_free(AC97_GPIO_TXFS);
	294	err1:
	295	if (ret)
	296	printk("%s failed with %d\n", __func__, ret);
	297	mdelay(1);
	298	}
	299
4697bb92	300	static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
d2831d1f SH	301	.ac97_reset = pcm043_ac97_cold_reset,
	302	.ac97_warm_reset = pcm043_ac97_warm_reset,
	303	.flags = IMX_SSI_USE_AC97,
54df5268 SH	304	};
54df5268 SH	305
e2611ba4 UKK	306	static const struct mxc_nand_platform_data
e2611ba4 UKK	307	pcm037_nand_board_info __initconst = {
4f43c2ed SH	308	.width = 1,
	309	.hw_ecc = 1,
	310	};
	311
4bd597b6 SH	312	static int pcm043_otg_init(struct platform_device *pdev)
	313	{
	314	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
	315	}
	316
2d58de28	317	static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6	318	.init = pcm043_otg_init,
cb2dc111	319	.portsc = MXC_EHCI_MODE_UTMI,
cb2dc111 SH	320	};
cb2dc111 SH	321
4bd597b6 SH	322	static int pcm043_usbh1_init(struct platform_device *pdev)
	323	{
	324	return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI \|
	325	MXC_EHCI_INTERNAL_PHY \| MXC_EHCI_IPPUE_DOWN);
	326	}
	327
2d58de28	328	static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
4bd597b6	329	.init = pcm043_usbh1_init,
cb2dc111	330	.portsc = MXC_EHCI_MODE_SERIAL,
cb2dc111 SH	331	};
cb2dc111 SH	332
9e1dde33	333	static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
cb2dc111 SH	334	.operating_mode = FSL_USB2_DR_DEVICE,
	335	.phy_mode = FSL_USB2_PHY_UTMI,
	336	};
	337
	338	static int otg_mode_host;
	339
	340	static int __init pcm043_otg_mode(char *options)
	341	{
	342	if (!strcmp(options, "host"))
	343	otg_mode_host = 1;
	344	else if (!strcmp(options, "device"))
	345	otg_mode_host = 0;
	346	else
	347	pr_info("otg_mode neither \"host\" nor \"device\". "
	348	"Defaulting to device\n");
	349	return 0;
	350	}
	351	__setup("otg_mode=", pcm043_otg_mode);
	352
a10aabd5 WS	353	static struct esdhc_platform_data sd1_pdata = {
	354	.wp_gpio = SD1_GPIO_WP,
	355	.cd_gpio = SD1_GPIO_CD,
	356	};
	357
54df5268 SH	358	/*
	359	* Board specific initialization.
	360	*/
e134fb2b	361	static void __init pcm043_init(void)
54df5268 SH	362	{
	363	mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
	364
d2831d1f SH	365	mxc_audmux_v2_configure_port(3,
	366	MXC_AUDMUX_V2_PTCR_SYN \| /* 4wire mode */
	367	MXC_AUDMUX_V2_PTCR_TFSEL(0) \|
	368	MXC_AUDMUX_V2_PTCR_TFSDIR,
	369	MXC_AUDMUX_V2_PDCR_RXDSEL(0));
	370
	371	mxc_audmux_v2_configure_port(0,
	372	MXC_AUDMUX_V2_PTCR_SYN \| /* 4wire mode */
	373	MXC_AUDMUX_V2_PTCR_TCSEL(3) \|
	374	MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
	375	MXC_AUDMUX_V2_PDCR_RXDSEL(3));
	376
6bd96f3c	377	imx35_add_fec(NULL);
54df5268	378	platform_add_devices(devices, ARRAY_SIZE(devices));
742269e2	379	imx35_add_imx2_wdt(NULL);
54df5268	380
6eafde5f	381	imx35_add_imx_uart0(&uart_pdata);
e2611ba4	382	imx35_add_mxc_nand(&pcm037_nand_board_info);
4697bb92	383	imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
54df5268	384
6eafde5f	385	imx35_add_imx_uart1(&uart_pdata);
54df5268	386
54df5268 SH	387	i2c_register_board_info(0, pcm043_i2c_devices,
	388	ARRAY_SIZE(pcm043_i2c_devices));
	389
7cdc8fa7	390	imx35_add_imx_i2c0(&pcm043_i2c0_data);
54df5268 SH	391
	392	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
	393	mxc_register_device(&mx3_fb, &mx3fb_pdata);
cb2dc111	394
cb2dc111	395	if (otg_mode_host) {
48f6b099 SH	396	otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS \|
	397	ULPI_OTG_DRVVBUS_EXT);
	398	if (otg_pdata.otg)
	399	imx35_add_mxc_ehci_otg(&otg_pdata);
cb2dc111	400	}
070ed733 SH	401	imx35_add_mxc_ehci_hs(&usbh1_pdata);
070ed733 SH	402
cb2dc111	403	if (!otg_mode_host)
9e1dde33	404	imx35_add_fsl_usb2_udc(&otg_device_pdata);
cb2dc111	405
da92e42b	406	imx35_add_flexcan1(NULL);
a10aabd5	407	imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
54df5268 SH	408	}
	409
	410	static void __init pcm043_timer_init(void)
	411	{
	412	mx35_clocks_init();
	413	}
	414
	415	struct sys_timer pcm043_timer = {
	416	.init = pcm043_timer_init,
	417	};
	418
	419	MACHINE_START(PCM043, "Phytec Phycore pcm043")
	420	/* Maintainer: Pengutronix */
97976e22 UKK	421	.boot_params = MX3x_PHYS_OFFSET + 0x100,
	422	.map_io = mx35_map_io,
	423	.init_early = imx35_init_early,
	424	.init_irq = mx35_init_irq,
	425	.timer = &pcm043_timer,
e134fb2b	426	.init_machine = pcm043_init,
54df5268	427	MACHINE_END