[deliverable/linux.git] / arch / arm / mach-mx3 / mach-qong.c

/*
 *  Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/memory.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/nand.h>
#include <linux/gpio.h>

#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <mach/board-qong.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include "devices.h"

/* FPGA defines */
#define QONG_FPGA_VERSION(major, minor, rev)	\
	(((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))

#define QONG_FPGA_BASEADDR 		MX31_CS1_BASE_ADDR
#define QONG_FPGA_PERIPH_SIZE 		(1 << 24)

#define QONG_FPGA_CTRL_BASEADDR		QONG_FPGA_BASEADDR
#define QONG_FPGA_CTRL_SIZE 		0x10
/* FPGA control registers */
#define QONG_FPGA_CTRL_VERSION		0x00

#define QONG_DNET_ID		1
#define QONG_DNET_BASEADDR	\
	(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
#define QONG_DNET_SIZE 		0x00001000

#define QONG_FPGA_IRQ		IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)

/*
 * This file contains the board-specific initialization routines.
 */

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static int uart_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1
};

static inline void mxc_init_imx_uart(void)
{
	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
			"uart-0");
	mxc_register_device(&mxc_uart_device0, &uart_pdata);
}

static struct resource dnet_resources[] = {
	{
		.name	= "dnet-memory",
		.start	= QONG_DNET_BASEADDR,
		.end	= QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
		.flags	= IORESOURCE_MEM,
	}, {
		.start	= QONG_FPGA_IRQ,
		.end	= QONG_FPGA_IRQ,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device dnet_device = {
	.name			= "dnet",
	.id			= -1,
	.num_resources		= ARRAY_SIZE(dnet_resources),
	.resource		= dnet_resources,
};

static int __init qong_init_dnet(void)
{
	int ret;

	ret = platform_device_register(&dnet_device);
	return ret;
}

/* MTD NOR flash */

static struct physmap_flash_data qong_flash_data = {
	.width = 2,
};

static struct resource qong_flash_resource = {
	.start = MX31_CS0_BASE_ADDR,
	.end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
	.flags = IORESOURCE_MEM,
};

static struct platform_device qong_nor_mtd_device = {
	.name = "physmap-flash",
	.id = 0,
	.dev = {
		.platform_data = &qong_flash_data,
		},
	.resource = &qong_flash_resource,
	.num_resources = 1,
};

static void qong_init_nor_mtd(void)
{
	(void)platform_device_register(&qong_nor_mtd_device);
}

/*
 * Hardware specific access to control-lines
 */
static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
	struct nand_chip *nand_chip = mtd->priv;

	if (cmd == NAND_CMD_NONE)
		return;

	if (ctrl & NAND_CLE)
		writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
	else
		writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
}

/*
 * Read the Device Ready pin.
 */
static int qong_nand_device_ready(struct mtd_info *mtd)
{
	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
}

static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
{
	if (chip >= 0)
		gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
	else
		gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
}

static struct platform_nand_data qong_nand_data = {
	.chip = {
		.chip_delay		= 20,
		.options		= 0,
	},
	.ctrl = {
		.cmd_ctrl 		= qong_nand_cmd_ctrl,
		.dev_ready		= qong_nand_device_ready,
		.select_chip		= qong_nand_select_chip,
	}
};

static struct resource qong_nand_resource = {
	.start  	= MX31_CS3_BASE_ADDR,
	.end    	= MX31_CS3_BASE_ADDR + SZ_32M - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device qong_nand_device = {
	.name		= "gen_nand",
	.id		= -1,
	.dev		= {
		.platform_data = &qong_nand_data,
	},
	.num_resources	= 1,
	.resource	= &qong_nand_resource,
};

static void __init qong_init_nand_mtd(void)
{
	/* init CS */
	mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
	mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);

	/* enable pin */
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
		gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);

	/* ready/busy pin */
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));

	/* write protect pin */
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));

	platform_device_register(&qong_nand_device);
}

static void __init qong_init_fpga(void)
{
	void __iomem *regs;
	u32 fpga_ver;

	regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
	if (!regs) {
		printk(KERN_ERR "%s: failed to map registers, aborting.\n",
				__func__);
		return;
	}

	fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
	iounmap(regs);
	printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
			(fpga_ver & 0xF000) >> 12,
			(fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
	if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
		printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
				"devices won't be registered!\n");
		return;
	}

	/* register FPGA-based devices */
	qong_init_nand_mtd();
	qong_init_dnet();
}

/*
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_init_imx_uart();
	qong_init_nor_mtd();
	qong_init_fpga();
}

static void __init qong_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer qong_timer = {
	.init	= qong_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_QONG data structure.
 */

MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
	/* Maintainer: DENX Software Engineering GmbH */
	.phys_io        = MX31_AIPS1_BASE_ADDR,
	.io_pg_offst    = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31_map_io,
	.init_irq       = mx31_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &qong_timer,
MACHINE_END
Commit	Line	Data
148854c6 IY	1	/*
	2	* Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#include <linux/types.h>
	20	#include <linux/init.h>
	21	#include <linux/kernel.h>
	22	#include <linux/memory.h>
	23	#include <linux/platform_device.h>
	24	#include <linux/mtd/physmap.h>
	25	#include <linux/mtd/nand.h>
	26	#include <linux/gpio.h>
	27
	28	#include <mach/hardware.h>
	29	#include <mach/irqs.h>
	30	#include <asm/mach-types.h>
	31	#include <asm/mach/arch.h>
	32	#include <asm/mach/time.h>
	33	#include <asm/mach/map.h>
	34	#include <mach/common.h>
	35	#include <asm/page.h>
	36	#include <asm/setup.h>
	37	#include <mach/board-qong.h>
	38	#include <mach/imx-uart.h>
	39	#include <mach/iomux-mx3.h>
	40	#include "devices.h"
	41
	42	/* FPGA defines */
	43	#define QONG_FPGA_VERSION(major, minor, rev) \
	44	(((major & 0xF) << 12) \| ((minor & 0xF) << 8) \| (rev & 0xFF))
	45
f568dd7f	46	#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
148854c6 IY	47	#define QONG_FPGA_PERIPH_SIZE (1 << 24)
	48
	49	#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
	50	#define QONG_FPGA_CTRL_SIZE 0x10
	51	/* FPGA control registers */
	52	#define QONG_FPGA_CTRL_VERSION 0x00
	53
	54	#define QONG_DNET_ID 1
	55	#define QONG_DNET_BASEADDR \
	56	(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
	57	#define QONG_DNET_SIZE 0x00001000
	58
	59	#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
	60
	61	/*
	62	* This file contains the board-specific initialization routines.
	63	*/
	64
	65	static struct imxuart_platform_data uart_pdata = {
	66	.flags = IMXUART_HAVE_RTSCTS,
	67	};
	68
	69	static int uart_pins[] = {
	70	MX31_PIN_CTS1__CTS1,
	71	MX31_PIN_RTS1__RTS1,
	72	MX31_PIN_TXD1__TXD1,
	73	MX31_PIN_RXD1__RXD1
	74	};
	75
	76	static inline void mxc_init_imx_uart(void)
	77	{
	78	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
	79	"uart-0");
	80	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	81	}
	82
	83	static struct resource dnet_resources[] = {
3f4f54b4	84	{
148854c6 IY	85	.name = "dnet-memory",
	86	.start = QONG_DNET_BASEADDR,
	87	.end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
	88	.flags = IORESOURCE_MEM,
3f4f54b4	89	}, {
148854c6 IY	90	.start = QONG_FPGA_IRQ,
	91	.end = QONG_FPGA_IRQ,
	92	.flags = IORESOURCE_IRQ,
	93	},
	94	};
	95
	96	static struct platform_device dnet_device = {
	97	.name = "dnet",
	98	.id = -1,
	99	.num_resources = ARRAY_SIZE(dnet_resources),
	100	.resource = dnet_resources,
	101	};
	102
	103	static int __init qong_init_dnet(void)
	104	{
	105	int ret;
	106
	107	ret = platform_device_register(&dnet_device);
	108	return ret;
	109	}
	110
	111	/* MTD NOR flash */
	112
	113	static struct physmap_flash_data qong_flash_data = {
	114	.width = 2,
	115	};
	116
	117	static struct resource qong_flash_resource = {
f568dd7f UKK	118	.start = MX31_CS0_BASE_ADDR,
f568dd7f UKK	119	.end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
148854c6 IY	120	.flags = IORESOURCE_MEM,
	121	};
	122
	123	static struct platform_device qong_nor_mtd_device = {
	124	.name = "physmap-flash",
	125	.id = 0,
	126	.dev = {
	127	.platform_data = &qong_flash_data,
	128	},
	129	.resource = &qong_flash_resource,
	130	.num_resources = 1,
	131	};
	132
	133	static void qong_init_nor_mtd(void)
	134	{
	135	(void)platform_device_register(&qong_nor_mtd_device);
	136	}
	137
	138	/*
	139	* Hardware specific access to control-lines
	140	*/
	141	static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
	142	{
	143	struct nand_chip *nand_chip = mtd->priv;
	144
	145	if (cmd == NAND_CMD_NONE)
	146	return;
	147
	148	if (ctrl & NAND_CLE)
	149	writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
	150	else
	151	writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
	152	}
	153
	154	/*
	155	* Read the Device Ready pin.
	156	*/
	157	static int qong_nand_device_ready(struct mtd_info *mtd)
	158	{
	159	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
	160	}
	161
	162	static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
	163	{
	164	if (chip >= 0)
	165	gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
	166	else
	167	gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
	168	}
	169
	170	static struct platform_nand_data qong_nand_data = {
	171	.chip = {
	172	.chip_delay = 20,
	173	.options = 0,
	174	},
	175	.ctrl = {
	176	.cmd_ctrl = qong_nand_cmd_ctrl,
	177	.dev_ready = qong_nand_device_ready,
	178	.select_chip = qong_nand_select_chip,
	179	}
	180	};
	181
	182	static struct resource qong_nand_resource = {
f568dd7f UKK	183	.start = MX31_CS3_BASE_ADDR,
f568dd7f UKK	184	.end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
148854c6 IY	185	.flags = IORESOURCE_MEM,
	186	};
	187
	188	static struct platform_device qong_nand_device = {
	189	.name = "gen_nand",
	190	.id = -1,
	191	.dev = {
	192	.platform_data = &qong_nand_data,
	193	},
	194	.num_resources = 1,
	195	.resource = &qong_nand_resource,
	196	};
	197
	198	static void __init qong_init_nand_mtd(void)
	199	{
	200	/* init CS */
a8dfb646	201	mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
148854c6 IY	202	mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
	203
	204	/* enable pin */
	205	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
	206	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
	207	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
	208
	209	/* ready/busy pin */
	210	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
	211	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
	212	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
	213
	214	/* write protect pin */
	215	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
	216	if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
	217	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
	218
	219	platform_device_register(&qong_nand_device);
	220	}
	221
	222	static void __init qong_init_fpga(void)
	223	{
	224	void __iomem *regs;
	225	u32 fpga_ver;
	226
	227	regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
	228	if (!regs) {
	229	printk(KERN_ERR "%s: failed to map registers, aborting.\n",
	230	__func__);
	231	return;
	232	}
	233
	234	fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
	235	iounmap(regs);
	236	printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
	237	(fpga_ver & 0xF000) >> 12,
	238	(fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
	239	if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
	240	printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
	241	"devices won't be registered!\n");
	242	return;
	243	}
	244
	245	/* register FPGA-based devices */
	246	qong_init_nand_mtd();
	247	qong_init_dnet();
	248	}
	249
148854c6 IY	250	/*
	251	* Board specific initialization.
	252	*/
	253	static void __init mxc_board_init(void)
	254	{
	255	mxc_init_imx_uart();
	256	qong_init_nor_mtd();
	257	qong_init_fpga();
	258	}
	259
	260	static void __init qong_timer_init(void)
	261	{
	262	mx31_clocks_init(26000000);
	263	}
	264
	265	static struct sys_timer qong_timer = {
	266	.init = qong_timer_init,
	267	};
	268
	269	/*
	270	* The following uses standard kernel macros defined in arch.h in order to
	271	* initialize __mach_desc_QONG data structure.
	272	*/
	273
	274	MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
	275	/* Maintainer: DENX Software Engineering GmbH */
f568dd7f	276	.phys_io = MX31_AIPS1_BASE_ADDR,
321ed164	277	.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237	278	.boot_params = MX3x_PHYS_OFFSET + 0x100,
35c82da0	279	.map_io = mx31_map_io,
c5aa0ad0	280	.init_irq = mx31_init_irq,
148854c6 IY	281	.init_machine = mxc_board_init,
	282	.timer = &qong_timer,
	283	MACHINE_END