[deliverable/linux.git] / arch / arm / mach-mx3 / mx31ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31ads.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif

#include "devices.h"

/*!
 * @file mx31ads.c
 *
 * @brief This file contains the board-specific initialization routines.
 *
 * @ingroup System
 */

#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/*!
 * The serial port definition structure.
 */
static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
		.mapbase  = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
		.irq      = EXPIO_INT_XUART_INTA,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	}, {
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
		.mapbase  = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
		.irq      = EXPIO_INT_XUART_INTB,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	},
	{},
};

static struct platform_device serial_device = {
	.name	= "serial8250",
	.id	= 0,
	.dev	= {
		.platform_data = serial_platform_data,
	},
};

static int __init mxc_init_extuart(void)
{
	return platform_device_register(&serial_device);
}
#else
static inline int mxc_init_extuart(void)
{
	return 0;
}
#endif

#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static unsigned int uart_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1
};

static inline void mxc_init_imx_uart(void)
{
	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
	mxc_register_device(&mxc_uart_device0, &uart_pdata);
}
#else /* !SERIAL_IMX */
static inline void mxc_init_imx_uart(void)
{
}
#endif /* !SERIAL_IMX */

static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 imr_val;
	u32 int_valid;
	u32 expio_irq;

	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;

	expio_irq = MXC_EXP_IO_BASE;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;

		generic_handle_irq(expio_irq);
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param irq           an expio virtual irq number
 */
static void expio_mask_irq(u32 irq)
{
	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	/* mask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	__raw_readw(PBC_INTMASK_CLEAR_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param irq           an expanded io virtual irq number
 */
static void expio_ack_irq(u32 irq)
{
	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	/* clear the interrupt status */
	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param irq           a expio virtual irq number
 */
static void expio_unmask_irq(u32 irq)
{
	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	/* unmask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}

static struct irq_chip expio_irq_chip = {
	.ack = expio_ack_irq,
	.mask = expio_mask_irq,
	.unmask = expio_unmask_irq,
};

static void __init mx31ads_init_expio(void)
{
	int i;

	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");

	/*
	 * Configure INT line as GPIO input
	 */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");

	/* disable the interrupt and clear the status */
	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
}

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
/* This section defines setup for the Wolfson Microelectronics
 * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 * regulator definitions may be shared with them, but for now they can
 * only be used with this board so would generate warnings about
 * unused statics and some of the configuration is specific to this
 * module.
 */

/* CPU */
static struct regulator_consumer_supply sw1a_consumers[] = {
	{
		.supply = "cpu_vcc",
	}
};

static struct regulator_init_data sw1a_data = {
	.constraints = {
		.name = "SW1A",
		.min_uV = 1275000,
		.max_uV = 1600000,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
				  REGULATOR_CHANGE_MODE,
		.valid_modes_mask = REGULATOR_MODE_NORMAL |
				    REGULATOR_MODE_FAST,
		.state_mem = {
			 .uV = 1400000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	.consumer_supplies = sw1a_consumers,
};

/* System IO - High */
static struct regulator_init_data viohi_data = {
	.constraints = {
		.name = "VIOHO",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.state_mem = {
			 .uV = 2800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* System IO - Low */
static struct regulator_init_data violo_data = {
	.constraints = {
		.name = "VIOLO",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* DDR RAM */
static struct regulator_init_data sw2a_data = {
	.constraints = {
		.name = "SW2A",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.state_disk = {
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 0,
		 },
		.always_on = 1,
		.boot_on = 1,
		.initial_state = PM_SUSPEND_MEM,
	},
};

static struct regulator_init_data ldo1_data = {
	.constraints = {
		.name = "VCAM/VMMC1/VMMC2",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
	},
};

static struct regulator_consumer_supply ldo2_consumers[] = {
	{ .supply = "AVDD", .dev_name = "1-001a" },
	{ .supply = "HPVDD", .dev_name = "1-001a" },
};

/* CODEC and SIM */
static struct regulator_init_data ldo2_data = {
	.constraints = {
		.name = "VESIM/VSIM/AVDD",
		.min_uV = 3300000,
		.max_uV = 3300000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	.consumer_supplies = ldo2_consumers,
};

/* General */
static struct regulator_init_data vdig_data = {
	.constraints = {
		.name = "VDIG",
		.min_uV = 1500000,
		.max_uV = 1500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* Tranceivers */
static struct regulator_init_data ldo4_data = {
	.constraints = {
		.name = "VRF1/CVDD_2.775",
		.min_uV = 2500000,
		.max_uV = 2500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

static struct wm8350_led_platform_data wm8350_led_data = {
	.name            = "wm8350:white",
	.default_trigger = "heartbeat",
	.max_uA          = 27899,
};

static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	.vmid_discharge_msecs = 1000,
	.drain_msecs = 30,
	.cap_discharge_msecs = 700,
	.vmid_charge_msecs = 700,
	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	.dis_out4 = WM8350_DISCHARGE_SLOW,
	.dis_out3 = WM8350_DISCHARGE_SLOW,
	.dis_out2 = WM8350_DISCHARGE_SLOW,
	.dis_out1 = WM8350_DISCHARGE_SLOW,
	.vroi_out4 = WM8350_TIE_OFF_500R,
	.vroi_out3 = WM8350_TIE_OFF_500R,
	.vroi_out2 = WM8350_TIE_OFF_500R,
	.vroi_out1 = WM8350_TIE_OFF_500R,
	.vroi_enable = 0,
	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
};

static int mx31_wm8350_init(struct wm8350 *wm8350)
{
	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);

	/* LEDs */
	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
			     WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
			       WM8350_ISINK_FLASH_DISABLE,
			       WM8350_ISINK_FLASH_TRIG_BIT,
			       WM8350_ISINK_FLASH_DUR_32MS,
			       WM8350_ISINK_FLASH_ON_INSTANT,
			       WM8350_ISINK_FLASH_OFF_INSTANT,
			       WM8350_ISINK_FLASH_MODE_EN);
	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
			       WM8350_ISINK_MODE_BOOST,
			       WM8350_ISINK_ILIM_NORMAL,
			       WM8350_DC5_RMP_20V,
			       WM8350_DC5_FBSRC_ISINKA);
	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
			    &wm8350_led_data);

	wm8350->codec.platform_data = &imx32ads_wm8350_setup;

	regulator_has_full_constraints();

	return 0;
}

static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	.init = mx31_wm8350_init,
};
#endif

#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	{
		I2C_BOARD_INFO("wm8350", 0x1a),
		.platform_data = &mx31_wm8350_pdata,
		.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	},
#endif
};

static void mxc_init_i2c(void)
{
	i2c_register_board_info(1, mx31ads_i2c1_devices,
				ARRAY_SIZE(mx31ads_i2c1_devices));

	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));

	mxc_register_device(&mxc_i2c_device1, NULL);
}
#else
static void mxc_init_i2c(void)
{
}
#endif

/*!
 * This structure defines static mappings for the i.MX31ADS board.
 */
static struct map_desc mx31ads_io_desc[] __initdata = {
	{
		.virtual	= SPBA0_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(SPBA0_BASE_ADDR),
		.length		= SPBA0_SIZE,
		.type		= MT_DEVICE_NONSHARED
	}, {
		.virtual	= CS4_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(CS4_BASE_ADDR),
		.length		= CS4_SIZE / 2,
		.type		= MT_DEVICE
	},
};

/*!
 * Set up static virtual mappings.
 */
static void __init mx31ads_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
}

static void __init mx31ads_init_irq(void)
{
	mx31_init_irq();
	mx31ads_init_expio();
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_init_extuart();
	mxc_init_imx_uart();
	mxc_init_i2c();
}

static void __init mx31ads_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31ads_timer = {
	.init	= mx31ads_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31ADS data structure.
 */
MACHINE_START(MX31ADS, "Freescale MX31ADS")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.phys_io	= AIPS1_BASE_ADDR,
	.io_pg_offst	= ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	.boot_params    = PHYS_OFFSET + 0x100,
	.map_io         = mx31ads_map_io,
	.init_irq       = mx31ads_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31ads_timer,
MACHINE_END
Commit	Line	Data
52c543f9 QJ	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#include <linux/types.h>
	22	#include <linux/init.h>
	23	#include <linux/clk.h>
	24	#include <linux/serial_8250.h>
fe7316bf MB	25	#include <linux/gpio.h>
fe7316bf MB	26	#include <linux/i2c.h>
d7568f79	27	#include <linux/irq.h>
52c543f9	28
a09e64fb	29	#include <mach/hardware.h>
52c543f9 QJ	30	#include <asm/mach-types.h>
52c543f9 QJ	31	#include <asm/mach/arch.h>
d0f349fb	32	#include <asm/mach/time.h>
52c543f9 QJ	33	#include <asm/memory.h>
52c543f9 QJ	34	#include <asm/mach/map.h>
a09e64fb RK	35	#include <mach/common.h>
a09e64fb RK	36	#include <mach/board-mx31ads.h>
0741794c GC	37	#include <mach/imx-uart.h>
0741794c GC	38	#include <mach/iomux-mx3.h>
52c543f9	39
fe7316bf MB	40	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	41	#include <linux/mfd/wm8350/audio.h>
	42	#include <linux/mfd/wm8350/core.h>
	43	#include <linux/mfd/wm8350/pmic.h>
	44	#endif
	45
2eca047b SH	46	#include "devices.h"
2eca047b SH	47
52c543f9 QJ	48	/*!
	49	* @file mx31ads.c
	50	*
	51	* @brief This file contains the board-specific initialization routines.
	52	*
	53	* @ingroup System
	54	*/
	55
	56	#if defined(CONFIG_SERIAL_8250) \|\| defined(CONFIG_SERIAL_8250_MODULE)
	57	/*!
	58	* The serial port definition structure.
	59	*/
	60	static struct plat_serial8250_port serial_platform_data[] = {
	61	{
	62	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
	63	.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA),
	64	.irq = EXPIO_INT_XUART_INTA,
	65	.uartclk = 14745600,
	66	.regshift = 0,
	67	.iotype = UPIO_MEM,
	68	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	69	}, {
	70	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
	71	.mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB),
	72	.irq = EXPIO_INT_XUART_INTB,
	73	.uartclk = 14745600,
	74	.regshift = 0,
	75	.iotype = UPIO_MEM,
	76	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	77	},
	78	{},
	79	};
	80
	81	static struct platform_device serial_device = {
	82	.name = "serial8250",
	83	.id = 0,
	84	.dev = {
	85	.platform_data = serial_platform_data,
	86	},
	87	};
	88
	89	static int __init mxc_init_extuart(void)
	90	{
	91	return platform_device_register(&serial_device);
	92	}
	93	#else
	94	static inline int mxc_init_extuart(void)
	95	{
	96	return 0;
	97	}
	98	#endif
	99
0741794c GC	100	#if defined(CONFIG_SERIAL_IMX) \|\| defined(CONFIG_SERIAL_IMX_MODULE)
	101	static struct imxuart_platform_data uart_pdata = {
	102	.flags = IMXUART_HAVE_RTSCTS,
	103	};
	104
9070e7af	105	static unsigned int uart_pins[] = {
945c10b8 VL	106	MX31_PIN_CTS1__CTS1,
	107	MX31_PIN_RTS1__RTS1,
	108	MX31_PIN_TXD1__TXD1,
	109	MX31_PIN_RXD1__RXD1
	110	};
	111
0741794c GC	112	static inline void mxc_init_imx_uart(void)
0741794c GC	113	{
945c10b8	114	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
0741794c GC	115	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	116	}
	117	#else /* !SERIAL_IMX */
	118	static inline void mxc_init_imx_uart(void)
	119	{
	120	}
	121	#endif /* !SERIAL_IMX */
	122
d7568f79 GC	123	static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
	124	{
	125	u32 imr_val;
	126	u32 int_valid;
	127	u32 expio_irq;
	128
	129	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	130	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
	131
	132	expio_irq = MXC_EXP_IO_BASE;
	133	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	134	if ((int_valid & 1) == 0)
	135	continue;
	136
	137	generic_handle_irq(expio_irq);
	138	}
	139	}
	140
	141	/*
	142	* Disable an expio pin's interrupt by setting the bit in the imr.
	143	* @param irq an expio virtual irq number
	144	*/
	145	static void expio_mask_irq(u32 irq)
	146	{
	147	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	148	/* mask the interrupt */
	149	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	150	__raw_readw(PBC_INTMASK_CLEAR_REG);
	151	}
	152
	153	/*
	154	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
	155	* @param irq an expanded io virtual irq number
	156	*/
	157	static void expio_ack_irq(u32 irq)
	158	{
	159	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	160	/* clear the interrupt status */
	161	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
	162	}
	163
	164	/*
	165	* Enable a expio pin's interrupt by clearing the bit in the imr.
	166	* @param irq a expio virtual irq number
	167	*/
	168	static void expio_unmask_irq(u32 irq)
	169	{
	170	u32 expio = MXC_IRQ_TO_EXPIO(irq);
	171	/* unmask the interrupt */
	172	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
	173	}
	174
	175	static struct irq_chip expio_irq_chip = {
	176	.ack = expio_ack_irq,
	177	.mask = expio_mask_irq,
	178	.unmask = expio_unmask_irq,
	179	};
	180
	181	static void __init mx31ads_init_expio(void)
	182	{
	183	int i;
	184
	185	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
	186
187	/*
188	* Configure INT line as GPIO input
189	*/
4f163eb8	190	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
d7568f79 GC	191
	192	/* disable the interrupt and clear the status */
	193	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	194	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	195	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	196	i++) {
	197	set_irq_chip(i, &expio_irq_chip);
	198	set_irq_handler(i, handle_level_irq);
	199	set_irq_flags(i, IRQF_VALID);
	200	}
	201	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	202	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
	203	}
	204
fe7316bf MB	205	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	206	/* This section defines setup for the Wolfson Microelectronics
	207	* 1133-EV1 PMU/audio board. When other PMU boards are supported the
	208	* regulator definitions may be shared with them, but for now they can
	209	* only be used with this board so would generate warnings about
	210	* unused statics and some of the configuration is specific to this
	211	* module.
	212	*/
	213
	214	/* CPU */
	215	static struct regulator_consumer_supply sw1a_consumers[] = {
	216	{
	217	.supply = "cpu_vcc",
	218	}
	219	};
	220
	221	static struct regulator_init_data sw1a_data = {
	222	.constraints = {
	223	.name = "SW1A",
	224	.min_uV = 1275000,
	225	.max_uV = 1600000,
	226	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	227	REGULATOR_CHANGE_MODE,
	228	.valid_modes_mask = REGULATOR_MODE_NORMAL \|
	229	REGULATOR_MODE_FAST,
	230	.state_mem = {
	231	.uV = 1400000,
	232	.mode = REGULATOR_MODE_NORMAL,
	233	.enabled = 1,
	234	},
	235	.initial_state = PM_SUSPEND_MEM,
	236	.always_on = 1,
	237	.boot_on = 1,
	238	},
	239	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	240	.consumer_supplies = sw1a_consumers,
	241	};
	242
	243	/* System IO - High */
	244	static struct regulator_init_data viohi_data = {
	245	.constraints = {
	246	.name = "VIOHO",
	247	.min_uV = 2800000,
	248	.max_uV = 2800000,
	249	.state_mem = {
	250	.uV = 2800000,
	251	.mode = REGULATOR_MODE_NORMAL,
	252	.enabled = 1,
	253	},
	254	.initial_state = PM_SUSPEND_MEM,
	255	.always_on = 1,
	256	.boot_on = 1,
	257	},
	258	};
	259
	260	/* System IO - Low */
	261	static struct regulator_init_data violo_data = {
	262	.constraints = {
	263	.name = "VIOLO",
	264	.min_uV = 1800000,
	265	.max_uV = 1800000,
	266	.state_mem = {
	267	.uV = 1800000,
	268	.mode = REGULATOR_MODE_NORMAL,
269	.enabled = 1,
270	},
271	.initial_state = PM_SUSPEND_MEM,
272	.always_on = 1,
273	.boot_on = 1,
274	},
275	};
276
277	/* DDR RAM */
278	static struct regulator_init_data sw2a_data = {
279	.constraints = {
280	.name = "SW2A",
281	.min_uV = 1800000,
282	.max_uV = 1800000,
283	.valid_modes_mask = REGULATOR_MODE_NORMAL,
284	.state_mem = {
285	.uV = 1800000,
286	.mode = REGULATOR_MODE_NORMAL,
287	.enabled = 1,
288	},
289	.state_disk = {
290	.mode = REGULATOR_MODE_NORMAL,
291	.enabled = 0,
292	},
293	.always_on = 1,
294	.boot_on = 1,
295	.initial_state = PM_SUSPEND_MEM,
296	},
297	};
298
299	static struct regulator_init_data ldo1_data = {
300	.constraints = {
301	.name = "VCAM/VMMC1/VMMC2",
302	.min_uV = 2800000,
303	.max_uV = 2800000,
304	.valid_modes_mask = REGULATOR_MODE_NORMAL,
305	.apply_uV = 1,
306	},
307	};
308
309	static struct regulator_consumer_supply ldo2_consumers[] = {
edc34a90 MB	310	{ .supply = "AVDD", .dev_name = "1-001a" },
edc34a90 MB	311	{ .supply = "HPVDD", .dev_name = "1-001a" },
fe7316bf MB	312	};
	313
	314	/* CODEC and SIM */
	315	static struct regulator_init_data ldo2_data = {
	316	.constraints = {
	317	.name = "VESIM/VSIM/AVDD",
	318	.min_uV = 3300000,
	319	.max_uV = 3300000,
	320	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	321	.apply_uV = 1,
	322	},
	323	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	324	.consumer_supplies = ldo2_consumers,
	325	};
	326
	327	/* General */
	328	static struct regulator_init_data vdig_data = {
	329	.constraints = {
	330	.name = "VDIG",
	331	.min_uV = 1500000,
	332	.max_uV = 1500000,
	333	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	334	.apply_uV = 1,
	335	.always_on = 1,
	336	.boot_on = 1,
	337	},
	338	};
	339
	340	/* Tranceivers */
	341	static struct regulator_init_data ldo4_data = {
	342	.constraints = {
	343	.name = "VRF1/CVDD_2.775",
	344	.min_uV = 2500000,
	345	.max_uV = 2500000,
	346	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	347	.apply_uV = 1,
	348	.always_on = 1,
	349	.boot_on = 1,
	350	},
	351	};
	352
	353	static struct wm8350_led_platform_data wm8350_led_data = {
	354	.name = "wm8350:white",
	355	.default_trigger = "heartbeat",
	356	.max_uA = 27899,
	357	};
	358
	359	static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	360	.vmid_discharge_msecs = 1000,
	361	.drain_msecs = 30,
	362	.cap_discharge_msecs = 700,
	363	.vmid_charge_msecs = 700,
	364	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	365	.dis_out4 = WM8350_DISCHARGE_SLOW,
	366	.dis_out3 = WM8350_DISCHARGE_SLOW,
	367	.dis_out2 = WM8350_DISCHARGE_SLOW,
	368	.dis_out1 = WM8350_DISCHARGE_SLOW,
	369	.vroi_out4 = WM8350_TIE_OFF_500R,
	370	.vroi_out3 = WM8350_TIE_OFF_500R,
	371	.vroi_out2 = WM8350_TIE_OFF_500R,
	372	.vroi_out1 = WM8350_TIE_OFF_500R,
	373	.vroi_enable = 0,
	374	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	375	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
376	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
377	};
378
379	static int mx31_wm8350_init(struct wm8350 *wm8350)
380	{
fe7316bf MB	381	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
	382	WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
	383	WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
	384	WM8350_GPIO_DEBOUNCE_ON);
	385
	386	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
	387	WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
	388	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	389	WM8350_GPIO_DEBOUNCE_ON);
	390
	391	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
	392	WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
	393	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	394	WM8350_GPIO_DEBOUNCE_OFF);
	395
	396	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
	397	WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
	398	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	399	WM8350_GPIO_DEBOUNCE_OFF);
	400
	401	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
	402	WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
	403	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	404	WM8350_GPIO_DEBOUNCE_OFF);
	405
	406	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
	407	WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	408	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	409	WM8350_GPIO_DEBOUNCE_OFF);
	410
	411	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
	412	WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	413	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	414	WM8350_GPIO_DEBOUNCE_OFF);
	415
fe7316bf MB	416	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	417	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	418	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	419	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	420	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	421	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	422	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	423	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
	424
	425	/* LEDs */
	426	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
	427	WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	428	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
	429	WM8350_ISINK_FLASH_DISABLE,
	430	WM8350_ISINK_FLASH_TRIG_BIT,
	431	WM8350_ISINK_FLASH_DUR_32MS,
	432	WM8350_ISINK_FLASH_ON_INSTANT,
	433	WM8350_ISINK_FLASH_OFF_INSTANT,
	434	WM8350_ISINK_FLASH_MODE_EN);
	435	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
	436	WM8350_ISINK_MODE_BOOST,
	437	WM8350_ISINK_ILIM_NORMAL,
	438	WM8350_DC5_RMP_20V,
	439	WM8350_DC5_FBSRC_ISINKA);
	440	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
	441	&wm8350_led_data);
	442
	443	wm8350->codec.platform_data = &imx32ads_wm8350_setup;
	444
0ac402fd MB	445	regulator_has_full_constraints();
0ac402fd MB	446
fe7316bf MB	447	return 0;
	448	}
	449
	450	static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	451	.init = mx31_wm8350_init,
	452	};
	453	#endif
	454
	455	#if defined(CONFIG_I2C_IMX) \|\| defined(CONFIG_I2C_IMX_MODULE)
	456	static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
	457	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	458	{
	459	I2C_BOARD_INFO("wm8350", 0x1a),
	460	.platform_data = &mx31_wm8350_pdata,
	461	.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	462	},
	463	#endif
	464	};
	465
	466	static void mxc_init_i2c(void)
	467	{
	468	i2c_register_board_info(1, mx31ads_i2c1_devices,
	469	ARRAY_SIZE(mx31ads_i2c1_devices));
	470
	471	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	472	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
	473
	474	mxc_register_device(&mxc_i2c_device1, NULL);
	475	}
	476	#else
	477	static void mxc_init_i2c(void)
	478	{
	479	}
	480	#endif
	481
52c543f9 QJ	482	/*!
	483	* This structure defines static mappings for the i.MX31ADS board.
	484	*/
	485	static struct map_desc mx31ads_io_desc[] __initdata = {
	486	{
52c543f9 QJ	487	.virtual = SPBA0_BASE_ADDR_VIRT,
	488	.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
	489	.length = SPBA0_SIZE,
9b727abd	490	.type = MT_DEVICE_NONSHARED
52c543f9 QJ	491	}, {
	492	.virtual = CS4_BASE_ADDR_VIRT,
	493	.pfn = __phys_to_pfn(CS4_BASE_ADDR),
	494	.length = CS4_SIZE / 2,
	495	.type = MT_DEVICE
	496	},
	497	};
	498
	499	/*!
	500	* Set up static virtual mappings.
	501	*/
8b785b9d	502	static void __init mx31ads_map_io(void)
52c543f9	503	{
cd4a05f9	504	mx31_map_io();
52c543f9 QJ	505	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
	506	}
	507
8b785b9d	508	static void __init mx31ads_init_irq(void)
d7568f79	509	{
c5aa0ad0	510	mx31_init_irq();
d7568f79 GC	511	mx31ads_init_expio();
	512	}
	513
52c543f9 QJ	514	/*!
	515	* Board specific initialization.
	516	*/
	517	static void __init mxc_board_init(void)
	518	{
	519	mxc_init_extuart();
0741794c	520	mxc_init_imx_uart();
fe7316bf	521	mxc_init_i2c();
52c543f9 QJ	522	}
52c543f9 QJ	523
d0f349fb JB	524	static void __init mx31ads_timer_init(void)
d0f349fb JB	525	{
30c730f8	526	mx31_clocks_init(26000000);
d0f349fb JB	527	}
d0f349fb JB	528
8b785b9d	529	static struct sys_timer mx31ads_timer = {
d0f349fb JB	530	.init = mx31ads_timer_init,
	531	};
	532
52c543f9 QJ	533	/*
	534	* The following uses standard kernel macros defined in arch.h in order to
	535	* initialize __mach_desc_MX31ADS data structure.
	536	*/
	537	MACHINE_START(MX31ADS, "Freescale MX31ADS")
	538	/* Maintainer: Freescale Semiconductor, Inc. */
	539	.phys_io = AIPS1_BASE_ADDR,
	540	.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	541	.boot_params = PHYS_OFFSET + 0x100,
	542	.map_io = mx31ads_map_io,
d7568f79	543	.init_irq = mx31ads_init_irq,
52c543f9	544	.init_machine = mxc_board_init,
d0f349fb	545	.timer = &mx31ads_timer,
52c543f9	546	MACHINE_END