[deliverable/linux.git] / arch / arm / mach-mx3 / pcm037.c

/*
 *  Copyright (C) 2008 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>

#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>

#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/board-pcm037.h>
#include <mach/mx3fb.h>
#include <mach/mxc_nand.h>
#include <mach/mmc.h>
#ifdef CONFIG_I2C_IMX
#include <mach/i2c.h>
#endif

#include "devices.h"

static unsigned int pcm037_pins[] = {
	/* I2C */
	MX31_PIN_CSPI2_MOSI__SCL,
	MX31_PIN_CSPI2_MISO__SDA,
	/* SDHC1 */
	MX31_PIN_SD1_DATA3__SD1_DATA3,
	MX31_PIN_SD1_DATA2__SD1_DATA2,
	MX31_PIN_SD1_DATA1__SD1_DATA1,
	MX31_PIN_SD1_DATA0__SD1_DATA0,
	MX31_PIN_SD1_CLK__SD1_CLK,
	MX31_PIN_SD1_CMD__SD1_CMD,
	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
	/* SPI1 */
	MX31_PIN_CSPI1_MOSI__MOSI,
	MX31_PIN_CSPI1_MISO__MISO,
	MX31_PIN_CSPI1_SCLK__SCLK,
	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI1_SS0__SS0,
	MX31_PIN_CSPI1_SS1__SS1,
	MX31_PIN_CSPI1_SS2__SS2,
	/* UART1 */
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
	/* UART2 */
	MX31_PIN_TXD2__TXD2,
	MX31_PIN_RXD2__RXD2,
	MX31_PIN_CTS2__CTS2,
	MX31_PIN_RTS2__RTS2,
	/* UART3 */
	MX31_PIN_CSPI3_MOSI__RXD3,
	MX31_PIN_CSPI3_MISO__TXD3,
	MX31_PIN_CSPI3_SCLK__RTS3,
	MX31_PIN_CSPI3_SPI_RDY__CTS3,
	/* LAN9217 irq pin */
	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
	/* Onewire */
	MX31_PIN_BATT_LINE__OWIRE,
	/* Framebuffer */
	MX31_PIN_LD0__LD0,
	MX31_PIN_LD1__LD1,
	MX31_PIN_LD2__LD2,
	MX31_PIN_LD3__LD3,
	MX31_PIN_LD4__LD4,
	MX31_PIN_LD5__LD5,
	MX31_PIN_LD6__LD6,
	MX31_PIN_LD7__LD7,
	MX31_PIN_LD8__LD8,
	MX31_PIN_LD9__LD9,
	MX31_PIN_LD10__LD10,
	MX31_PIN_LD11__LD11,
	MX31_PIN_LD12__LD12,
	MX31_PIN_LD13__LD13,
	MX31_PIN_LD14__LD14,
	MX31_PIN_LD15__LD15,
	MX31_PIN_LD16__LD16,
	MX31_PIN_LD17__LD17,
	MX31_PIN_VSYNC3__VSYNC3,
	MX31_PIN_HSYNC__HSYNC,
	MX31_PIN_FPSHIFT__FPSHIFT,
	MX31_PIN_DRDY0__DRDY0,
	MX31_PIN_D3_REV__D3_REV,
	MX31_PIN_CONTRAST__CONTRAST,
	MX31_PIN_D3_SPL__D3_SPL,
	MX31_PIN_D3_CLS__D3_CLS,
	MX31_PIN_LCS0__GPI03_23,
};

static struct physmap_flash_data pcm037_flash_data = {
	.width  = 2,
};

static struct resource pcm037_flash_resource = {
	.start	= 0xa0000000,
	.end	= 0xa1ffffff,
	.flags	= IORESOURCE_MEM,
};

static int usbotg_pins[] = {
	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	MX31_PIN_USBOTG_STP__USBOTG_STP,
};

/* USB OTG HS port */
static int __init gpio_usbotg_hs_activate(void)
{
	int ret = mxc_iomux_setup_multiple_pins(usbotg_pins,
					ARRAY_SIZE(usbotg_pins), "usbotg");

	if (ret < 0) {
		printk(KERN_ERR "Cannot set up OTG pins\n");
		return ret;
	}

	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);

	return 0;
}

/* OTG config */
static struct fsl_usb2_platform_data usb_pdata = {
	.operating_mode	= FSL_USB2_DR_DEVICE,
	.phy_mode	= FSL_USB2_PHY_ULPI,
};

static struct platform_device pcm037_flash = {
	.name	= "physmap-flash",
	.id	= 0,
	.dev	= {
		.platform_data  = &pcm037_flash_data,
	},
	.resource = &pcm037_flash_resource,
	.num_resources = 1,
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static struct resource smsc911x_resources[] = {
	[0] = {
		.start		= CS1_BASE_ADDR + 0x300,
		.end		= CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	},
	[1] = {
		.start		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
		.end		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
		.flags		= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
	},
};

static struct smsc911x_platform_config smsc911x_info = {
	.flags		= SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
			  SMSC911X_SAVE_MAC_ADDRESS,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct platform_device pcm037_eth = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_info,
	},
};

static struct platdata_mtd_ram pcm038_sram_data = {
	.bankwidth = 2,
};

static struct resource pcm038_sram_resource = {
	.start = CS4_BASE_ADDR,
	.end   = CS4_BASE_ADDR + 512 * 1024 - 1,
	.flags = IORESOURCE_MEM,
};

static struct platform_device pcm037_sram_device = {
	.name = "mtd-ram",
	.id = 0,
	.dev = {
		.platform_data = &pcm038_sram_data,
	},
	.num_resources = 1,
	.resource = &pcm038_sram_resource,
};

static struct mxc_nand_platform_data pcm037_nand_board_info = {
	.width = 1,
	.hw_ecc = 1,
};

#ifdef CONFIG_I2C_IMX
static struct imxi2c_platform_data pcm037_i2c_1_data = {
	.bitrate = 100000,
};

static struct at24_platform_data board_eeprom = {
	.byte_len = 4096,
	.page_size = 32,
	.flags = AT24_FLAG_ADDR16,
};

static struct i2c_board_info pcm037_i2c_devices[] = {
       {
		I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
		.platform_data = &board_eeprom,
	}, {
		I2C_BOARD_INFO("rtc-pcf8563", 0x51),
		.type = "pcf8563",
	}
};
#endif

/* Not connected by default */
#ifdef PCM970_SDHC_RW_SWITCH
static int pcm970_sdhc1_get_ro(struct device *dev)
{
	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
}
#endif

static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
		void *data)
{
	int ret;
	int gpio_det, gpio_wp;

	gpio_det = IOMUX_TO_GPIO(MX31_PIN_SCK6);
	gpio_wp = IOMUX_TO_GPIO(MX31_PIN_SFS6);

	gpio_direction_input(gpio_det);
	gpio_direction_input(gpio_wp);

	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
			IRQF_DISABLED | IRQF_TRIGGER_FALLING,
				"sdhc-detect", data);
	return ret;
}

static void pcm970_sdhc1_exit(struct device *dev, void *data)
{
	free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
}

static struct imxmmc_platform_data sdhc_pdata = {
#ifdef PCM970_SDHC_RW_SWITCH
	.get_ro = pcm970_sdhc1_get_ro,
#endif
	.init = pcm970_sdhc1_init,
	.exit = pcm970_sdhc1_exit,
};

static struct platform_device *devices[] __initdata = {
	&pcm037_flash,
	&pcm037_eth,
	&pcm037_sram_device,
};

static struct ipu_platform_data mx3_ipu_data = {
	.irq_base = MXC_IPU_IRQ_START,
};

static const struct fb_videomode fb_modedb[] = {
	{
		/* 240x320 @ 60 Hz Sharp */
		.name		= "Sharp-LQ035Q7DH06-QVGA",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 185925,
		.left_margin	= 9,
		.right_margin	= 16,
		.upper_margin	= 7,
		.lower_margin	= 9,
		.hsync_len	= 1,
		.vsync_len	= 1,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
				  FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	}, {
		/* 240x320 @ 60 Hz */
		.name		= "TX090",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 38255,
		.left_margin	= 144,
		.right_margin	= 0,
		.upper_margin	= 7,
		.lower_margin	= 40,
		.hsync_len	= 96,
		.vsync_len	= 1,
		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	},
};

static struct mx3fb_platform_data mx3fb_pdata = {
	.dma_dev	= &mx3_ipu.dev,
	.name		= "Sharp-LQ035Q7DH06-QVGA",
	.mode		= fb_modedb,
	.num_modes	= ARRAY_SIZE(fb_modedb),
};

/*
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
			"pcm037");

	platform_add_devices(devices, ARRAY_SIZE(devices));

	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	mxc_register_device(&mxc_uart_device1, &uart_pdata);
	mxc_register_device(&mxc_uart_device2, &uart_pdata);

	mxc_register_device(&mxc_w1_master_device, NULL);

	/* LAN9217 IRQ pin */
	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));

#ifdef CONFIG_I2C_IMX
	i2c_register_board_info(1, pcm037_i2c_devices,
			ARRAY_SIZE(pcm037_i2c_devices));

	mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
#endif
	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
	mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
	mxc_register_device(&mx3_fb, &mx3fb_pdata);
	if (!gpio_usbotg_hs_activate())
		mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
}

static void __init pcm037_timer_init(void)
{
	mx31_clocks_init(26000000);
}

struct sys_timer pcm037_timer = {
	.init	= pcm037_timer_init,
};

MACHINE_START(PCM037, "Phytec Phycore pcm037")
	/* Maintainer: Pengutronix */
	.phys_io	= AIPS1_BASE_ADDR,
	.io_pg_offst	= ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	.boot_params    = PHYS_OFFSET + 0x100,
	.map_io         = mx31_map_io,
	.init_irq       = mxc_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &pcm037_timer,
MACHINE_END
Commit	Line	Data
ce8ffef0 SH	1	/*
	2	* Copyright (C) 2008 Sascha Hauer, Pengutronix
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#include <linux/types.h>
	20	#include <linux/init.h>
	21
	22	#include <linux/platform_device.h>
	23	#include <linux/mtd/physmap.h>
3dad21a9	24	#include <linux/mtd/plat-ram.h>
ce8ffef0	25	#include <linux/memory.h>
ba54b958	26	#include <linux/gpio.h>
4353318e	27	#include <linux/smsc911x.h>
ba54b958	28	#include <linux/interrupt.h>
79206750 SH	29	#include <linux/i2c.h>
79206750 SH	30	#include <linux/i2c/at24.h>
dddd4a49 SH	31	#include <linux/delay.h>
	32	#include <linux/spi/spi.h>
	33	#include <linux/irq.h>
eb05bbeb	34	#include <linux/fsl_devices.h>
ce8ffef0	35
a09e64fb	36	#include <mach/hardware.h>
ce8ffef0 SH	37	#include <asm/mach-types.h>
	38	#include <asm/mach/arch.h>
	39	#include <asm/mach/time.h>
	40	#include <asm/mach/map.h>
a09e64fb RK	41	#include <mach/common.h>
	42	#include <mach/imx-uart.h>
	43	#include <mach/iomux-mx3.h>
a8df0ee8	44	#include <mach/ipu.h>
a09e64fb	45	#include <mach/board-pcm037.h>
a8df0ee8	46	#include <mach/mx3fb.h>
3287abbd	47	#include <mach/mxc_nand.h>
f2cb641f	48	#include <mach/mmc.h>
79206750 SH	49	#ifdef CONFIG_I2C_IMX
	50	#include <mach/i2c.h>
	51	#endif
ce8ffef0	52
5cf09421 SH	53	#include "devices.h"
5cf09421 SH	54
01ac7d58 SH	55	static unsigned int pcm037_pins[] = {
	56	/* I2C */
	57	MX31_PIN_CSPI2_MOSI__SCL,
	58	MX31_PIN_CSPI2_MISO__SDA,
	59	/* SDHC1 */
	60	MX31_PIN_SD1_DATA3__SD1_DATA3,
	61	MX31_PIN_SD1_DATA2__SD1_DATA2,
	62	MX31_PIN_SD1_DATA1__SD1_DATA1,
	63	MX31_PIN_SD1_DATA0__SD1_DATA0,
	64	MX31_PIN_SD1_CLK__SD1_CLK,
	65	MX31_PIN_SD1_CMD__SD1_CMD,
	66	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
	67	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
	68	/* SPI1 */
	69	MX31_PIN_CSPI1_MOSI__MOSI,
	70	MX31_PIN_CSPI1_MISO__MISO,
	71	MX31_PIN_CSPI1_SCLK__SCLK,
	72	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	73	MX31_PIN_CSPI1_SS0__SS0,
	74	MX31_PIN_CSPI1_SS1__SS1,
	75	MX31_PIN_CSPI1_SS2__SS2,
	76	/* UART1 */
	77	MX31_PIN_CTS1__CTS1,
	78	MX31_PIN_RTS1__RTS1,
	79	MX31_PIN_TXD1__TXD1,
	80	MX31_PIN_RXD1__RXD1,
	81	/* UART2 */
	82	MX31_PIN_TXD2__TXD2,
	83	MX31_PIN_RXD2__RXD2,
	84	MX31_PIN_CTS2__CTS2,
	85	MX31_PIN_RTS2__RTS2,
	86	/* UART3 */
	87	MX31_PIN_CSPI3_MOSI__RXD3,
	88	MX31_PIN_CSPI3_MISO__TXD3,
	89	MX31_PIN_CSPI3_SCLK__RTS3,
	90	MX31_PIN_CSPI3_SPI_RDY__CTS3,
	91	/* LAN9217 irq pin */
	92	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
	93	/* Onewire */
	94	MX31_PIN_BATT_LINE__OWIRE,
	95	/* Framebuffer */
	96	MX31_PIN_LD0__LD0,
	97	MX31_PIN_LD1__LD1,
	98	MX31_PIN_LD2__LD2,
	99	MX31_PIN_LD3__LD3,
	100	MX31_PIN_LD4__LD4,
	101	MX31_PIN_LD5__LD5,
	102	MX31_PIN_LD6__LD6,
	103	MX31_PIN_LD7__LD7,
	104	MX31_PIN_LD8__LD8,
	105	MX31_PIN_LD9__LD9,
	106	MX31_PIN_LD10__LD10,
	107	MX31_PIN_LD11__LD11,
	108	MX31_PIN_LD12__LD12,
	109	MX31_PIN_LD13__LD13,
	110	MX31_PIN_LD14__LD14,
	111	MX31_PIN_LD15__LD15,
	112	MX31_PIN_LD16__LD16,
	113	MX31_PIN_LD17__LD17,
	114	MX31_PIN_VSYNC3__VSYNC3,
	115	MX31_PIN_HSYNC__HSYNC,
	116	MX31_PIN_FPSHIFT__FPSHIFT,
	117	MX31_PIN_DRDY0__DRDY0,
	118	MX31_PIN_D3_REV__D3_REV,
119	MX31_PIN_CONTRAST__CONTRAST,
120	MX31_PIN_D3_SPL__D3_SPL,
121	MX31_PIN_D3_CLS__D3_CLS,
122	MX31_PIN_LCS0__GPI03_23,
123	};
124
ce8ffef0 SH	125	static struct physmap_flash_data pcm037_flash_data = {
	126	.width = 2,
	127	};
	128
	129	static struct resource pcm037_flash_resource = {
	130	.start = 0xa0000000,
	131	.end = 0xa1ffffff,
	132	.flags = IORESOURCE_MEM,
	133	};
	134
eb05bbeb GL	135	static int usbotg_pins[] = {
	136	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	137	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	138	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	139	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	140	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	141	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	142	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	143	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	144	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	145	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	146	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	147	MX31_PIN_USBOTG_STP__USBOTG_STP,
	148	};
	149
	150	/* USB OTG HS port */
	151	static int __init gpio_usbotg_hs_activate(void)
	152	{
	153	int ret = mxc_iomux_setup_multiple_pins(usbotg_pins,
	154	ARRAY_SIZE(usbotg_pins), "usbotg");
	155
	156	if (ret < 0) {
	157	printk(KERN_ERR "Cannot set up OTG pins\n");
	158	return ret;
	159	}
	160
	161	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	162	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	163	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	164	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	165	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	166	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	167	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	168	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	169	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	170	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	171	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	172	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	173
	174	return 0;
	175	}
	176
	177	/* OTG config */
	178	static struct fsl_usb2_platform_data usb_pdata = {
	179	.operating_mode = FSL_USB2_DR_DEVICE,
	180	.phy_mode = FSL_USB2_PHY_ULPI,
	181	};
	182
ce8ffef0 SH	183	static struct platform_device pcm037_flash = {
	184	.name = "physmap-flash",
	185	.id = 0,
	186	.dev = {
	187	.platform_data = &pcm037_flash_data,
	188	},
	189	.resource = &pcm037_flash_resource,
	190	.num_resources = 1,
	191	};
	192
	193	static struct imxuart_platform_data uart_pdata = {
a9b06233	194	.flags = IMXUART_HAVE_RTSCTS,
ce8ffef0 SH	195	};
ce8ffef0 SH	196
4353318e	197	static struct resource smsc911x_resources[] = {
ba54b958 GL	198	[0] = {
	199	.start = CS1_BASE_ADDR + 0x300,
	200	.end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
	201	.flags = IORESOURCE_MEM,
	202	},
	203	[1] = {
	204	.start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
	205	.end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
4353318e	206	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_LOWLEVEL,
ba54b958 GL	207	},
	208	};
	209
4353318e SG	210	static struct smsc911x_platform_config smsc911x_info = {
	211	.flags = SMSC911X_USE_32BIT \| SMSC911X_FORCE_INTERNAL_PHY \|
	212	SMSC911X_SAVE_MAC_ADDRESS,
	213	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	214	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	215	.phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958 GL	216	};
	217
	218	static struct platform_device pcm037_eth = {
4353318e	219	.name = "smsc911x",
ba54b958	220	.id = -1,
4353318e SG	221	.num_resources = ARRAY_SIZE(smsc911x_resources),
4353318e SG	222	.resource = smsc911x_resources,
ba54b958	223	.dev = {
4353318e	224	.platform_data = &smsc911x_info,
ba54b958 GL	225	},
	226	};
	227
3dad21a9 SH	228	static struct platdata_mtd_ram pcm038_sram_data = {
	229	.bankwidth = 2,
	230	};
	231
	232	static struct resource pcm038_sram_resource = {
	233	.start = CS4_BASE_ADDR,
	234	.end = CS4_BASE_ADDR + 512 * 1024 - 1,
	235	.flags = IORESOURCE_MEM,
	236	};
	237
	238	static struct platform_device pcm037_sram_device = {
	239	.name = "mtd-ram",
	240	.id = 0,
	241	.dev = {
	242	.platform_data = &pcm038_sram_data,
	243	},
	244	.num_resources = 1,
	245	.resource = &pcm038_sram_resource,
	246	};
	247
3287abbd SH	248	static struct mxc_nand_platform_data pcm037_nand_board_info = {
	249	.width = 1,
	250	.hw_ecc = 1,
	251	};
	252
79206750	253	#ifdef CONFIG_I2C_IMX
79206750 SH	254	static struct imxi2c_platform_data pcm037_i2c_1_data = {
79206750 SH	255	.bitrate = 100000,
79206750 SH	256	};
	257
	258	static struct at24_platform_data board_eeprom = {
	259	.byte_len = 4096,
	260	.page_size = 32,
	261	.flags = AT24_FLAG_ADDR16,
	262	};
	263
	264	static struct i2c_board_info pcm037_i2c_devices[] = {
	265	{
	266	I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
	267	.platform_data = &board_eeprom,
	268	}, {
	269	I2C_BOARD_INFO("rtc-pcf8563", 0x51),
	270	.type = "pcf8563",
	271	}
	272	};
	273	#endif
	274
dddd4a49 SH	275	/* Not connected by default */
	276	#ifdef PCM970_SDHC_RW_SWITCH
	277	static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f	278	{
dddd4a49 SH	279	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
	280	}
	281	#endif
	282
	283	static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
	284	void *data)
	285	{
	286	int ret;
	287	int gpio_det, gpio_wp;
	288
	289	gpio_det = IOMUX_TO_GPIO(MX31_PIN_SCK6);
	290	gpio_wp = IOMUX_TO_GPIO(MX31_PIN_SFS6);
	291
	292	gpio_direction_input(gpio_det);
	293	gpio_direction_input(gpio_wp);
	294
	295	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
	296	IRQF_DISABLED \| IRQF_TRIGGER_FALLING,
	297	"sdhc-detect", data);
	298	return ret;
f2cb641f SH	299	}
	300
	301	static void pcm970_sdhc1_exit(struct device dev, void data)
	302	{
dddd4a49	303	free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
f2cb641f SH	304	}
f2cb641f SH	305
f2cb641f	306	static struct imxmmc_platform_data sdhc_pdata = {
dddd4a49 SH	307	#ifdef PCM970_SDHC_RW_SWITCH
	308	.get_ro = pcm970_sdhc1_get_ro,
	309	#endif
f2cb641f SH	310	.init = pcm970_sdhc1_init,
	311	.exit = pcm970_sdhc1_exit,
	312	};
	313
ce8ffef0 SH	314	static struct platform_device *devices[] __initdata = {
ce8ffef0 SH	315	&pcm037_flash,
ba54b958	316	&pcm037_eth,
3dad21a9	317	&pcm037_sram_device,
ce8ffef0 SH	318	};
ce8ffef0 SH	319
a8df0ee8 GL	320	static struct ipu_platform_data mx3_ipu_data = {
	321	.irq_base = MXC_IPU_IRQ_START,
	322	};
	323
	324	static const struct fb_videomode fb_modedb[] = {
	325	{
	326	/* 240x320 @ 60 Hz Sharp */
	327	.name = "Sharp-LQ035Q7DH06-QVGA",
	328	.refresh = 60,
	329	.xres = 240,
	330	.yres = 320,
	331	.pixclock = 185925,
	332	.left_margin = 9,
	333	.right_margin = 16,
	334	.upper_margin = 7,
	335	.lower_margin = 9,
	336	.hsync_len = 1,
	337	.vsync_len = 1,
	338	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_SHARP_MODE \|
	339	FB_SYNC_CLK_INVERT \| FB_SYNC_CLK_IDLE_EN,
	340	.vmode = FB_VMODE_NONINTERLACED,
	341	.flag = 0,
	342	}, {
	343	/* 240x320 @ 60 Hz */
	344	.name = "TX090",
	345	.refresh = 60,
	346	.xres = 240,
	347	.yres = 320,
	348	.pixclock = 38255,
	349	.left_margin = 144,
	350	.right_margin = 0,
	351	.upper_margin = 7,
	352	.lower_margin = 40,
	353	.hsync_len = 96,
	354	.vsync_len = 1,
	355	.sync = FB_SYNC_VERT_HIGH_ACT \| FB_SYNC_OE_ACT_HIGH,
	356	.vmode = FB_VMODE_NONINTERLACED,
	357	.flag = 0,
	358	},
	359	};
	360
	361	static struct mx3fb_platform_data mx3fb_pdata = {
	362	.dma_dev = &mx3_ipu.dev,
	363	.name = "Sharp-LQ035Q7DH06-QVGA",
	364	.mode = fb_modedb,
	365	.num_modes = ARRAY_SIZE(fb_modedb),
	366	};
	367
ce8ffef0 SH	368	/*
	369	* Board specific initialization.
	370	*/
	371	static void __init mxc_board_init(void)
	372	{
01ac7d58 SH	373	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
	374	"pcm037");
	375
ce8ffef0 SH	376	platform_add_devices(devices, ARRAY_SIZE(devices));
ce8ffef0 SH	377
5cf09421	378	mxc_register_device(&mxc_uart_device0, &uart_pdata);
13e9f612	379	mxc_register_device(&mxc_uart_device1, &uart_pdata);
5cf09421	380	mxc_register_device(&mxc_uart_device2, &uart_pdata);
d517cab1	381
d517cab1	382	mxc_register_device(&mxc_w1_master_device, NULL);
ba54b958	383
f8e5143b	384	/* LAN9217 IRQ pin */
01ac7d58	385	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
3287abbd	386
79206750 SH	387	#ifdef CONFIG_I2C_IMX
	388	i2c_register_board_info(1, pcm037_i2c_devices,
	389	ARRAY_SIZE(pcm037_i2c_devices));
	390
	391	mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
	392	#endif
3287abbd	393	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
f2cb641f	394	mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
a8df0ee8 GL	395	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
a8df0ee8 GL	396	mxc_register_device(&mx3_fb, &mx3fb_pdata);
eb05bbeb GL	397	if (!gpio_usbotg_hs_activate())
eb05bbeb GL	398	mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
ce8ffef0 SH	399	}
ce8ffef0 SH	400
ce8ffef0 SH	401	static void __init pcm037_timer_init(void)
ce8ffef0 SH	402	{
30c730f8	403	mx31_clocks_init(26000000);
ce8ffef0 SH	404	}
	405
	406	struct sys_timer pcm037_timer = {
	407	.init = pcm037_timer_init,
	408	};
	409
	410	MACHINE_START(PCM037, "Phytec Phycore pcm037")
	411	/* Maintainer: Pengutronix */
	412	.phys_io = AIPS1_BASE_ADDR,
	413	.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
	414	.boot_params = PHYS_OFFSET + 0x100,
cd4a05f9	415	.map_io = mx31_map_io,
ce8ffef0 SH	416	.init_irq = mxc_init_irq,
	417	.init_machine = mxc_board_init,
	418	.timer = &pcm037_timer,
	419	MACHINE_END
	420