[deliverable/linux.git] / arch / arm / mach-mx5 / board-cpuimx51.c

/*
 *
 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
 *
 * based on board-mx51_babbage.c which is
 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>

#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>

#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

#include "devices-imx51.h"
#include "devices.h"

#define CPUIMX51_USBH1_STP	IMX_GPIO_NR(1, 27)
#define CPUIMX51_QUARTA_GPIO	IMX_GPIO_NR(3, 28)
#define CPUIMX51_QUARTB_GPIO	IMX_GPIO_NR(3, 25)
#define CPUIMX51_QUARTC_GPIO	IMX_GPIO_NR(3, 26)
#define CPUIMX51_QUARTD_GPIO	IMX_GPIO_NR(3, 27)
#define CPUIMX51_QUARTA_IRQ	(MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
#define CPUIMX51_QUARTB_IRQ	(MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
#define CPUIMX51_QUARTC_IRQ	(MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
#define CPUIMX51_QUARTD_IRQ	(MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
#define CPUIMX51_QUART_XTAL	14745600
#define CPUIMX51_QUART_REGSHIFT	17

/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET		0x10
#define MX51_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)

#define	MX51_USB_PLLDIV_12_MHZ		0x00
#define	MX51_USB_PLL_DIV_19_2_MHZ	0x01
#define	MX51_USB_PLL_DIV_24_MHZ		0x02

static struct plat_serial8250_port serial_platform_data[] = {
	{
		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
		.irq = CPUIMX51_QUARTA_IRQ,
		.irqflags = IRQF_TRIGGER_HIGH,
		.uartclk = CPUIMX51_QUART_XTAL,
		.regshift = CPUIMX51_QUART_REGSHIFT,
		.iotype = UPIO_MEM,
		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
	}, {
		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
		.irq = CPUIMX51_QUARTB_IRQ,
		.irqflags = IRQF_TRIGGER_HIGH,
		.uartclk = CPUIMX51_QUART_XTAL,
		.regshift = CPUIMX51_QUART_REGSHIFT,
		.iotype = UPIO_MEM,
		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
	}, {
		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
		.irq = CPUIMX51_QUARTC_IRQ,
		.irqflags = IRQF_TRIGGER_HIGH,
		.uartclk = CPUIMX51_QUART_XTAL,
		.regshift = CPUIMX51_QUART_REGSHIFT,
		.iotype = UPIO_MEM,
		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
	}, {
		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
		.irq = CPUIMX51_QUARTD_IRQ,
		.irqflags = IRQF_TRIGGER_HIGH,
		.uartclk = CPUIMX51_QUART_XTAL,
		.regshift = CPUIMX51_QUART_REGSHIFT,
		.iotype = UPIO_MEM,
		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
	}, {
	}
};

static struct platform_device serial_device = {
	.name = "serial8250",
	.id = 0,
	.dev = {
		.platform_data = serial_platform_data,
	},
};

static struct platform_device *devices[] __initdata = {
	&serial_device,
};

static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
	/* UART1 */
	MX51_PAD_UART1_RXD__UART1_RXD,
	MX51_PAD_UART1_TXD__UART1_TXD,
	MX51_PAD_UART1_RTS__UART1_RTS,
	MX51_PAD_UART1_CTS__UART1_CTS,

	/* I2C2 */
	MX51_PAD_GPIO1_2__I2C2_SCL,
	MX51_PAD_GPIO1_3__I2C2_SDA,
	MX51_PAD_NANDF_D10__GPIO3_30,

	/* QUART IRQ */
	MX51_PAD_NANDF_D15__GPIO3_25,
	MX51_PAD_NANDF_D14__GPIO3_26,
	MX51_PAD_NANDF_D13__GPIO3_27,
	MX51_PAD_NANDF_D12__GPIO3_28,

	/* USB HOST1 */
	MX51_PAD_USBH1_CLK__USBH1_CLK,
	MX51_PAD_USBH1_DIR__USBH1_DIR,
	MX51_PAD_USBH1_NXT__USBH1_NXT,
	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	MX51_PAD_USBH1_STP__USBH1_STP,
};

static const struct mxc_nand_platform_data
		eukrea_cpuimx51_nand_board_info __initconst = {
	.width		= 1,
	.hw_ecc		= 1,
	.flash_bbt	= 1,
};

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static const
struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
	.bitrate = 100000,
};

static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
	{
		I2C_BOARD_INFO("pcf8563", 0x51),
	},
};

/* This function is board specific as the bit mask for the plldiv will also
be different for other Freescale SoCs, thus a common bitmask is not
possible and cannot get place in /plat-mxc/ehci.c.*/
static int initialize_otg_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* Set the PHY clock to 19.2MHz */
	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	v |= MX51_USB_PLL_DIV_19_2_MHZ;
	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
}

static int initialize_usbh1_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;

	usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
	if (!usb_base)
		return -ENOMEM;
	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;

	/* The clock for the USBH1 ULPI port will come externally from the PHY. */
	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
	iounmap(usb_base);

	mdelay(10);

	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
			MXC_EHCI_ITC_NO_THRESHOLD);
}

static struct mxc_usbh_platform_data dr_utmi_config = {
	.init		= initialize_otg_port,
	.portsc	= MXC_EHCI_UTMI_16BIT,
};

static struct fsl_usb2_platform_data usb_pdata = {
	.operating_mode	= FSL_USB2_DR_DEVICE,
	.phy_mode	= FSL_USB2_PHY_UTMI_WIDE,
};

static struct mxc_usbh_platform_data usbh1_config = {
	.init		= initialize_usbh1_port,
	.portsc	= MXC_EHCI_MODE_ULPI,
};

static int otg_mode_host;

static int __init eukrea_cpuimx51_otg_mode(char *options)
{
	if (!strcmp(options, "host"))
		otg_mode_host = 1;
	else if (!strcmp(options, "device"))
		otg_mode_host = 0;
	else
		pr_info("otg_mode neither \"host\" nor \"device\". "
			"Defaulting to device\n");
	return 0;
}
__setup("otg_mode=", eukrea_cpuimx51_otg_mode);

/*
 * Board specific initialization.
 */
static void __init eukrea_cpuimx51_init(void)
{
	imx51_soc_init();

	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
					ARRAY_SIZE(eukrea_cpuimx51_pads));

	imx51_add_imx_uart(0, &uart_pdata);
	imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);

	gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
	gpio_direction_input(CPUIMX51_QUARTA_GPIO);
	gpio_free(CPUIMX51_QUARTA_GPIO);
	gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
	gpio_direction_input(CPUIMX51_QUARTB_GPIO);
	gpio_free(CPUIMX51_QUARTB_GPIO);
	gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
	gpio_direction_input(CPUIMX51_QUARTC_GPIO);
	gpio_free(CPUIMX51_QUARTC_GPIO);
	gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
	gpio_direction_input(CPUIMX51_QUARTD_GPIO);
	gpio_free(CPUIMX51_QUARTD_GPIO);

	imx51_add_fec(NULL);
	platform_add_devices(devices, ARRAY_SIZE(devices));

	imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
	i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
				ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));

	if (otg_mode_host)
		mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
	else {
		initialize_otg_port(NULL);
		mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
	}
	mxc_register_device(&mxc_usbh1_device, &usbh1_config);

#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
	eukrea_mbimx51_baseboard_init();
#endif
}

static void __init eukrea_cpuimx51_timer_init(void)
{
	mx51_clocks_init(32768, 24000000, 22579200, 0);
}

static struct sys_timer mxc_timer = {
	.init	= eukrea_cpuimx51_timer_init,
};

MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
	/* Maintainer: Eric Bénard <eric@eukrea.com> */
	.boot_params = MX51_PHYS_OFFSET + 0x100,
	.map_io = mx51_map_io,
	.init_early = imx51_init_early,
	.init_irq = mx51_init_irq,
	.timer = &mxc_timer,
	.init_machine = eukrea_cpuimx51_init,
MACHINE_END
Commit	Line	Data
ef93f144 EB	1	/*
	2	*
	3	* Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
	4	*
	5	* based on board-mx51_babbage.c which is
	6	* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
	7	* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
	8	*
	9	* The code contained herein is licensed under the GNU General Public
	10	* License. You may obtain a copy of the GNU General Public License
	11	* Version 2 or later at the following locations:
	12	*
	13	* http://www.opensource.org/licenses/gpl-license.html
	14	* http://www.gnu.org/copyleft/gpl.html
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/serial_8250.h>
	20	#include <linux/i2c.h>
	21	#include <linux/gpio.h>
	22	#include <linux/delay.h>
	23	#include <linux/io.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
ef93f144 EB	26
	27	#include <mach/eukrea-baseboards.h>
	28	#include <mach/common.h>
	29	#include <mach/hardware.h>
ef93f144	30	#include <mach/iomux-mx51.h>
ef93f144 EB	31
	32	#include <asm/irq.h>
	33	#include <asm/setup.h>
	34	#include <asm/mach-types.h>
	35	#include <asm/mach/arch.h>
	36	#include <asm/mach/time.h>
	37
04b73b15	38	#include "devices-imx51.h"
ef93f144 EB	39	#include "devices.h"
ef93f144 EB	40
96886c43 APR	41	#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
	42	#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
	43	#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
	44	#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
	45	#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
ef93f144 EB	46	#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
	47	#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
	48	#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
	49	#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
	50	#define CPUIMX51_QUART_XTAL 14745600
	51	#define CPUIMX51_QUART_REGSHIFT 17
	52
	53	/* USB_CTRL_1 */
	54	#define MX51_USB_CTRL_1_OFFSET 0x10
	55	#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
	56
	57	#define MX51_USB_PLLDIV_12_MHZ 0x00
	58	#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
	59	#define MX51_USB_PLL_DIV_24_MHZ 0x02
	60
ef93f144 EB	61	static struct plat_serial8250_port serial_platform_data[] = {
	62	{
	63	.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
	64	.irq = CPUIMX51_QUARTA_IRQ,
	65	.irqflags = IRQF_TRIGGER_HIGH,
	66	.uartclk = CPUIMX51_QUART_XTAL,
	67	.regshift = CPUIMX51_QUART_REGSHIFT,
	68	.iotype = UPIO_MEM,
	69	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_IOREMAP,
	70	}, {
	71	.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
	72	.irq = CPUIMX51_QUARTB_IRQ,
	73	.irqflags = IRQF_TRIGGER_HIGH,
	74	.uartclk = CPUIMX51_QUART_XTAL,
	75	.regshift = CPUIMX51_QUART_REGSHIFT,
	76	.iotype = UPIO_MEM,
	77	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_IOREMAP,
	78	}, {
	79	.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
	80	.irq = CPUIMX51_QUARTC_IRQ,
	81	.irqflags = IRQF_TRIGGER_HIGH,
	82	.uartclk = CPUIMX51_QUART_XTAL,
	83	.regshift = CPUIMX51_QUART_REGSHIFT,
	84	.iotype = UPIO_MEM,
	85	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_IOREMAP,
	86	}, {
	87	.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
	88	.irq = CPUIMX51_QUARTD_IRQ,
	89	.irqflags = IRQF_TRIGGER_HIGH,
	90	.uartclk = CPUIMX51_QUART_XTAL,
	91	.regshift = CPUIMX51_QUART_REGSHIFT,
	92	.iotype = UPIO_MEM,
	93	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_IOREMAP,
	94	}, {
	95	}
	96	};
	97
	98	static struct platform_device serial_device = {
	99	.name = "serial8250",
	100	.id = 0,
	101	.dev = {
	102	.platform_data = serial_platform_data,
	103	},
	104	};
ef93f144 EB	105
ef93f144 EB	106	static struct platform_device *devices[] __initdata = {
ef93f144	107	&serial_device,
ef93f144 EB	108	};
ef93f144 EB	109
8f5260c8	110	static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
ef93f144 EB	111	/* UART1 */
	112	MX51_PAD_UART1_RXD__UART1_RXD,
	113	MX51_PAD_UART1_TXD__UART1_TXD,
	114	MX51_PAD_UART1_RTS__UART1_RTS,
	115	MX51_PAD_UART1_CTS__UART1_CTS,
	116
	117	/* I2C2 */
ee1ae4d7 SH	118	MX51_PAD_GPIO1_2__I2C2_SCL,
	119	MX51_PAD_GPIO1_3__I2C2_SDA,
	120	MX51_PAD_NANDF_D10__GPIO3_30,
ef93f144 EB	121
ef93f144 EB	122	/* QUART IRQ */
ee1ae4d7 SH	123	MX51_PAD_NANDF_D15__GPIO3_25,
	124	MX51_PAD_NANDF_D14__GPIO3_26,
	125	MX51_PAD_NANDF_D13__GPIO3_27,
	126	MX51_PAD_NANDF_D12__GPIO3_28,
ef93f144 EB	127
	128	/* USB HOST1 */
	129	MX51_PAD_USBH1_CLK__USBH1_CLK,
	130	MX51_PAD_USBH1_DIR__USBH1_DIR,
	131	MX51_PAD_USBH1_NXT__USBH1_NXT,
	132	MX51_PAD_USBH1_DATA0__USBH1_DATA0,
	133	MX51_PAD_USBH1_DATA1__USBH1_DATA1,
	134	MX51_PAD_USBH1_DATA2__USBH1_DATA2,
	135	MX51_PAD_USBH1_DATA3__USBH1_DATA3,
	136	MX51_PAD_USBH1_DATA4__USBH1_DATA4,
	137	MX51_PAD_USBH1_DATA5__USBH1_DATA5,
	138	MX51_PAD_USBH1_DATA6__USBH1_DATA6,
	139	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
	140	MX51_PAD_USBH1_STP__USBH1_STP,
	141	};
	142
a3927416 EB	143	static const struct mxc_nand_platform_data
	144	eukrea_cpuimx51_nand_board_info __initconst = {
	145	.width = 1,
	146	.hw_ecc = 1,
	147	.flash_bbt = 1,
	148	};
	149
04b73b15	150	static const struct imxuart_platform_data uart_pdata __initconst = {
ef93f144 EB	151	.flags = IMXUART_HAVE_RTSCTS,
	152	};
	153
44505c07 UKK	154	static const
44505c07 UKK	155	struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
ef93f144 EB	156	.bitrate = 100000,
	157	};
	158
	159	static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
	160	{
	161	I2C_BOARD_INFO("pcf8563", 0x51),
	162	},
	163	};
	164
	165	/* This function is board specific as the bit mask for the plldiv will also
	166	be different for other Freescale SoCs, thus a common bitmask is not
	167	possible and cannot get place in /plat-mxc/ehci.c.*/
	168	static int initialize_otg_port(struct platform_device *pdev)
	169	{
	170	u32 v;
	171	void __iomem *usb_base;
	172	void __iomem *usbother_base;
	173
	174	usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	175	if (!usb_base)
28a4f908 FE	176	return -ENOMEM;
ef93f144 EB	177	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	178
	179	/* Set the PHY clock to 19.2MHz */
	180	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	181	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	182	v \|= MX51_USB_PLL_DIV_19_2_MHZ;
	183	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	184	iounmap(usb_base);
4bd597b6 SH	185
	186	mdelay(10);
	187
	188	return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
ef93f144 EB	189	}
	190
	191	static int initialize_usbh1_port(struct platform_device *pdev)
	192	{
	193	u32 v;
	194	void __iomem *usb_base;
	195	void __iomem *usbother_base;
	196
	197	usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
28a4f908 FE	198	if (!usb_base)
28a4f908 FE	199	return -ENOMEM;
ef93f144 EB	200	usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
	201
	202	/* The clock for the USBH1 ULPI port will come externally from the PHY. */
	203	v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
	204	__raw_writel(v \| MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
	205	iounmap(usb_base);
4bd597b6 SH	206
	207	mdelay(10);
	208
	209	return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED \|
	210	MXC_EHCI_ITC_NO_THRESHOLD);
ef93f144 EB	211	}
	212
	213	static struct mxc_usbh_platform_data dr_utmi_config = {
	214	.init = initialize_otg_port,
	215	.portsc = MXC_EHCI_UTMI_16BIT,
ef93f144 EB	216	};
	217
	218	static struct fsl_usb2_platform_data usb_pdata = {
	219	.operating_mode = FSL_USB2_DR_DEVICE,
	220	.phy_mode = FSL_USB2_PHY_UTMI_WIDE,
	221	};
	222
	223	static struct mxc_usbh_platform_data usbh1_config = {
	224	.init = initialize_usbh1_port,
	225	.portsc = MXC_EHCI_MODE_ULPI,
ef93f144 EB	226	};
	227
	228	static int otg_mode_host;
	229
	230	static int __init eukrea_cpuimx51_otg_mode(char *options)
	231	{
	232	if (!strcmp(options, "host"))
	233	otg_mode_host = 1;
	234	else if (!strcmp(options, "device"))
	235	otg_mode_host = 0;
	236	else
	237	pr_info("otg_mode neither \"host\" nor \"device\". "
	238	"Defaulting to device\n");
	239	return 0;
	240	}
	241	__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
	242
	243	/*
	244	* Board specific initialization.
	245	*/
	246	static void __init eukrea_cpuimx51_init(void)
	247	{
b78d8e59 SG	248	imx51_soc_init();
b78d8e59 SG	249
ef93f144 EB	250	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
	251	ARRAY_SIZE(eukrea_cpuimx51_pads));
	252
04b73b15	253	imx51_add_imx_uart(0, &uart_pdata);
a3927416 EB	254	imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
a3927416 EB	255
ef93f144 EB	256	gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
	257	gpio_direction_input(CPUIMX51_QUARTA_GPIO);
	258	gpio_free(CPUIMX51_QUARTA_GPIO);
	259	gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
	260	gpio_direction_input(CPUIMX51_QUARTB_GPIO);
	261	gpio_free(CPUIMX51_QUARTB_GPIO);
	262	gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
	263	gpio_direction_input(CPUIMX51_QUARTC_GPIO);
	264	gpio_free(CPUIMX51_QUARTC_GPIO);
	265	gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
	266	gpio_direction_input(CPUIMX51_QUARTD_GPIO);
	267	gpio_free(CPUIMX51_QUARTD_GPIO);
	268
6bd96f3c	269	imx51_add_fec(NULL);
ef93f144 EB	270	platform_add_devices(devices, ARRAY_SIZE(devices));
ef93f144 EB	271
44505c07	272	imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
ef93f144 EB	273	i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
	274	ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
	275
	276	if (otg_mode_host)
	277	mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
	278	else {
	279	initialize_otg_port(NULL);
	280	mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
	281	}
	282	mxc_register_device(&mxc_usbh1_device, &usbh1_config);
	283
	284	#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
	285	eukrea_mbimx51_baseboard_init();
	286	#endif
	287	}
	288
	289	static void __init eukrea_cpuimx51_timer_init(void)
	290	{
	291	mx51_clocks_init(32768, 24000000, 22579200, 0);
	292	}
	293
	294	static struct sys_timer mxc_timer = {
	295	.init = eukrea_cpuimx51_timer_init,
	296	};
	297
	298	MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
	299	/* Maintainer: Eric Bénard <eric@eukrea.com> */
7608d7d2	300	.boot_params = MX51_PHYS_OFFSET + 0x100,
ef93f144	301	.map_io = mx51_map_io,
ab130421	302	.init_early = imx51_init_early,
ef93f144	303	.init_irq = mx51_init_irq,
ef93f144	304	.timer = &mxc_timer,
ab130421	305	.init_machine = eukrea_cpuimx51_init,
ef93f144	306	MACHINE_END