[deliverable/linux.git] / arch / arm / mach-mx5 / board-mx51_efikamx.c

/*
 * Copyright (C) 2010 Linaro Limited
 *
 * based on code from the following
 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/fsl_devices.h>

#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <mach/i2c.h>
#include <mach/mxc_ehci.h>

#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>

#include "devices-imx51.h"
#include "devices.h"

#define	MX51_USB_PLL_DIV_24_MHZ	0x01

#define EFIKAMX_PCBID0		(2*32 + 16)
#define EFIKAMX_PCBID1		(2*32 + 17)
#define EFIKAMX_PCBID2		(2*32 + 11)

#define EFIKAMX_BLUE_LED	(2*32 + 13)
#define EFIKAMX_GREEN_LED	(2*32 + 14)
#define EFIKAMX_RED_LED		(2*32 + 15)

/* the pci ids pin have pull up. they're driven low according to board id */
#define MX51_PAD_PCBID0	IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PCBID1	IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PCBID2	IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)

static iomux_v3_cfg_t mx51efikamx_pads[] = {
	/* UART1 */
	MX51_PAD_UART1_RXD__UART1_RXD,
	MX51_PAD_UART1_TXD__UART1_TXD,
	MX51_PAD_UART1_RTS__UART1_RTS,
	MX51_PAD_UART1_CTS__UART1_CTS,
	/* board id */
	MX51_PAD_PCBID0,
	MX51_PAD_PCBID1,
	MX51_PAD_PCBID2,

	/* SD 1 */
	MX51_PAD_SD1_CMD__SD1_CMD,
	MX51_PAD_SD1_CLK__SD1_CLK,
	MX51_PAD_SD1_DATA0__SD1_DATA0,
	MX51_PAD_SD1_DATA1__SD1_DATA1,
	MX51_PAD_SD1_DATA2__SD1_DATA2,
	MX51_PAD_SD1_DATA3__SD1_DATA3,

	/* SD 2 */
	MX51_PAD_SD2_CMD__SD2_CMD,
	MX51_PAD_SD2_CLK__SD2_CLK,
	MX51_PAD_SD2_DATA0__SD2_DATA0,
	MX51_PAD_SD2_DATA1__SD2_DATA1,
	MX51_PAD_SD2_DATA2__SD2_DATA2,
	MX51_PAD_SD2_DATA3__SD2_DATA3,

	/* SD/MMC WP/CD */
	MX51_PAD_GPIO_1_0__ESDHC1_CD,
	MX51_PAD_GPIO_1_1__ESDHC1_WP,
	MX51_PAD_GPIO_1_7__ESDHC2_WP,
	MX51_PAD_GPIO_1_8__ESDHC2_CD,

	/* leds */
	MX51_PAD_CSI1_D9__GPIO_3_13,
	MX51_PAD_CSI1_VSYNC__GPIO_3_14,
	MX51_PAD_CSI1_HSYNC__GPIO_3_15,
};

/* Serial ports */
#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
static const struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static inline void mxc_init_imx_uart(void)
{
	imx51_add_imx_uart(0, &uart_pdata);
	imx51_add_imx_uart(1, &uart_pdata);
	imx51_add_imx_uart(2, &uart_pdata);
}
#else /* !SERIAL_IMX */
static inline void mxc_init_imx_uart(void)
{
}
#endif /* SERIAL_IMX */

/* This function is board specific as the bit mask for the plldiv will also
 * be different for other Freescale SoCs, thus a common bitmask is not
 * possible and cannot get place in /plat-mxc/ehci.c.
 */
static int initialize_otg_port(struct platform_device *pdev)
{
	u32 v;
	void __iomem *usb_base;
	void __iomem *usbother_base;
	usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
	usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);

	/* Set the PHY clock to 19.2MHz */
	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	v |= MX51_USB_PLL_DIV_24_MHZ;
	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	iounmap(usb_base);
	return 0;
}

static struct mxc_usbh_platform_data dr_utmi_config = {
	.init   = initialize_otg_port,
	.portsc = MXC_EHCI_UTMI_16BIT,
	.flags  = MXC_EHCI_INTERNAL_PHY,
};

/*   PCBID2  PCBID1 PCBID0  STATE
	1       1      1    ER1:rev1.1
	1       1      0    ER2:rev1.2
	1       0      1    ER3:rev1.3
	1       0      0    ER4:rev1.4
*/
static void __init mx51_efikamx_board_id(void)
{
	int id;

	/* things are taking time to settle */
	msleep(150);

	gpio_request(EFIKAMX_PCBID0, "pcbid0");
	gpio_direction_input(EFIKAMX_PCBID0);
	gpio_request(EFIKAMX_PCBID1, "pcbid1");
	gpio_direction_input(EFIKAMX_PCBID1);
	gpio_request(EFIKAMX_PCBID2, "pcbid2");
	gpio_direction_input(EFIKAMX_PCBID2);

	id = gpio_get_value(EFIKAMX_PCBID0);
	id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
	id |= gpio_get_value(EFIKAMX_PCBID2) << 2;

	switch (id) {
	case 7:
		system_rev = 0x11;
		break;
	case 6:
		system_rev = 0x12;
		break;
	case 5:
		system_rev = 0x13;
		break;
	case 4:
		system_rev = 0x14;
		break;
	default:
		system_rev = 0x10;
		break;
	}

	if ((system_rev == 0x10)
		|| (system_rev == 0x12)
		|| (system_rev == 0x14)) {
		printk(KERN_WARNING
			"EfikaMX: Unsupported board revision 1.%u!\n",
			system_rev & 0xf);
	}
}

static struct gpio_led mx51_efikamx_leds[] = {
	{
		.name = "efikamx:green",
		.default_trigger = "default-on",
		.gpio = EFIKAMX_GREEN_LED,
	},
	{
		.name = "efikamx:red",
		.default_trigger = "ide-disk",
		.gpio = EFIKAMX_RED_LED,
	},
	{
		.name = "efikamx:blue",
		.default_trigger = "mmc0",
		.gpio = EFIKAMX_BLUE_LED,
	},
};

static struct gpio_led_platform_data mx51_efikamx_leds_data = {
	.leds = mx51_efikamx_leds,
	.num_leds = ARRAY_SIZE(mx51_efikamx_leds),
};

static struct platform_device mx51_efikamx_leds_device = {
	.name = "leds-gpio",
	.id = -1,
	.dev = {
		.platform_data = &mx51_efikamx_leds_data,
	},
};

static void __init mxc_board_init(void)
{
	mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
					ARRAY_SIZE(mx51efikamx_pads));
	mx51_efikamx_board_id();
	mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
	mxc_init_imx_uart();
	imx51_add_esdhc(0, NULL);

	/* on < 1.2 boards both SD controllers are used */
	if (system_rev < 0x12) {
		imx51_add_esdhc(1, NULL);
		mx51_efikamx_leds[2].default_trigger = "mmc1";
	}

	platform_device_register(&mx51_efikamx_leds_device);
}

static void __init mx51_efikamx_timer_init(void)
{
	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
}

static struct sys_timer mxc_timer = {
	.init	= mx51_efikamx_timer_init,
};

MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
	/* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
	.boot_params = MX51_PHYS_OFFSET + 0x100,
	.map_io = mx51_map_io,
	.init_irq = mx51_init_irq,
	.init_machine =  mxc_board_init,
	.timer = &mxc_timer,
MACHINE_END
Commit	Line	Data
088d01b0 AK	1	/*
	2	* Copyright (C) 2010 Linaro Limited
	3	*
	4	* based on code from the following
	5	* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
	6	* Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
	7	* Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
	8	*
	9	* The code contained herein is licensed under the GNU General Public
	10	* License. You may obtain a copy of the GNU General Public License
	11	* Version 2 or later at the following locations:
	12	*
	13	* http://www.opensource.org/licenses/gpl-license.html
	14	* http://www.gnu.org/copyleft/gpl.html
	15	*/
	16
	17	#include <linux/init.h>
	18	#include <linux/platform_device.h>
	19	#include <linux/i2c.h>
	20	#include <linux/gpio.h>
9d2c0ef7	21	#include <linux/leds.h>
088d01b0 AK	22	#include <linux/delay.h>
	23	#include <linux/io.h>
	24	#include <linux/fsl_devices.h>
	25
	26	#include <mach/common.h>
	27	#include <mach/hardware.h>
	28	#include <mach/iomux-mx51.h>
	29	#include <mach/i2c.h>
	30	#include <mach/mxc_ehci.h>
	31
	32	#include <asm/irq.h>
	33	#include <asm/setup.h>
	34	#include <asm/mach-types.h>
	35	#include <asm/mach/arch.h>
	36	#include <asm/mach/time.h>
	37
	38	#include "devices-imx51.h"
	39	#include "devices.h"
	40
81490fcd AK	41	#define MX51_USB_PLL_DIV_24_MHZ 0x01
81490fcd AK	42
f1dd361b APR	43	#define EFIKAMX_PCBID0 (2*32 + 16)
	44	#define EFIKAMX_PCBID1 (2*32 + 17)
	45	#define EFIKAMX_PCBID2 (2*32 + 11)
	46
9d2c0ef7 APR	47	#define EFIKAMX_BLUE_LED (2*32 + 13)
	48	#define EFIKAMX_GREEN_LED (2*32 + 14)
	49	#define EFIKAMX_RED_LED (2*32 + 15)
	50
f1dd361b APR	51	/* the pci ids pin have pull up. they're driven low according to board id */
	52	#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
	53	#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
	54	#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
	55
8f5260c8	56	static iomux_v3_cfg_t mx51efikamx_pads[] = {
088d01b0 AK	57	/* UART1 */
	58	MX51_PAD_UART1_RXD__UART1_RXD,
	59	MX51_PAD_UART1_TXD__UART1_TXD,
	60	MX51_PAD_UART1_RTS__UART1_RTS,
	61	MX51_PAD_UART1_CTS__UART1_CTS,
f1dd361b APR	62	/* board id */
	63	MX51_PAD_PCBID0,
	64	MX51_PAD_PCBID1,
	65	MX51_PAD_PCBID2,
a96eb148 APR	66
	67	/* SD 1 */
	68	MX51_PAD_SD1_CMD__SD1_CMD,
	69	MX51_PAD_SD1_CLK__SD1_CLK,
	70	MX51_PAD_SD1_DATA0__SD1_DATA0,
	71	MX51_PAD_SD1_DATA1__SD1_DATA1,
	72	MX51_PAD_SD1_DATA2__SD1_DATA2,
	73	MX51_PAD_SD1_DATA3__SD1_DATA3,
	74
	75	/* SD 2 */
	76	MX51_PAD_SD2_CMD__SD2_CMD,
	77	MX51_PAD_SD2_CLK__SD2_CLK,
	78	MX51_PAD_SD2_DATA0__SD2_DATA0,
	79	MX51_PAD_SD2_DATA1__SD2_DATA1,
	80	MX51_PAD_SD2_DATA2__SD2_DATA2,
	81	MX51_PAD_SD2_DATA3__SD2_DATA3,
	82
	83	/* SD/MMC WP/CD */
	84	MX51_PAD_GPIO_1_0__ESDHC1_CD,
	85	MX51_PAD_GPIO_1_1__ESDHC1_WP,
	86	MX51_PAD_GPIO_1_7__ESDHC2_WP,
	87	MX51_PAD_GPIO_1_8__ESDHC2_CD,
9d2c0ef7 APR	88
	89	/* leds */
	90	MX51_PAD_CSI1_D9__GPIO_3_13,
	91	MX51_PAD_CSI1_VSYNC__GPIO_3_14,
	92	MX51_PAD_CSI1_HSYNC__GPIO_3_15,
088d01b0 AK	93	};
	94
	95	/* Serial ports */
	96	#if defined(CONFIG_SERIAL_IMX) \|\| defined(CONFIG_SERIAL_IMX_MODULE)
	97	static const struct imxuart_platform_data uart_pdata = {
	98	.flags = IMXUART_HAVE_RTSCTS,
	99	};
	100
	101	static inline void mxc_init_imx_uart(void)
	102	{
	103	imx51_add_imx_uart(0, &uart_pdata);
	104	imx51_add_imx_uart(1, &uart_pdata);
	105	imx51_add_imx_uart(2, &uart_pdata);
	106	}
	107	#else /* !SERIAL_IMX */
	108	static inline void mxc_init_imx_uart(void)
	109	{
	110	}
	111	#endif /* SERIAL_IMX */
	112
81490fcd AK	113	/* This function is board specific as the bit mask for the plldiv will also
	114	* be different for other Freescale SoCs, thus a common bitmask is not
	115	* possible and cannot get place in /plat-mxc/ehci.c.
	116	*/
	117	static int initialize_otg_port(struct platform_device *pdev)
	118	{
	119	u32 v;
	120	void __iomem *usb_base;
	121	void __iomem *usbother_base;
	122	usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
	123	usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
	124
	125	/* Set the PHY clock to 19.2MHz */
	126	v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	127	v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
	128	v \|= MX51_USB_PLL_DIV_24_MHZ;
	129	__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
	130	iounmap(usb_base);
	131	return 0;
	132	}
	133
	134	static struct mxc_usbh_platform_data dr_utmi_config = {
	135	.init = initialize_otg_port,
	136	.portsc = MXC_EHCI_UTMI_16BIT,
	137	.flags = MXC_EHCI_INTERNAL_PHY,
	138	};
	139
f1dd361b APR	140	/* PCBID2 PCBID1 PCBID0 STATE
	141	1 1 1 ER1:rev1.1
	142	1 1 0 ER2:rev1.2
	143	1 0 1 ER3:rev1.3
	144	1 0 0 ER4:rev1.4
	145	*/
	146	static void __init mx51_efikamx_board_id(void)
	147	{
	148	int id;
	149
	150	/* things are taking time to settle */
	151	msleep(150);
	152
	153	gpio_request(EFIKAMX_PCBID0, "pcbid0");
	154	gpio_direction_input(EFIKAMX_PCBID0);
	155	gpio_request(EFIKAMX_PCBID1, "pcbid1");
	156	gpio_direction_input(EFIKAMX_PCBID1);
	157	gpio_request(EFIKAMX_PCBID2, "pcbid2");
	158	gpio_direction_input(EFIKAMX_PCBID2);
	159
	160	id = gpio_get_value(EFIKAMX_PCBID0);
	161	id \|= gpio_get_value(EFIKAMX_PCBID1) << 1;
	162	id \|= gpio_get_value(EFIKAMX_PCBID2) << 2;
	163
	164	switch (id) {
	165	case 7:
	166	system_rev = 0x11;
	167	break;
	168	case 6:
	169	system_rev = 0x12;
	170	break;
	171	case 5:
	172	system_rev = 0x13;
	173	break;
	174	case 4:
	175	system_rev = 0x14;
	176	break;
	177	default:
	178	system_rev = 0x10;
	179	break;
	180	}
	181
	182	if ((system_rev == 0x10)
	183	\|\| (system_rev == 0x12)
	184	\|\| (system_rev == 0x14)) {
	185	printk(KERN_WARNING
	186	"EfikaMX: Unsupported board revision 1.%u!\n",
	187	system_rev & 0xf);
	188	}
	189	}
	190
9d2c0ef7 APR	191	static struct gpio_led mx51_efikamx_leds[] = {
	192	{
	193	.name = "efikamx:green",
	194	.default_trigger = "default-on",
	195	.gpio = EFIKAMX_GREEN_LED,
	196	},
	197	{
	198	.name = "efikamx:red",
	199	.default_trigger = "ide-disk",
	200	.gpio = EFIKAMX_RED_LED,
	201	},
	202	{
	203	.name = "efikamx:blue",
	204	.default_trigger = "mmc0",
	205	.gpio = EFIKAMX_BLUE_LED,
	206	},
	207	};
	208
	209	static struct gpio_led_platform_data mx51_efikamx_leds_data = {
	210	.leds = mx51_efikamx_leds,
	211	.num_leds = ARRAY_SIZE(mx51_efikamx_leds),
	212	};
	213
	214	static struct platform_device mx51_efikamx_leds_device = {
	215	.name = "leds-gpio",
	216	.id = -1,
	217	.dev = {
	218	.platform_data = &mx51_efikamx_leds_data,
	219	},
	220	};
	221
088d01b0 AK	222	static void __init mxc_board_init(void)
	223	{
	224	mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
	225	ARRAY_SIZE(mx51efikamx_pads));
f1dd361b	226	mx51_efikamx_board_id();
81490fcd	227	mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
088d01b0	228	mxc_init_imx_uart();
a96eb148 APR	229	imx51_add_esdhc(0, NULL);
	230
	231	/* on < 1.2 boards both SD controllers are used */
9d2c0ef7	232	if (system_rev < 0x12) {
a96eb148	233	imx51_add_esdhc(1, NULL);
9d2c0ef7 APR	234	mx51_efikamx_leds[2].default_trigger = "mmc1";
	235	}
	236
	237	platform_device_register(&mx51_efikamx_leds_device);
088d01b0 AK	238	}
	239
	240	static void __init mx51_efikamx_timer_init(void)
	241	{
	242	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
	243	}
	244
	245	static struct sys_timer mxc_timer = {
	246	.init = mx51_efikamx_timer_init,
	247	};
	248
	249	MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
	250	/* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
088d01b0 AK	251	.boot_params = MX51_PHYS_OFFSET + 0x100,
	252	.map_io = mx51_map_io,
	253	.init_irq = mx51_init_irq,
	254	.init_machine = mxc_board_init,
	255	.timer = &mxc_timer,
	256	MACHINE_END