ARM: imx53: correct Silicon Revision definition following fuse map
[deliverable/linux.git] / arch / arm / mach-mx5 / cpu.c
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a329b48c 1/*
b66ff7a2 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * This file contains the CPU initialization code.
12 */
13
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
5443856c 17#include <linux/module.h>
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18#include <mach/hardware.h>
19#include <asm/io.h>
20
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21static int cpu_silicon_rev = -1;
22
9ab4650f 23#define IIM_SREV 0x24
5443856c 24
9ab4650f 25static int get_mx51_srev(void)
5443856c 26{
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27 void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
28 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
5443856c 29
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30 if (rev == 0x0)
31 return IMX_CHIP_REVISION_2_0;
32 else if (rev == 0x10)
33 return IMX_CHIP_REVISION_3_0;
34 return 0;
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35}
36
37/*
38 * Returns:
39 * the silicon revision of the cpu
40 * -EINVAL - not a mx51
41 */
42int mx51_revision(void)
43{
44 if (!cpu_is_mx51())
45 return -EINVAL;
46
47 if (cpu_silicon_rev == -1)
9ab4650f 48 cpu_silicon_rev = get_mx51_srev();
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49
50 return cpu_silicon_rev;
51}
52EXPORT_SYMBOL(mx51_revision);
53
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54#ifdef CONFIG_NEON
55
56/*
57 * All versions of the silicon before Rev. 3 have broken NEON implementations.
58 * Dependent on link order - so the assumption is that vfp_init is called
59 * before us.
60 */
61static int __init mx51_neon_fixup(void)
62{
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63 if (!cpu_is_mx51())
64 return 0;
65
9ab4650f 66 if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
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67 elf_hwcap &= ~HWCAP_NEON;
68 pr_info("Turning off NEON support, detected broken NEON implementation\n");
69 }
70 return 0;
71}
72
73late_initcall(mx51_neon_fixup);
74#endif
75
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76static int get_mx53_srev(void)
77{
78 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
79 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
80
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81 switch (rev) {
82 case 0x0:
9ab4650f 83 return IMX_CHIP_REVISION_1_0;
503e1639 84 case 0x2:
9ab4650f 85 return IMX_CHIP_REVISION_2_0;
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86 case 0x3:
87 return IMX_CHIP_REVISION_2_1;
88 default:
89 return IMX_CHIP_REVISION_UNKNOWN;
90 }
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91}
92
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93/*
94 * Returns:
95 * the silicon revision of the cpu
96 * -EINVAL - not a mx53
97 */
98int mx53_revision(void)
99{
100 if (!cpu_is_mx53())
101 return -EINVAL;
102
103 if (cpu_silicon_rev == -1)
9ab4650f 104 cpu_silicon_rev = get_mx53_srev();
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105
106 return cpu_silicon_rev;
107}
108EXPORT_SYMBOL(mx53_revision);
109
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110static int __init post_cpu_init(void)
111{
112 unsigned int reg;
113 void __iomem *base;
114
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115 if (cpu_is_mx51() || cpu_is_mx53()) {
116 if (cpu_is_mx51())
117 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
118 else
119 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
120
121 __raw_writel(0x0, base + 0x40);
122 __raw_writel(0x0, base + 0x44);
123 __raw_writel(0x0, base + 0x48);
124 __raw_writel(0x0, base + 0x4C);
125 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
126 __raw_writel(reg, base + 0x50);
127
128 if (cpu_is_mx51())
129 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
130 else
131 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
132
133 __raw_writel(0x0, base + 0x40);
134 __raw_writel(0x0, base + 0x44);
135 __raw_writel(0x0, base + 0x48);
136 __raw_writel(0x0, base + 0x4C);
137 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
138 __raw_writel(reg, base + 0x50);
139 }
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140
141 return 0;
142}
143
144postcore_initcall(post_cpu_init);
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