projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a329b48c | 1 | /* |
| b66ff7a2 | 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| a329b48c AK |
3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | |
| 5 | * License. You may obtain a copy of the GNU General Public License | |
| 6 | * Version 2 or later at the following locations: | |
| 7 | * | |
| 8 | * http://www.opensource.org/licenses/gpl-license.html | |
| 9 | * http://www.gnu.org/copyleft/gpl.html | |
| 10 | * | |
| 11 | * This file contains the CPU initialization code. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <linux/types.h> | |
| 15 | #include <linux/kernel.h> | |
| 16 | #include <linux/init.h> | |
| 5443856c | 17 | #include <linux/module.h> |
| a329b48c AK |
18 | #include <mach/hardware.h> |
| 19 | #include <asm/io.h> | |
| 20 | ||
| 5443856c SH |
21 | static int cpu_silicon_rev = -1; |
| 22 | ||
| 9ab4650f | 23 | #define IIM_SREV 0x24 |
| 5443856c | 24 | |
| 9ab4650f | 25 | static int get_mx51_srev(void) |
| 5443856c | 26 | { |
| 9ab4650f DN |
27 | void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR); |
| 28 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | |
| 5443856c | 29 | |
| 9ab4650f DN |
30 | if (rev == 0x0) |
| 31 | return IMX_CHIP_REVISION_2_0; | |
| 32 | else if (rev == 0x10) | |
| 33 | return IMX_CHIP_REVISION_3_0; | |
| 34 | return 0; | |
| 5443856c SH |
35 | } |
| 36 | ||
| 37 | /* | |
| 38 | * Returns: | |
| 39 | * the silicon revision of the cpu | |
| 40 | * -EINVAL - not a mx51 | |
| 41 | */ | |
| 42 | int mx51_revision(void) | |
| 43 | { | |
| 44 | if (!cpu_is_mx51()) | |
| 45 | return -EINVAL; | |
| 46 | ||
| 47 | if (cpu_silicon_rev == -1) | |
| 9ab4650f | 48 | cpu_silicon_rev = get_mx51_srev(); |
| 5443856c SH |
49 | |
| 50 | return cpu_silicon_rev; | |
| 51 | } | |
| 52 | EXPORT_SYMBOL(mx51_revision); | |
| 53 | ||
| 33d7c5c1 AK |
54 | #ifdef CONFIG_NEON |
| 55 | ||
| 56 | /* | |
| 57 | * All versions of the silicon before Rev. 3 have broken NEON implementations. | |
| 58 | * Dependent on link order - so the assumption is that vfp_init is called | |
| 59 | * before us. | |
| 60 | */ | |
| 61 | static int __init mx51_neon_fixup(void) | |
| 62 | { | |
| 92fcdc9d SH |
63 | if (!cpu_is_mx51()) |
| 64 | return 0; | |
| 65 | ||
| 9ab4650f | 66 | if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) { |
| 33d7c5c1 AK |
67 | elf_hwcap &= ~HWCAP_NEON; |
| 68 | pr_info("Turning off NEON support, detected broken NEON implementation\n"); | |
| 69 | } | |
| 70 | return 0; | |
| 71 | } | |
| 72 | ||
| 73 | late_initcall(mx51_neon_fixup); | |
| 74 | #endif | |
| 75 | ||
| 9ab4650f DN |
76 | static int get_mx53_srev(void) |
| 77 | { | |
| 78 | void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); | |
| 79 | u32 rev = readl(iim_base + IIM_SREV) & 0xff; | |
| 80 | ||
| 81 | if (rev == 0x0) | |
| 82 | return IMX_CHIP_REVISION_1_0; | |
| 83 | else if (rev == 0x10) | |
| 84 | return IMX_CHIP_REVISION_2_0; | |
| 85 | return 0; | |
| 86 | } | |
| 87 | ||
| b66ff7a2 DN |
88 | /* |
| 89 | * Returns: | |
| 90 | * the silicon revision of the cpu | |
| 91 | * -EINVAL - not a mx53 | |
| 92 | */ | |
| 93 | int mx53_revision(void) | |
| 94 | { | |
| 95 | if (!cpu_is_mx53()) | |
| 96 | return -EINVAL; | |
| 97 | ||
| 98 | if (cpu_silicon_rev == -1) | |
| 9ab4650f | 99 | cpu_silicon_rev = get_mx53_srev(); |
| b66ff7a2 DN |
100 | |
| 101 | return cpu_silicon_rev; | |
| 102 | } | |
| 103 | EXPORT_SYMBOL(mx53_revision); | |
| 104 | ||
| a329b48c AK |
105 | static int __init post_cpu_init(void) |
| 106 | { | |
| 107 | unsigned int reg; | |
| 108 | void __iomem *base; | |
| 109 | ||
| c0abefd3 DN |
110 | if (cpu_is_mx51() || cpu_is_mx53()) { |
| 111 | if (cpu_is_mx51()) | |
| 112 | base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); | |
| 113 | else | |
| 114 | base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR); | |
| 115 | ||
| 116 | __raw_writel(0x0, base + 0x40); | |
| 117 | __raw_writel(0x0, base + 0x44); | |
| 118 | __raw_writel(0x0, base + 0x48); | |
| 119 | __raw_writel(0x0, base + 0x4C); | |
| 120 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | |
| 121 | __raw_writel(reg, base + 0x50); | |
| 122 | ||
| 123 | if (cpu_is_mx51()) | |
| 124 | base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); | |
| 125 | else | |
| 126 | base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR); | |
| 127 | ||
| 128 | __raw_writel(0x0, base + 0x40); | |
| 129 | __raw_writel(0x0, base + 0x44); | |
| 130 | __raw_writel(0x0, base + 0x48); | |
| 131 | __raw_writel(0x0, base + 0x4C); | |
| 132 | reg = __raw_readl(base + 0x50) & 0x00FFFFFF; | |
| 133 | __raw_writel(reg, base + 0x50); | |
| 134 | } | |
| a329b48c AK |
135 | |
| 136 | return 0; | |
| 137 | } | |
| 138 | ||
| 139 | postcore_initcall(post_cpu_init); |