[deliverable/linux.git] / arch / arm / mach-mx5 / cpu.c

/*
 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 *
 * This file contains the CPU initialization code.
 */

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <mach/hardware.h>
#include <asm/io.h>

static int cpu_silicon_rev = -1;

#define SI_REV 0x48

static void query_silicon_parameter(void)
{
	void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
	u32 rev;

	if (!rom) {
		cpu_silicon_rev = -EINVAL;
		return;
	}

	rev = readl(rom + SI_REV);
	switch (rev) {
	case 0x1:
		cpu_silicon_rev = MX51_CHIP_REV_1_0;
		break;
	case 0x2:
		cpu_silicon_rev = MX51_CHIP_REV_1_1;
		break;
	case 0x10:
		cpu_silicon_rev = MX51_CHIP_REV_2_0;
		break;
	case 0x20:
		cpu_silicon_rev = MX51_CHIP_REV_3_0;
		break;
	default:
		cpu_silicon_rev = 0;
	}

	iounmap(rom);
}

/*
 * Returns:
 *	the silicon revision of the cpu
 *	-EINVAL - not a mx51
 */
int mx51_revision(void)
{
	if (!cpu_is_mx51())
		return -EINVAL;

	if (cpu_silicon_rev == -1)
		query_silicon_parameter();

	return cpu_silicon_rev;
}
EXPORT_SYMBOL(mx51_revision);

#ifdef CONFIG_NEON

/*
 * All versions of the silicon before Rev. 3 have broken NEON implementations.
 * Dependent on link order - so the assumption is that vfp_init is called
 * before us.
 */
static int __init mx51_neon_fixup(void)
{
	if (!cpu_is_mx51())
		return 0;

	if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
		elf_hwcap &= ~HWCAP_NEON;
		pr_info("Turning off NEON support, detected broken NEON implementation\n");
	}
	return 0;
}

late_initcall(mx51_neon_fixup);
#endif

static int __init post_cpu_init(void)
{
	unsigned int reg;
	void __iomem *base;

	if (cpu_is_mx51() || cpu_is_mx53()) {
		if (cpu_is_mx51())
			base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
		else
			base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);

		__raw_writel(0x0, base + 0x40);
		__raw_writel(0x0, base + 0x44);
		__raw_writel(0x0, base + 0x48);
		__raw_writel(0x0, base + 0x4C);
		reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
		__raw_writel(reg, base + 0x50);

		if (cpu_is_mx51())
			base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
		else
			base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);

		__raw_writel(0x0, base + 0x40);
		__raw_writel(0x0, base + 0x44);
		__raw_writel(0x0, base + 0x48);
		__raw_writel(0x0, base + 0x4C);
		reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
		__raw_writel(reg, base + 0x50);
	}

	return 0;
}

postcore_initcall(post_cpu_init);
Commit	Line	Data
a329b48c AK	1	/*
	2	* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*
	11	* This file contains the CPU initialization code.
	12	*/
	13
	14	#include <linux/types.h>
	15	#include <linux/kernel.h>
	16	#include <linux/init.h>
5443856c	17	#include <linux/module.h>
a329b48c AK	18	#include <mach/hardware.h>
	19	#include <asm/io.h>
	20
5443856c SH	21	static int cpu_silicon_rev = -1;
	22
	23	#define SI_REV 0x48
	24
	25	static void query_silicon_parameter(void)
	26	{
	27	void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
	28	u32 rev;
	29
	30	if (!rom) {
	31	cpu_silicon_rev = -EINVAL;
	32	return;
	33	}
	34
	35	rev = readl(rom + SI_REV);
	36	switch (rev) {
	37	case 0x1:
	38	cpu_silicon_rev = MX51_CHIP_REV_1_0;
	39	break;
	40	case 0x2:
	41	cpu_silicon_rev = MX51_CHIP_REV_1_1;
	42	break;
	43	case 0x10:
	44	cpu_silicon_rev = MX51_CHIP_REV_2_0;
	45	break;
	46	case 0x20:
	47	cpu_silicon_rev = MX51_CHIP_REV_3_0;
	48	break;
	49	default:
	50	cpu_silicon_rev = 0;
	51	}
	52
	53	iounmap(rom);
	54	}
	55
	56	/*
	57	* Returns:
	58	* the silicon revision of the cpu
	59	* -EINVAL - not a mx51
	60	*/
	61	int mx51_revision(void)
	62	{
	63	if (!cpu_is_mx51())
	64	return -EINVAL;
	65
	66	if (cpu_silicon_rev == -1)
	67	query_silicon_parameter();
	68
	69	return cpu_silicon_rev;
	70	}
	71	EXPORT_SYMBOL(mx51_revision);
	72
33d7c5c1 AK	73	#ifdef CONFIG_NEON
	74
	75	/*
	76	* All versions of the silicon before Rev. 3 have broken NEON implementations.
	77	* Dependent on link order - so the assumption is that vfp_init is called
	78	* before us.
	79	*/
	80	static int __init mx51_neon_fixup(void)
	81	{
92fcdc9d SH	82	if (!cpu_is_mx51())
	83	return 0;
	84
33d7c5c1 AK	85	if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
	86	elf_hwcap &= ~HWCAP_NEON;
	87	pr_info("Turning off NEON support, detected broken NEON implementation\n");
	88	}
	89	return 0;
	90	}
	91
	92	late_initcall(mx51_neon_fixup);
	93	#endif
	94
a329b48c AK	95	static int __init post_cpu_init(void)
	96	{
	97	unsigned int reg;
	98	void __iomem *base;
	99
c0abefd3 DN	100	if (cpu_is_mx51() \|\| cpu_is_mx53()) {
	101	if (cpu_is_mx51())
	102	base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
	103	else
	104	base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
	105
	106	__raw_writel(0x0, base + 0x40);
	107	__raw_writel(0x0, base + 0x44);
	108	__raw_writel(0x0, base + 0x48);
	109	__raw_writel(0x0, base + 0x4C);
	110	reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
	111	__raw_writel(reg, base + 0x50);
	112
	113	if (cpu_is_mx51())
	114	base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
	115	else
	116	base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
	117
	118	__raw_writel(0x0, base + 0x40);
	119	__raw_writel(0x0, base + 0x44);
	120	__raw_writel(0x0, base + 0x48);
	121	__raw_writel(0x0, base + 0x4C);
	122	reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
	123	__raw_writel(reg, base + 0x50);
	124	}
a329b48c AK	125
	126	return 0;
	127	}
	128
	129	postcore_initcall(post_cpu_init);