[deliverable/linux.git] / arch / arm / mach-mx5 / mm.c

/*
 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License.  You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 *
 * Create static mapping between physical to virtual memory.
 */

#include <linux/mm.h>
#include <linux/init.h>

#include <asm/mach/map.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/iomux-v3.h>

/*
 * Define the MX51 memory map.
 */
static struct map_desc mx51_io_desc[] __initdata = {
	imx_map_entry(MX51, IRAM, MT_DEVICE),
	imx_map_entry(MX51, DEBUG, MT_DEVICE),
	imx_map_entry(MX51, AIPS1, MT_DEVICE),
	imx_map_entry(MX51, SPBA0, MT_DEVICE),
	imx_map_entry(MX51, AIPS2, MT_DEVICE),
};

/*
 * Define the MX53 memory map.
 */
static struct map_desc mx53_io_desc[] __initdata = {
	imx_map_entry(MX53, AIPS1, MT_DEVICE),
	imx_map_entry(MX53, SPBA0, MT_DEVICE),
	imx_map_entry(MX53, AIPS2, MT_DEVICE),
};

/*
 * This function initializes the memory map. It is called during the
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
 */
void __init mx51_map_io(void)
{
	iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
}

void __init imx51_init_early(void)
{
	mxc_set_cpu_type(MXC_CPU_MX51);
	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
}

void __init mx53_map_io(void)
{
	iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
}

void __init imx53_init_early(void)
{
	mxc_set_cpu_type(MXC_CPU_MX53);
	mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
}

void __init mx51_init_irq(void)
{
	unsigned long tzic_addr;
	void __iomem *tzic_virt;

	if (mx51_revision() < IMX_CHIP_REVISION_2_0)
		tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
	else
		tzic_addr = MX51_TZIC_BASE_ADDR;

	tzic_virt = ioremap(tzic_addr, SZ_16K);
	if (!tzic_virt)
		panic("unable to map TZIC interrupt controller\n");

	tzic_init_irq(tzic_virt);
}

void __init mx53_init_irq(void)
{
	unsigned long tzic_addr;
	void __iomem *tzic_virt;

	tzic_addr = MX53_TZIC_BASE_ADDR;

	tzic_virt = ioremap(tzic_addr, SZ_16K);
	if (!tzic_virt)
		panic("unable to map TZIC interrupt controller\n");

	tzic_init_irq(tzic_virt);
}

static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
	.ap_2_ap_addr = 642,
	.uart_2_mcu_addr = 817,
	.mcu_2_app_addr = 747,
	.mcu_2_shp_addr = 961,
	.ata_2_mcu_addr = 1473,
	.mcu_2_ata_addr = 1392,
	.app_2_per_addr = 1033,
	.app_2_mcu_addr = 683,
	.shp_2_per_addr = 1251,
	.shp_2_mcu_addr = 892,
};

static struct sdma_platform_data imx51_sdma_pdata __initdata = {
	.sdma_version = 2,
	.cpu_name = "imx51",
	.to_version = 1,
	.script_addrs = &imx51_sdma_script,
};

static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
	.ap_2_ap_addr = 642,
	.app_2_mcu_addr = 683,
	.mcu_2_app_addr = 747,
	.uart_2_mcu_addr = 817,
	.shp_2_mcu_addr = 891,
	.mcu_2_shp_addr = 960,
	.uartsh_2_mcu_addr = 1032,
	.spdif_2_mcu_addr = 1100,
	.mcu_2_spdif_addr = 1134,
	.firi_2_mcu_addr = 1193,
	.mcu_2_firi_addr = 1290,
};

static struct sdma_platform_data imx53_sdma_pdata __initdata = {
	.sdma_version = 2,
	.cpu_name = "imx53",
	.to_version = 1,
	.script_addrs = &imx53_sdma_script,
};

void __init imx51_soc_init(void)
{
	int to_version = mx51_revision() >> 4;

	mxc_register_gpio(0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
	mxc_register_gpio(1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
	mxc_register_gpio(2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
	mxc_register_gpio(3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);

	imx51_sdma_pdata.to_version = to_version;
	imx_add_imx_sdma(MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
}

void __init imx53_soc_init(void)
{
	mxc_register_gpio(0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
	mxc_register_gpio(1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
	mxc_register_gpio(2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
	mxc_register_gpio(3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
	mxc_register_gpio(4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
	mxc_register_gpio(5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
	mxc_register_gpio(6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);

	imx_add_imx_sdma(MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
}
Commit	Line	Data
a329b48c	1	/*
b66ff7a2	2	* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
a329b48c AK	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*
	11	* Create static mapping between physical to virtual memory.
	12	*/
	13
	14	#include <linux/mm.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/mach/map.h>
	18
	19	#include <mach/hardware.h>
	20	#include <mach/common.h>
36223604	21	#include <mach/devices-common.h>
a329b48c AK	22	#include <mach/iomux-v3.h>
	23
	24	/*
	25	* Define the MX51 memory map.
	26	*/
08ff97b5 UKK	27	static struct map_desc mx51_io_desc[] __initdata = {
	28	imx_map_entry(MX51, IRAM, MT_DEVICE),
	29	imx_map_entry(MX51, DEBUG, MT_DEVICE),
	30	imx_map_entry(MX51, AIPS1, MT_DEVICE),
	31	imx_map_entry(MX51, SPBA0, MT_DEVICE),
	32	imx_map_entry(MX51, AIPS2, MT_DEVICE),
a329b48c AK	33	};
a329b48c AK	34
b66ff7a2 DN	35	/*
	36	* Define the MX53 memory map.
	37	*/
	38	static struct map_desc mx53_io_desc[] __initdata = {
	39	imx_map_entry(MX53, AIPS1, MT_DEVICE),
	40	imx_map_entry(MX53, SPBA0, MT_DEVICE),
	41	imx_map_entry(MX53, AIPS2, MT_DEVICE),
	42	};
	43
a329b48c AK	44	/*
	45	* This function initializes the memory map. It is called during the
	46	* system startup to create static physical to virtual memory mappings
	47	* for the IO modules.
	48	*/
	49	void __init mx51_map_io(void)
ab130421 UKK	50	{
	51	iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
	52	}
	53
	54	void __init imx51_init_early(void)
a329b48c	55	{
a329b48c AK	56	mxc_set_cpu_type(MXC_CPU_MX51);
a329b48c AK	57	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
8c2efec3	58	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
a329b48c AK	59	}
a329b48c AK	60
b66ff7a2	61	void __init mx53_map_io(void)
ab130421 UKK	62	{
	63	iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
	64	}
	65
	66	void __init imx53_init_early(void)
b66ff7a2 DN	67	{
	68	mxc_set_cpu_type(MXC_CPU_MX53);
	69	mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
78c73591	70	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
b66ff7a2 DN	71	}
b66ff7a2 DN	72
a329b48c AK	73	void __init mx51_init_irq(void)
a329b48c AK	74	{
3d1bc862 SH	75	unsigned long tzic_addr;
	76	void __iomem *tzic_virt;
	77
9ab4650f	78	if (mx51_revision() < IMX_CHIP_REVISION_2_0)
3d1bc862 SH	79	tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
	80	else
	81	tzic_addr = MX51_TZIC_BASE_ADDR;
	82
	83	tzic_virt = ioremap(tzic_addr, SZ_16K);
	84	if (!tzic_virt)
	85	panic("unable to map TZIC interrupt controller\n");
	86
	87	tzic_init_irq(tzic_virt);
a329b48c	88	}
c0abefd3	89
c0abefd3 DN	90	void __init mx53_init_irq(void)
	91	{
	92	unsigned long tzic_addr;
	93	void __iomem *tzic_virt;
	94
	95	tzic_addr = MX53_TZIC_BASE_ADDR;
	96
	97	tzic_virt = ioremap(tzic_addr, SZ_16K);
	98	if (!tzic_virt)
	99	panic("unable to map TZIC interrupt controller\n");
	100
	101	tzic_init_irq(tzic_virt);
b78d8e59 SG	102	}
b78d8e59 SG	103
36223604 SG	104	static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
	105	.ap_2_ap_addr = 642,
	106	.uart_2_mcu_addr = 817,
	107	.mcu_2_app_addr = 747,
	108	.mcu_2_shp_addr = 961,
	109	.ata_2_mcu_addr = 1473,
	110	.mcu_2_ata_addr = 1392,
	111	.app_2_per_addr = 1033,
	112	.app_2_mcu_addr = 683,
	113	.shp_2_per_addr = 1251,
	114	.shp_2_mcu_addr = 892,
	115	};
	116
	117	static struct sdma_platform_data imx51_sdma_pdata __initdata = {
	118	.sdma_version = 2,
	119	.cpu_name = "imx51",
	120	.to_version = 1,
	121	.script_addrs = &imx51_sdma_script,
	122	};
	123
	124	static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
	125	.ap_2_ap_addr = 642,
	126	.app_2_mcu_addr = 683,
	127	.mcu_2_app_addr = 747,
	128	.uart_2_mcu_addr = 817,
	129	.shp_2_mcu_addr = 891,
	130	.mcu_2_shp_addr = 960,
	131	.uartsh_2_mcu_addr = 1032,
	132	.spdif_2_mcu_addr = 1100,
	133	.mcu_2_spdif_addr = 1134,
	134	.firi_2_mcu_addr = 1193,
	135	.mcu_2_firi_addr = 1290,
	136	};
	137
	138	static struct sdma_platform_data imx53_sdma_pdata __initdata = {
	139	.sdma_version = 2,
	140	.cpu_name = "imx53",
	141	.to_version = 1,
	142	.script_addrs = &imx53_sdma_script,
	143	};
	144
b78d8e59 SG	145	void __init imx51_soc_init(void)
b78d8e59 SG	146	{
36223604 SG	147	int to_version = mx51_revision() >> 4;
36223604 SG	148
b78d8e59 SG	149	mxc_register_gpio(0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
	150	mxc_register_gpio(1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
	151	mxc_register_gpio(2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
	152	mxc_register_gpio(3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
36223604 SG	153
	154	imx51_sdma_pdata.to_version = to_version;
	155	imx_add_imx_sdma(MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
b78d8e59 SG	156	}
	157
	158	void __init imx53_soc_init(void)
	159	{
	160	mxc_register_gpio(0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
	161	mxc_register_gpio(1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
	162	mxc_register_gpio(2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
	163	mxc_register_gpio(3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
	164	mxc_register_gpio(4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
	165	mxc_register_gpio(5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
	166	mxc_register_gpio(6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
36223604 SG	167
36223604 SG	168	imx_add_imx_sdma(MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
c0abefd3	169	}