Commit | Line | Data |
---|---|---|
a329b48c | 1 | /* |
b66ff7a2 | 2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
a329b48c AK |
3 | * |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | * | |
11 | * Create static mapping between physical to virtual memory. | |
12 | */ | |
13 | ||
14 | #include <linux/mm.h> | |
15 | #include <linux/init.h> | |
16 | ||
17 | #include <asm/mach/map.h> | |
18 | ||
19 | #include <mach/hardware.h> | |
20 | #include <mach/common.h> | |
21 | #include <mach/iomux-v3.h> | |
22 | ||
23 | /* | |
24 | * Define the MX51 memory map. | |
25 | */ | |
08ff97b5 UKK |
26 | static struct map_desc mx51_io_desc[] __initdata = { |
27 | imx_map_entry(MX51, IRAM, MT_DEVICE), | |
28 | imx_map_entry(MX51, DEBUG, MT_DEVICE), | |
29 | imx_map_entry(MX51, AIPS1, MT_DEVICE), | |
30 | imx_map_entry(MX51, SPBA0, MT_DEVICE), | |
31 | imx_map_entry(MX51, AIPS2, MT_DEVICE), | |
a329b48c AK |
32 | }; |
33 | ||
b66ff7a2 DN |
34 | /* |
35 | * Define the MX53 memory map. | |
36 | */ | |
37 | static struct map_desc mx53_io_desc[] __initdata = { | |
38 | imx_map_entry(MX53, AIPS1, MT_DEVICE), | |
39 | imx_map_entry(MX53, SPBA0, MT_DEVICE), | |
40 | imx_map_entry(MX53, AIPS2, MT_DEVICE), | |
41 | }; | |
42 | ||
a329b48c AK |
43 | /* |
44 | * This function initializes the memory map. It is called during the | |
45 | * system startup to create static physical to virtual memory mappings | |
46 | * for the IO modules. | |
47 | */ | |
48 | void __init mx51_map_io(void) | |
ab130421 UKK |
49 | { |
50 | iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); | |
51 | } | |
52 | ||
53 | void __init imx51_init_early(void) | |
a329b48c | 54 | { |
a329b48c AK |
55 | mxc_set_cpu_type(MXC_CPU_MX51); |
56 | mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); | |
8c2efec3 | 57 | mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |
a329b48c AK |
58 | } |
59 | ||
b66ff7a2 | 60 | void __init mx53_map_io(void) |
ab130421 UKK |
61 | { |
62 | iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc)); | |
63 | } | |
64 | ||
65 | void __init imx53_init_early(void) | |
b66ff7a2 DN |
66 | { |
67 | mxc_set_cpu_type(MXC_CPU_MX53); | |
68 | mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); | |
78c73591 | 69 | mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR)); |
b66ff7a2 DN |
70 | } |
71 | ||
a329b48c AK |
72 | void __init mx51_init_irq(void) |
73 | { | |
3d1bc862 SH |
74 | unsigned long tzic_addr; |
75 | void __iomem *tzic_virt; | |
76 | ||
9ab4650f | 77 | if (mx51_revision() < IMX_CHIP_REVISION_2_0) |
3d1bc862 SH |
78 | tzic_addr = MX51_TZIC_BASE_ADDR_TO1; |
79 | else | |
80 | tzic_addr = MX51_TZIC_BASE_ADDR; | |
81 | ||
82 | tzic_virt = ioremap(tzic_addr, SZ_16K); | |
83 | if (!tzic_virt) | |
84 | panic("unable to map TZIC interrupt controller\n"); | |
85 | ||
86 | tzic_init_irq(tzic_virt); | |
a329b48c | 87 | } |
c0abefd3 | 88 | |
c0abefd3 DN |
89 | void __init mx53_init_irq(void) |
90 | { | |
91 | unsigned long tzic_addr; | |
92 | void __iomem *tzic_virt; | |
93 | ||
94 | tzic_addr = MX53_TZIC_BASE_ADDR; | |
95 | ||
96 | tzic_virt = ioremap(tzic_addr, SZ_16K); | |
97 | if (!tzic_virt) | |
98 | panic("unable to map TZIC interrupt controller\n"); | |
99 | ||
100 | tzic_init_irq(tzic_virt); | |
b78d8e59 SG |
101 | } |
102 | ||
103 | void __init imx51_soc_init(void) | |
104 | { | |
e7fc6ae7 SG |
105 | /* i.mx51 has the i.mx31 type gpio */ |
106 | mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH); | |
107 | mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH); | |
108 | mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH); | |
109 | mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH); | |
b78d8e59 SG |
110 | } |
111 | ||
112 | void __init imx53_soc_init(void) | |
113 | { | |
e7fc6ae7 SG |
114 | /* i.mx53 has the i.mx31 type gpio */ |
115 | mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH); | |
116 | mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH); | |
117 | mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH); | |
118 | mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH); | |
119 | mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH); | |
120 | mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH); | |
121 | mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH); | |
c0abefd3 | 122 | } |