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1 | /* |
2 | * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> | |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
5 | * Based on code from Freescale, | |
6 | * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version 2 | |
11 | * of the License, or (at your option) any later version. | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
20 | * MA 02110-1301, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <mach/mx23.h> | |
29 | #include <mach/mx28.h> | |
30 | #include <asm-generic/bug.h> | |
31 | ||
32 | #include "gpio.h" | |
33 | ||
34 | static struct mxs_gpio_port *mxs_gpio_ports; | |
35 | static int gpio_table_size; | |
36 | ||
37 | #define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10) | |
38 | #define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10) | |
39 | #define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10) | |
40 | #define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10) | |
41 | #define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10) | |
42 | #define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10) | |
43 | #define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10) | |
44 | #define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10) | |
45 | ||
46 | #define GPIO_INT_FALL_EDGE 0x0 | |
47 | #define GPIO_INT_LOW_LEV 0x1 | |
48 | #define GPIO_INT_RISE_EDGE 0x2 | |
49 | #define GPIO_INT_HIGH_LEV 0x3 | |
50 | #define GPIO_INT_LEV_MASK (1 << 0) | |
51 | #define GPIO_INT_POL_MASK (1 << 1) | |
52 | ||
53 | /* Note: This driver assumes 32 GPIOs are handled in one register */ | |
54 | ||
55 | static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index) | |
56 | { | |
57 | __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id)); | |
58 | } | |
59 | ||
60 | static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index, | |
61 | int enable) | |
62 | { | |
63 | if (enable) { | |
64 | __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id)); | |
65 | __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id)); | |
66 | } else { | |
67 | __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id)); | |
68 | } | |
69 | } | |
70 | ||
71 | static void mxs_gpio_ack_irq(u32 irq) | |
72 | { | |
73 | u32 gpio = irq_to_gpio(irq); | |
74 | clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f); | |
75 | } | |
76 | ||
77 | static void mxs_gpio_mask_irq(u32 irq) | |
78 | { | |
79 | u32 gpio = irq_to_gpio(irq); | |
80 | set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0); | |
81 | } | |
82 | ||
83 | static void mxs_gpio_unmask_irq(u32 irq) | |
84 | { | |
85 | u32 gpio = irq_to_gpio(irq); | |
86 | set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1); | |
87 | } | |
88 | ||
89 | static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset); | |
90 | ||
91 | static int mxs_gpio_set_irq_type(u32 irq, u32 type) | |
92 | { | |
93 | u32 gpio = irq_to_gpio(irq); | |
94 | u32 pin_mask = 1 << (gpio & 31); | |
95 | struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; | |
96 | void __iomem *pin_addr; | |
97 | int edge; | |
98 | ||
99 | switch (type) { | |
100 | case IRQ_TYPE_EDGE_RISING: | |
101 | edge = GPIO_INT_RISE_EDGE; | |
102 | break; | |
103 | case IRQ_TYPE_EDGE_FALLING: | |
104 | edge = GPIO_INT_FALL_EDGE; | |
105 | break; | |
106 | case IRQ_TYPE_LEVEL_LOW: | |
107 | edge = GPIO_INT_LOW_LEV; | |
108 | break; | |
109 | case IRQ_TYPE_LEVEL_HIGH: | |
110 | edge = GPIO_INT_HIGH_LEV; | |
111 | break; | |
112 | default: | |
113 | return -EINVAL; | |
114 | } | |
115 | ||
116 | /* set level or edge */ | |
117 | pin_addr = port->base + PINCTRL_IRQLEV(port->id); | |
118 | if (edge & GPIO_INT_LEV_MASK) | |
119 | __mxs_setl(pin_mask, pin_addr); | |
120 | else | |
121 | __mxs_clrl(pin_mask, pin_addr); | |
122 | ||
123 | /* set polarity */ | |
124 | pin_addr = port->base + PINCTRL_IRQPOL(port->id); | |
125 | if (edge & GPIO_INT_POL_MASK) | |
126 | __mxs_setl(pin_mask, pin_addr); | |
127 | else | |
128 | __mxs_clrl(pin_mask, pin_addr); | |
129 | ||
130 | clear_gpio_irqstatus(port, gpio & 0x1f); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | /* MXS has one interrupt *per* gpio port */ | |
136 | static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) | |
137 | { | |
138 | u32 irq_stat; | |
139 | struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); | |
140 | u32 gpio_irq_no_base = port->virtual_irq_start; | |
141 | ||
142 | irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) & | |
143 | __raw_readl(port->base + PINCTRL_IRQEN(port->id)); | |
144 | ||
145 | while (irq_stat != 0) { | |
146 | int irqoffset = fls(irq_stat) - 1; | |
147 | generic_handle_irq(gpio_irq_no_base + irqoffset); | |
148 | irq_stat &= ~(1 << irqoffset); | |
149 | } | |
150 | } | |
151 | ||
152 | /* | |
153 | * Set interrupt number "irq" in the GPIO as a wake-up source. | |
154 | * While system is running, all registered GPIO interrupts need to have | |
155 | * wake-up enabled. When system is suspended, only selected GPIO interrupts | |
156 | * need to have wake-up enabled. | |
157 | * @param irq interrupt source number | |
158 | * @param enable enable as wake-up if equal to non-zero | |
159 | * @return This function returns 0 on success. | |
160 | */ | |
161 | static int mxs_gpio_set_wake_irq(u32 irq, u32 enable) | |
162 | { | |
163 | u32 gpio = irq_to_gpio(irq); | |
164 | u32 gpio_idx = gpio & 0x1f; | |
165 | struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32]; | |
166 | ||
167 | if (enable) { | |
168 | if (port->irq_high && (gpio_idx >= 16)) | |
169 | enable_irq_wake(port->irq_high); | |
170 | else | |
171 | enable_irq_wake(port->irq); | |
172 | } else { | |
173 | if (port->irq_high && (gpio_idx >= 16)) | |
174 | disable_irq_wake(port->irq_high); | |
175 | else | |
176 | disable_irq_wake(port->irq); | |
177 | } | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
182 | static struct irq_chip gpio_irq_chip = { | |
183 | .ack = mxs_gpio_ack_irq, | |
184 | .mask = mxs_gpio_mask_irq, | |
185 | .unmask = mxs_gpio_unmask_irq, | |
186 | .set_type = mxs_gpio_set_irq_type, | |
187 | .set_wake = mxs_gpio_set_wake_irq, | |
188 | }; | |
189 | ||
190 | static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset, | |
191 | int dir) | |
192 | { | |
193 | struct mxs_gpio_port *port = | |
194 | container_of(chip, struct mxs_gpio_port, chip); | |
195 | void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id); | |
196 | ||
197 | if (dir) | |
198 | __mxs_setl(1 << offset, pin_addr); | |
199 | else | |
200 | __mxs_clrl(1 << offset, pin_addr); | |
201 | } | |
202 | ||
203 | static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset) | |
204 | { | |
205 | struct mxs_gpio_port *port = | |
206 | container_of(chip, struct mxs_gpio_port, chip); | |
207 | ||
208 | return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1; | |
209 | } | |
210 | ||
211 | static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
212 | { | |
213 | struct mxs_gpio_port *port = | |
214 | container_of(chip, struct mxs_gpio_port, chip); | |
215 | void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id); | |
216 | ||
217 | if (value) | |
218 | __mxs_setl(1 << offset, pin_addr); | |
219 | else | |
220 | __mxs_clrl(1 << offset, pin_addr); | |
221 | } | |
222 | ||
223 | static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |
224 | { | |
225 | struct mxs_gpio_port *port = | |
226 | container_of(chip, struct mxs_gpio_port, chip); | |
227 | ||
228 | return port->virtual_irq_start + offset; | |
229 | } | |
230 | ||
231 | static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
232 | { | |
233 | mxs_set_gpio_direction(chip, offset, 0); | |
234 | return 0; | |
235 | } | |
236 | ||
237 | static int mxs_gpio_direction_output(struct gpio_chip *chip, | |
238 | unsigned offset, int value) | |
239 | { | |
240 | mxs_gpio_set(chip, offset, value); | |
241 | mxs_set_gpio_direction(chip, offset, 1); | |
242 | return 0; | |
243 | } | |
244 | ||
245 | int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) | |
246 | { | |
247 | int i, j; | |
248 | ||
249 | /* save for local usage */ | |
250 | mxs_gpio_ports = port; | |
251 | gpio_table_size = cnt; | |
252 | ||
253 | pr_info("MXS GPIO hardware\n"); | |
254 | ||
255 | for (i = 0; i < cnt; i++) { | |
256 | /* disable the interrupt and clear the status */ | |
257 | __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i)); | |
258 | __raw_writel(0, port[i].base + PINCTRL_IRQEN(i)); | |
259 | ||
260 | /* clear address has to be used to clear IRQSTAT bits */ | |
261 | __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i)); | |
262 | ||
263 | for (j = port[i].virtual_irq_start; | |
264 | j < port[i].virtual_irq_start + 32; j++) { | |
265 | set_irq_chip(j, &gpio_irq_chip); | |
266 | set_irq_handler(j, handle_level_irq); | |
267 | set_irq_flags(j, IRQF_VALID); | |
268 | } | |
269 | ||
270 | /* setup one handler for each entry */ | |
271 | set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); | |
272 | set_irq_data(port[i].irq, &port[i]); | |
273 | ||
274 | /* register gpio chip */ | |
275 | port[i].chip.direction_input = mxs_gpio_direction_input; | |
276 | port[i].chip.direction_output = mxs_gpio_direction_output; | |
277 | port[i].chip.get = mxs_gpio_get; | |
278 | port[i].chip.set = mxs_gpio_set; | |
279 | port[i].chip.to_irq = mxs_gpio_to_irq; | |
280 | port[i].chip.base = i * 32; | |
281 | port[i].chip.ngpio = 32; | |
282 | ||
283 | /* its a serious configuration bug when it fails */ | |
284 | BUG_ON(gpiochip_add(&port[i].chip) < 0); | |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
290 | #define DEFINE_MXS_GPIO_PORT(soc, _id) \ | |
291 | { \ | |
292 | .chip.label = "gpio-" #_id, \ | |
293 | .id = _id, \ | |
294 | .irq = soc ## _INT_GPIO ## _id, \ | |
295 | .base = soc ## _IO_ADDRESS( \ | |
296 | soc ## _PINCTRL ## _BASE_ADDR), \ | |
297 | .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \ | |
298 | } | |
299 | ||
300 | #define DEFINE_REGISTER_FUNCTION(prefix) \ | |
301 | int __init prefix ## _register_gpios(void) \ | |
302 | { \ | |
303 | return mxs_gpio_init(prefix ## _gpio_ports, \ | |
304 | ARRAY_SIZE(prefix ## _gpio_ports)); \ | |
305 | } | |
306 | ||
307 | #ifdef CONFIG_SOC_IMX23 | |
308 | static struct mxs_gpio_port mx23_gpio_ports[] = { | |
309 | DEFINE_MXS_GPIO_PORT(MX23, 0), | |
310 | DEFINE_MXS_GPIO_PORT(MX23, 1), | |
311 | DEFINE_MXS_GPIO_PORT(MX23, 2), | |
312 | }; | |
313 | DEFINE_REGISTER_FUNCTION(mx23) | |
314 | #endif | |
315 | ||
316 | #ifdef CONFIG_SOC_IMX28 | |
317 | static struct mxs_gpio_port mx28_gpio_ports[] = { | |
318 | DEFINE_MXS_GPIO_PORT(MX28, 0), | |
319 | DEFINE_MXS_GPIO_PORT(MX28, 1), | |
320 | DEFINE_MXS_GPIO_PORT(MX28, 2), | |
321 | DEFINE_MXS_GPIO_PORT(MX28, 3), | |
322 | DEFINE_MXS_GPIO_PORT(MX28, 4), | |
323 | }; | |
324 | DEFINE_REGISTER_FUNCTION(mx28) | |
325 | #endif |