[deliverable/linux.git] / arch / arm / mach-mxs / timer.c

/*
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *  Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#include <asm/mach/time.h>
#include <asm/sched_clock.h>
#include <mach/mxs.h>
#include <mach/common.h>

/*
 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
 * extends the counter to 32 bits.
 *
 * The implementation uses two timers, one for clock_event and
 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
 * uses 0 and 2.
 */

#define MX23_TIMROT_VERSION_OFFSET	0x0a0
#define MX28_TIMROT_VERSION_OFFSET	0x120
#define BP_TIMROT_MAJOR_VERSION		24
#define BV_TIMROT_VERSION_1		0x01
#define BV_TIMROT_VERSION_2		0x02
#define timrot_is_v1()	(timrot_major_version == BV_TIMROT_VERSION_1)

/*
 * There are 4 registers for each timrotv2 instance, and 2 registers
 * for each timrotv1. So address step 0x40 in macros below strides
 * one instance of timrotv2 while two instances of timrotv1.
 *
 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
 * on MX28 while timrot2 on MX23.
 */
/* common between v1 and v2 */
#define HW_TIMROT_ROTCTRL		0x00
#define HW_TIMROT_TIMCTRLn(n)		(0x20 + (n) * 0x40)
/* v1 only */
#define HW_TIMROT_TIMCOUNTn(n)		(0x30 + (n) * 0x40)
/* v2 only */
#define HW_TIMROT_RUNNING_COUNTn(n)	(0x30 + (n) * 0x40)
#define HW_TIMROT_FIXED_COUNTn(n)	(0x40 + (n) * 0x40)

#define BM_TIMROT_TIMCTRLn_RELOAD	(1 << 6)
#define BM_TIMROT_TIMCTRLn_UPDATE	(1 << 7)
#define BM_TIMROT_TIMCTRLn_IRQ_EN	(1 << 14)
#define BM_TIMROT_TIMCTRLn_IRQ		(1 << 15)
#define BP_TIMROT_TIMCTRLn_SELECT	0
#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL		0x8
#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL		0xb
#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS	0xf

static struct clock_event_device mxs_clockevent_device;
static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;

static void __iomem *mxs_timrot_base;
static u32 timrot_major_version;

static inline void timrot_irq_disable(void)
{
	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
}

static inline void timrot_irq_enable(void)
{
	__mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
}

static void timrot_irq_acknowledge(void)
{
	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
}

static cycle_t timrotv1_get_cycles(struct clocksource *cs)
{
	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
			& 0xffff0000) >> 16);
}

static int timrotv1_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));

	return 0;
}

static int timrotv2_set_next_event(unsigned long evt,
					struct clock_event_device *dev)
{
	/* timrot decrements the count */
	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));

	return 0;
}

static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	timrot_irq_acknowledge();
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction mxs_timer_irq = {
	.name		= "MXS Timer Tick",
	.dev_id		= &mxs_clockevent_device,
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= mxs_timer_interrupt,
};

#ifdef DEBUG
static const char *clock_event_mode_label[] const = {
	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	[CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	[CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
};
#endif /* DEBUG */

static void mxs_set_mode(enum clock_event_mode mode,
				struct clock_event_device *evt)
{
	/* Disable interrupt in timer module */
	timrot_irq_disable();

	if (mode != mxs_clockevent_mode) {
		/* Set event time into the furthest future */
		if (timrot_is_v1())
			__raw_writel(0xffff,
				mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
		else
			__raw_writel(0xffffffff,
				mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

		/* Clear pending interrupt */
		timrot_irq_acknowledge();
	}

#ifdef DEBUG
	pr_info("%s: changing mode from %s to %s\n", __func__,
		clock_event_mode_label[mxs_clockevent_mode],
		clock_event_mode_label[mode]);
#endif /* DEBUG */

	/* Remember timer mode */
	mxs_clockevent_mode = mode;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		pr_err("%s: Periodic mode is not implemented\n", __func__);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		timrot_irq_enable();
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		/* Left event sources disabled, no more interrupts appear */
		break;
	}
}

static struct clock_event_device mxs_clockevent_device = {
	.name		= "mxs_timrot",
	.features	= CLOCK_EVT_FEAT_ONESHOT,
	.set_mode	= mxs_set_mode,
	.set_next_event	= timrotv2_set_next_event,
	.rating		= 200,
};

static int __init mxs_clockevent_init(struct clk *timer_clk)
{
	if (timrot_is_v1())
		mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
	mxs_clockevent_device.cpumask = cpumask_of(0);
	clockevents_config_and_register(&mxs_clockevent_device,
					clk_get_rate(timer_clk),
					timrot_is_v1() ? 0xf : 0x2,
					timrot_is_v1() ? 0xfffe : 0xfffffffe);

	return 0;
}

static struct clocksource clocksource_mxs = {
	.name		= "mxs_timer",
	.rating		= 200,
	.read		= timrotv1_get_cycles,
	.mask		= CLOCKSOURCE_MASK(16),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static u32 notrace mxs_read_sched_clock_v2(void)
{
	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
}

static int __init mxs_clocksource_init(struct clk *timer_clk)
{
	unsigned int c = clk_get_rate(timer_clk);

	if (timrot_is_v1())
		clocksource_register_hz(&clocksource_mxs, c);
	else {
		clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
			"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
		setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
	}

	return 0;
}

static void __init mxs_timer_init(struct device_node *np)
{
	struct clk *timer_clk;
	int irq;

	mxs_timrot_base = of_iomap(np, 0);
	WARN_ON(!mxs_timrot_base);

	timer_clk = of_clk_get(np, 0);
	if (IS_ERR(timer_clk)) {
		pr_err("%s: failed to get clk\n", __func__);
		return;
	}

	clk_prepare_enable(timer_clk);

	/*
	 * Initialize timers to a known state
	 */
	mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);

	/* get timrot version */
	timrot_major_version = __raw_readl(mxs_timrot_base +
				(cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
						MX28_TIMROT_VERSION_OFFSET));
	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;

	/* one for clock_event */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_UPDATE |
			BM_TIMROT_TIMCTRLn_IRQ_EN,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));

	/* another for clocksource */
	__raw_writel((timrot_is_v1() ?
			BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
			BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) |
			BM_TIMROT_TIMCTRLn_RELOAD,
			mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));

	/* set clocksource timer fixed count to the maximum */
	if (timrot_is_v1())
		__raw_writel(0xffff,
			mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	else
		__raw_writel(0xffffffff,
			mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));

	/* init and register the timer to the framework */
	mxs_clocksource_init(timer_clk);
	mxs_clockevent_init(timer_clk);

	/* Make irqs happen */
	irq = irq_of_parse_and_map(np, 0);
	setup_irq(irq, &mxs_timer_irq);
}
CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init)
Commit	Line	Data
4e472096 SG	1	/*
	2	* Copyright (C) 2000-2001 Deep Blue Solutions
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	5	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	6	* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* as published by the Free Software Foundation; either version 2
	11	* of the License, or (at your option) any later version.
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	20	* MA 02110-1301, USA.
	21	*/
	22
39d1367e	23	#include <linux/err.h>
4e472096 SG	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
eeca6e60	28	#include <linux/of.h>
be35bd2b	29	#include <linux/of_address.h>
eeca6e60	30	#include <linux/of_irq.h>
4e472096 SG	31
4e472096 SG	32	#include <asm/mach/time.h>
67948ada	33	#include <asm/sched_clock.h>
4e472096 SG	34	#include <mach/mxs.h>
	35	#include <mach/common.h>
	36
	37	/*
	38	* There are 2 versions of the timrot on Freescale MXS-based SoCs.
	39	* The v1 on MX23 only gets 16 bits counter, while v2 on MX28
	40	* extends the counter to 32 bits.
	41	*
	42	* The implementation uses two timers, one for clock_event and
	43	* another for clocksource. MX28 uses timrot 0 and 1, while MX23
	44	* uses 0 and 2.
	45	*/
	46
	47	#define MX23_TIMROT_VERSION_OFFSET 0x0a0
	48	#define MX28_TIMROT_VERSION_OFFSET 0x120
	49	#define BP_TIMROT_MAJOR_VERSION 24
	50	#define BV_TIMROT_VERSION_1 0x01
	51	#define BV_TIMROT_VERSION_2 0x02
	52	#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
	53
	54	/*
	55	* There are 4 registers for each timrotv2 instance, and 2 registers
	56	* for each timrotv1. So address step 0x40 in macros below strides
	57	* one instance of timrotv2 while two instances of timrotv1.
	58	*
	59	* As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
	60	* on MX28 while timrot2 on MX23.
	61	*/
	62	/* common between v1 and v2 */
	63	#define HW_TIMROT_ROTCTRL 0x00
	64	#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
	65	/* v1 only */
	66	#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
	67	/* v2 only */
	68	#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
	69	#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
	70
	71	#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
	72	#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
	73	#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
	74	#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
	75	#define BP_TIMROT_TIMCTRLn_SELECT 0
2fb318ff TH	76	#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
	77	#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
	78	#define BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS 0xf
4e472096 SG	79
	80	static struct clock_event_device mxs_clockevent_device;
	81	static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
	82
be35bd2b	83	static void __iomem *mxs_timrot_base;
4e472096 SG	84	static u32 timrot_major_version;
	85
	86	static inline void timrot_irq_disable(void)
	87	{
	88	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
	89	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	90	}
	91
	92	static inline void timrot_irq_enable(void)
	93	{
	94	__mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
	95	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	96	}
	97
	98	static void timrot_irq_acknowledge(void)
	99	{
	100	__mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
	101	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	102	}
	103
	104	static cycle_t timrotv1_get_cycles(struct clocksource *cs)
	105	{
	106	return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
	107	& 0xffff0000) >> 16);
	108	}
	109
4e472096 SG	110	static int timrotv1_set_next_event(unsigned long evt,
	111	struct clock_event_device *dev)
	112	{
	113	/* timrot decrements the count */
	114	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
	115
	116	return 0;
	117	}
	118
	119	static int timrotv2_set_next_event(unsigned long evt,
	120	struct clock_event_device *dev)
	121	{
	122	/* timrot decrements the count */
	123	__raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
	124
	125	return 0;
	126	}
	127
	128	static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
	129	{
	130	struct clock_event_device *evt = dev_id;
	131
	132	timrot_irq_acknowledge();
	133	evt->event_handler(evt);
	134
	135	return IRQ_HANDLED;
	136	}
	137
	138	static struct irqaction mxs_timer_irq = {
	139	.name = "MXS Timer Tick",
	140	.dev_id = &mxs_clockevent_device,
	141	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
	142	.handler = mxs_timer_interrupt,
	143	};
	144
	145	#ifdef DEBUG
	146	static const char *clock_event_mode_label[] const = {
	147	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	148	[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
	149	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	150	[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
	151	};
	152	#endif /* DEBUG */
	153
	154	static void mxs_set_mode(enum clock_event_mode mode,
	155	struct clock_event_device *evt)
	156	{
	157	/* Disable interrupt in timer module */
	158	timrot_irq_disable();
	159
	160	if (mode != mxs_clockevent_mode) {
	161	/* Set event time into the furthest future */
	162	if (timrot_is_v1())
	163	__raw_writel(0xffff,
	164	mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	165	else
	166	__raw_writel(0xffffffff,
	167	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
	168
	169	/* Clear pending interrupt */
	170	timrot_irq_acknowledge();
	171	}
	172
	173	#ifdef DEBUG
174	pr_info("%s: changing mode from %s to %s\n", __func__,
175	clock_event_mode_label[mxs_clockevent_mode],
176	clock_event_mode_label[mode]);
177	#endif /* DEBUG */
178
179	/* Remember timer mode */
180	mxs_clockevent_mode = mode;
181
182	switch (mode) {
183	case CLOCK_EVT_MODE_PERIODIC:
184	pr_err("%s: Periodic mode is not implemented\n", __func__);
185	break;
186	case CLOCK_EVT_MODE_ONESHOT:
187	timrot_irq_enable();
188	break;
189	case CLOCK_EVT_MODE_SHUTDOWN:
190	case CLOCK_EVT_MODE_UNUSED:
191	case CLOCK_EVT_MODE_RESUME:
192	/* Left event sources disabled, no more interrupts appear */
193	break;
194	}
195	}
196
197	static struct clock_event_device mxs_clockevent_device = {
198	.name = "mxs_timrot",
199	.features = CLOCK_EVT_FEAT_ONESHOT,
4e472096 SG	200	.set_mode = mxs_set_mode,
	201	.set_next_event = timrotv2_set_next_event,
	202	.rating = 200,
	203	};
	204
	205	static int __init mxs_clockevent_init(struct clk *timer_clk)
	206	{
838a2ae8	207	if (timrot_is_v1())
4e472096	208	mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
838a2ae8 SG	209	mxs_clockevent_device.cpumask = cpumask_of(0);
838a2ae8 SG	210	clockevents_config_and_register(&mxs_clockevent_device,
93044fa1 TH	211	clk_get_rate(timer_clk),
93044fa1 TH	212	timrot_is_v1() ? 0xf : 0x2,
838a2ae8	213	timrot_is_v1() ? 0xfffe : 0xfffffffe);
4e472096 SG	214
	215	return 0;
	216	}
	217
	218	static struct clocksource clocksource_mxs = {
	219	.name = "mxs_timer",
	220	.rating = 200,
5c61ddcf RK	221	.read = timrotv1_get_cycles,
5c61ddcf RK	222	.mask = CLOCKSOURCE_MASK(16),
4e472096 SG	223	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	224	};
	225
67948ada SM	226	static u32 notrace mxs_read_sched_clock_v2(void)
	227	{
	228	return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
	229	}
	230
4e472096 SG	231	static int __init mxs_clocksource_init(struct clk *timer_clk)
	232	{
	233	unsigned int c = clk_get_rate(timer_clk);
	234
5c61ddcf RK	235	if (timrot_is_v1())
5c61ddcf RK	236	clocksource_register_hz(&clocksource_mxs, c);
67948ada	237	else {
5c61ddcf RK	238	clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
5c61ddcf RK	239	"mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
67948ada SM	240	setup_sched_clock(mxs_read_sched_clock_v2, 32, c);
67948ada SM	241	}
4e472096 SG	242
	243	return 0;
	244	}
	245
633ef4c7	246	static void __init mxs_timer_init(struct device_node *np)
4e472096	247	{
50260924	248	struct clk *timer_clk;
eeca6e60 SG	249	int irq;
eeca6e60 SG	250
be35bd2b SG	251	mxs_timrot_base = of_iomap(np, 0);
	252	WARN_ON(!mxs_timrot_base);
	253
2efb9504	254	timer_clk = of_clk_get(np, 0);
50260924 SG	255	if (IS_ERR(timer_clk)) {
	256	pr_err("%s: failed to get clk\n", __func__);
	257	return;
39d1367e SG	258	}
39d1367e SG	259
ae68f7af	260	clk_prepare_enable(timer_clk);
4e472096 SG	261
	262	/*
	263	* Initialize timers to a known state
	264	*/
	265	mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
	266
	267	/* get timrot version */
	268	timrot_major_version = __raw_readl(mxs_timrot_base +
	269	(cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
	270	MX28_TIMROT_VERSION_OFFSET));
	271	timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
	272
	273	/* one for clock_event */
	274	__raw_writel((timrot_is_v1() ?
	275	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	276	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	277	BM_TIMROT_TIMCTRLn_UPDATE \|
	278	BM_TIMROT_TIMCTRLn_IRQ_EN,
	279	mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
	280
	281	/* another for clocksource */
	282	__raw_writel((timrot_is_v1() ?
	283	BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
2fb318ff	284	BV_TIMROTv2_TIMCTRLn_SELECT__TICK_ALWAYS) \|
4e472096 SG	285	BM_TIMROT_TIMCTRLn_RELOAD,
	286	mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
	287
	288	/* set clocksource timer fixed count to the maximum */
	289	if (timrot_is_v1())
	290	__raw_writel(0xffff,
	291	mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
	292	else
	293	__raw_writel(0xffffffff,
	294	mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
	295
	296	/* init and register the timer to the framework */
	297	mxs_clocksource_init(timer_clk);
	298	mxs_clockevent_init(timer_clk);
	299
	300	/* Make irqs happen */
eeca6e60	301	irq = irq_of_parse_and_map(np, 0);
4e472096 SG	302	setup_irq(irq, &mxs_timer_irq);
4e472096 SG	303	}
633ef4c7	304	CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init)