[deliverable/linux.git] / arch / arm / mach-netx / time.c

/*
 * arch/arm/mach-netx/time.c
 *
 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <asm/mach/time.h>
#include <mach/netx-regs.h>

#define NETX_CLOCK_FREQ 100000000
#define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ)

#define TIMER_CLOCKEVENT 0
#define TIMER_CLOCKSOURCE 1

static void netx_set_mode(enum clock_event_mode mode,
		struct clock_event_device *clk)
{
	u32 tmode;

	/* disable timer */
	writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
		tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
			NETX_GPIO_COUNTER_CTRL_IRQ_EN |
			NETX_GPIO_COUNTER_CTRL_RUN;
		break;

	case CLOCK_EVT_MODE_ONESHOT:
		writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
		tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN |
			NETX_GPIO_COUNTER_CTRL_RUN;
		break;

	default:
		WARN(1, "%s: unhandled mode %d\n", __func__, mode);
		/* fall through */

	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		tmode = 0;
		break;
	}

	writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
}

static int netx_set_next_event(unsigned long evt,
		struct clock_event_device *clk)
{
	writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT));
	return 0;
}

static struct clock_event_device netx_clockevent = {
	.name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_next_event = netx_set_next_event,
	.set_mode = netx_set_mode,
};

/*
 * IRQ handler for the timer
 */
static irqreturn_t
netx_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &netx_clockevent;

	/* acknowledge interrupt */
	writel(COUNTER_BIT(0), NETX_GPIO_IRQ);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction netx_timer_irq = {
	.name		= "NetX Timer Tick",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= netx_timer_interrupt,
};

/*
 * Set up timer interrupt
 */
void __init netx_timer_init(void)
{
	/* disable timer initially */
	writel(0, NETX_GPIO_COUNTER_CTRL(0));

	/* Reset the timer value to zero */
	writel(0, NETX_GPIO_COUNTER_CURRENT(0));

	writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0));

	/* acknowledge interrupt */
	writel(COUNTER_BIT(0), NETX_GPIO_IRQ);

	/* Enable the interrupt in the specific timer
	 * register and start timer
	 */
	writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
	writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
			NETX_GPIO_COUNTER_CTRL(0));

	setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);

	/* Setup timer one for clocksource */
	writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
	writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
	writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));

	writel(NETX_GPIO_COUNTER_CTRL_RUN,
			NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));

	clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
		"netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up);

	/* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
	 * Adding some safety ... */
	netx_clockevent.cpumask = cpumask_of(0);
	clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ,
					0xa00, 0xfffffffe);
}
Commit	Line	Data
bb6d8c88 SH	1	/*
	2	* arch/arm/mach-netx/time.c
	3	*
	4	* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2
	8	* as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/interrupt.h>
1a815aed SH	22	#include <linux/irq.h>
1a815aed SH	23	#include <linux/clocksource.h>
2fcfe6b8	24	#include <linux/clockchips.h>
fced80c7	25	#include <linux/io.h>
bb6d8c88	26
a09e64fb	27	#include <mach/hardware.h>
bb6d8c88	28	#include <asm/mach/time.h>
a09e64fb	29	#include <mach/netx-regs.h>
bb6d8c88	30
5e3e2763 UKK	31	#define NETX_CLOCK_FREQ 100000000
	32	#define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ)
	33
2fcfe6b8	34	#define TIMER_CLOCKEVENT 0
24e78576 UKK	35	#define TIMER_CLOCKSOURCE 1
24e78576 UKK	36
2fcfe6b8 UKK	37	static void netx_set_mode(enum clock_event_mode mode,
	38	struct clock_event_device *clk)
	39	{
	40	u32 tmode;
	41
	42	/* disable timer */
	43	writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
	44
	45	switch (mode) {
	46	case CLOCK_EVT_MODE_PERIODIC:
5e3e2763	47	writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
2fcfe6b8 UKK	48	tmode = NETX_GPIO_COUNTER_CTRL_RST_EN \|
	49	NETX_GPIO_COUNTER_CTRL_IRQ_EN \|
	50	NETX_GPIO_COUNTER_CTRL_RUN;
	51	break;
	52
	53	case CLOCK_EVT_MODE_ONESHOT:
	54	writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
	55	tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN \|
	56	NETX_GPIO_COUNTER_CTRL_RUN;
	57	break;
	58
	59	default:
	60	WARN(1, "%s: unhandled mode %d\n", __func__, mode);
	61	/* fall through */
	62
	63	case CLOCK_EVT_MODE_SHUTDOWN:
	64	case CLOCK_EVT_MODE_UNUSED:
	65	case CLOCK_EVT_MODE_RESUME:
	66	tmode = 0;
	67	break;
	68	}
	69
	70	writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
	71	}
	72
	73	static int netx_set_next_event(unsigned long evt,
	74	struct clock_event_device *clk)
	75	{
	76	writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT));
	77	return 0;
	78	}
	79
	80	static struct clock_event_device netx_clockevent = {
	81	.name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
2fcfe6b8 UKK	82	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	83	.set_next_event = netx_set_next_event,
	84	.set_mode = netx_set_mode,
	85	};
	86
bb6d8c88 SH	87	/*
	88	* IRQ handler for the timer
	89	*/
	90	static irqreturn_t
0cd61b68	91	netx_timer_interrupt(int irq, void *dev_id)
bb6d8c88	92	{
2fcfe6b8	93	struct clock_event_device *evt = &netx_clockevent;
1a815aed	94
bb6d8c88 SH	95	/* acknowledge interrupt */
	96	writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
	97
2fcfe6b8 UKK	98	evt->event_handler(evt);
2fcfe6b8 UKK	99
bb6d8c88 SH	100	return IRQ_HANDLED;
	101	}
	102
bb6d8c88	103	static struct irqaction netx_timer_irq = {
98538488	104	.name = "NetX Timer Tick",
78f6db99	105	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
98538488	106	.handler = netx_timer_interrupt,
bb6d8c88 SH	107	};
	108
	109	/*
	110	* Set up timer interrupt
	111	*/
6bb27d73	112	void __init netx_timer_init(void)
bb6d8c88 SH	113	{
	114	/* disable timer initially */
	115	writel(0, NETX_GPIO_COUNTER_CTRL(0));
	116
	117	/* Reset the timer value to zero */
	118	writel(0, NETX_GPIO_COUNTER_CURRENT(0));
	119
5e3e2763	120	writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0));
bb6d8c88 SH	121
	122	/* acknowledge interrupt */
	123	writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
	124
98538488 UKK	125	/* Enable the interrupt in the specific timer
	126	* register and start timer
	127	*/
bb6d8c88 SH	128	writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
bb6d8c88 SH	129	writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN \| NETX_GPIO_COUNTER_CTRL_RUN,
98538488	130	NETX_GPIO_COUNTER_CTRL(0));
bb6d8c88 SH	131
bb6d8c88 SH	132	setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
1a815aed SH	133
1a815aed SH	134	/* Setup timer one for clocksource */
24e78576 UKK	135	writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
	136	writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
	137	writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));
1a815aed	138
98538488	139	writel(NETX_GPIO_COUNTER_CTRL_RUN,
24e78576	140	NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
1a815aed	141
234b6ced	142	clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
5e3e2763	143	"netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up);
2fcfe6b8	144
2fcfe6b8 UKK	145	/* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
2fcfe6b8 UKK	146	* Adding some safety ... */
29279267	147	netx_clockevent.cpumask = cpumask_of(0);
5e3e2763	148	clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ,
838a2ae8	149	0xa00, 0xfffffffe);
bb6d8c88	150	}