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bb6d8c88 SH |
1 | /* |
2 | * arch/arm/mach-netx/time.c | |
3 | * | |
4 | * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
1a815aed SH |
22 | #include <linux/irq.h> |
23 | #include <linux/clocksource.h> | |
2fcfe6b8 | 24 | #include <linux/clockchips.h> |
fced80c7 | 25 | #include <linux/io.h> |
bb6d8c88 | 26 | |
a09e64fb | 27 | #include <mach/hardware.h> |
bb6d8c88 | 28 | #include <asm/mach/time.h> |
a09e64fb | 29 | #include <mach/netx-regs.h> |
bb6d8c88 | 30 | |
2fcfe6b8 | 31 | #define TIMER_CLOCKEVENT 0 |
24e78576 UKK |
32 | #define TIMER_CLOCKSOURCE 1 |
33 | ||
2fcfe6b8 UKK |
34 | static void netx_set_mode(enum clock_event_mode mode, |
35 | struct clock_event_device *clk) | |
36 | { | |
37 | u32 tmode; | |
38 | ||
39 | /* disable timer */ | |
40 | writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); | |
41 | ||
42 | switch (mode) { | |
43 | case CLOCK_EVT_MODE_PERIODIC: | |
44 | writel(LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); | |
45 | tmode = NETX_GPIO_COUNTER_CTRL_RST_EN | | |
46 | NETX_GPIO_COUNTER_CTRL_IRQ_EN | | |
47 | NETX_GPIO_COUNTER_CTRL_RUN; | |
48 | break; | |
49 | ||
50 | case CLOCK_EVT_MODE_ONESHOT: | |
51 | writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); | |
52 | tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | | |
53 | NETX_GPIO_COUNTER_CTRL_RUN; | |
54 | break; | |
55 | ||
56 | default: | |
57 | WARN(1, "%s: unhandled mode %d\n", __func__, mode); | |
58 | /* fall through */ | |
59 | ||
60 | case CLOCK_EVT_MODE_SHUTDOWN: | |
61 | case CLOCK_EVT_MODE_UNUSED: | |
62 | case CLOCK_EVT_MODE_RESUME: | |
63 | tmode = 0; | |
64 | break; | |
65 | } | |
66 | ||
67 | writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); | |
68 | } | |
69 | ||
70 | static int netx_set_next_event(unsigned long evt, | |
71 | struct clock_event_device *clk) | |
72 | { | |
73 | writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT)); | |
74 | return 0; | |
75 | } | |
76 | ||
77 | static struct clock_event_device netx_clockevent = { | |
78 | .name = "netx-timer" __stringify(TIMER_CLOCKEVENT), | |
2fcfe6b8 UKK |
79 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
80 | .set_next_event = netx_set_next_event, | |
81 | .set_mode = netx_set_mode, | |
82 | }; | |
83 | ||
bb6d8c88 SH |
84 | /* |
85 | * IRQ handler for the timer | |
86 | */ | |
87 | static irqreturn_t | |
0cd61b68 | 88 | netx_timer_interrupt(int irq, void *dev_id) |
bb6d8c88 | 89 | { |
2fcfe6b8 | 90 | struct clock_event_device *evt = &netx_clockevent; |
1a815aed | 91 | |
bb6d8c88 SH |
92 | /* acknowledge interrupt */ |
93 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ); | |
94 | ||
2fcfe6b8 UKK |
95 | evt->event_handler(evt); |
96 | ||
bb6d8c88 SH |
97 | return IRQ_HANDLED; |
98 | } | |
99 | ||
bb6d8c88 | 100 | static struct irqaction netx_timer_irq = { |
98538488 UKK |
101 | .name = "NetX Timer Tick", |
102 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | |
103 | .handler = netx_timer_interrupt, | |
bb6d8c88 SH |
104 | }; |
105 | ||
106 | /* | |
107 | * Set up timer interrupt | |
108 | */ | |
6bb27d73 | 109 | void __init netx_timer_init(void) |
bb6d8c88 SH |
110 | { |
111 | /* disable timer initially */ | |
112 | writel(0, NETX_GPIO_COUNTER_CTRL(0)); | |
113 | ||
114 | /* Reset the timer value to zero */ | |
115 | writel(0, NETX_GPIO_COUNTER_CURRENT(0)); | |
116 | ||
117 | writel(LATCH, NETX_GPIO_COUNTER_MAX(0)); | |
118 | ||
119 | /* acknowledge interrupt */ | |
120 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ); | |
121 | ||
98538488 UKK |
122 | /* Enable the interrupt in the specific timer |
123 | * register and start timer | |
124 | */ | |
bb6d8c88 SH |
125 | writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE); |
126 | writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN, | |
98538488 | 127 | NETX_GPIO_COUNTER_CTRL(0)); |
bb6d8c88 SH |
128 | |
129 | setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq); | |
1a815aed SH |
130 | |
131 | /* Setup timer one for clocksource */ | |
24e78576 UKK |
132 | writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); |
133 | writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE)); | |
134 | writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE)); | |
1a815aed | 135 | |
98538488 | 136 | writel(NETX_GPIO_COUNTER_CTRL_RUN, |
24e78576 | 137 | NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); |
1a815aed | 138 | |
234b6ced RK |
139 | clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), |
140 | "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); | |
2fcfe6b8 | 141 | |
2fcfe6b8 UKK |
142 | /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. |
143 | * Adding some safety ... */ | |
29279267 | 144 | netx_clockevent.cpumask = cpumask_of(0); |
838a2ae8 SG |
145 | clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE, |
146 | 0xa00, 0xfffffffe); | |
bb6d8c88 | 147 | } |