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3179a019 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.h | |
3 | * | |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
15 | ||
8b9dbc16 RK |
16 | static unsigned long omap1_ckctl_recalc(struct clk *clk); |
17 | static unsigned long omap1_watchdog_recalc(struct clk *clk); | |
df2c2e70 | 18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
8b9dbc16 RK |
19 | static unsigned long omap1_sossi_recalc(struct clk *clk); |
20 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); | |
3179a019 | 21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); |
3179a019 | 22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); |
8b9dbc16 | 23 | static unsigned long omap1_uart_recalc(struct clk *clk); |
3179a019 TL |
24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); |
25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); | |
26 | static void omap1_init_ext_clk(struct clk * clk); | |
27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); | |
28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); | |
3179a019 | 29 | |
d5e6072b RK |
30 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
31 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | |
32 | ||
3179a019 TL |
33 | struct mpu_rate { |
34 | unsigned long rate; | |
35 | unsigned long xtal; | |
36 | unsigned long pll_rate; | |
37 | __u16 ckctl_val; | |
38 | __u16 dpllctl_val; | |
39 | }; | |
40 | ||
41 | struct uart_clk { | |
42 | struct clk clk; | |
43 | unsigned long sysc_addr; | |
44 | }; | |
45 | ||
46 | /* Provide a method for preventing idling some ARM IDLECT clocks */ | |
47 | struct arm_idlect1_clk { | |
48 | struct clk clk; | |
49 | unsigned long no_idle_count; | |
50 | __u8 idlect_shift; | |
51 | }; | |
52 | ||
53 | /* ARM_CKCTL bit shifts */ | |
54 | #define CKCTL_PERDIV_OFFSET 0 | |
55 | #define CKCTL_LCDDIV_OFFSET 2 | |
56 | #define CKCTL_ARMDIV_OFFSET 4 | |
57 | #define CKCTL_DSPDIV_OFFSET 6 | |
58 | #define CKCTL_TCDIV_OFFSET 8 | |
59 | #define CKCTL_DSPMMUDIV_OFFSET 10 | |
60 | /*#define ARM_TIMXO 12*/ | |
61 | #define EN_DSPCK 13 | |
62 | /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ | |
63 | /* DSP_CKCTL bit shifts */ | |
64 | #define CKCTL_DSPPERDIV_OFFSET 0 | |
65 | ||
66 | /* ARM_IDLECT2 bit shifts */ | |
67 | #define EN_WDTCK 0 | |
68 | #define EN_XORPCK 1 | |
69 | #define EN_PERCK 2 | |
70 | #define EN_LCDCK 3 | |
71 | #define EN_LBCK 4 /* Not on 1610/1710 */ | |
72 | /*#define EN_HSABCK 5*/ | |
73 | #define EN_APICK 6 | |
74 | #define EN_TIMCK 7 | |
75 | #define DMACK_REQ 8 | |
76 | #define EN_GPIOCK 9 /* Not on 1610/1710 */ | |
77 | /*#define EN_LBFREECK 10*/ | |
78 | #define EN_CKOUT_ARM 11 | |
79 | ||
80 | /* ARM_IDLECT3 bit shifts */ | |
81 | #define EN_OCPI_CK 0 | |
82 | #define EN_TC1_CK 2 | |
83 | #define EN_TC2_CK 4 | |
84 | ||
85 | /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ | |
86 | #define EN_DSPTIMCK 5 | |
87 | ||
88 | /* Various register defines for clock controls scattered around OMAP chip */ | |
90afd5cb | 89 | #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ |
3179a019 TL |
90 | #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ |
91 | #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ | |
92 | #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ | |
93 | #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ | |
94 | #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 | |
95 | #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 | |
96 | #define SOFT_REQ_REG 0xfffe0834 | |
97 | #define SOFT_REQ_REG2 0xfffe0880 | |
98 | ||
99 | /*------------------------------------------------------------------------- | |
100 | * Omap1 MPU rate table | |
101 | *-------------------------------------------------------------------------*/ | |
102 | static struct mpu_rate rate_table[] = { | |
103 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL | |
104 | * NOTE: Comment order here is different from bits in CKCTL value: | |
105 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv | |
106 | */ | |
107 | #if defined(CONFIG_OMAP_ARM_216MHZ) | |
108 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ | |
109 | #endif | |
110 | #if defined(CONFIG_OMAP_ARM_195MHZ) | |
111 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ | |
112 | #endif | |
113 | #if defined(CONFIG_OMAP_ARM_192MHZ) | |
114 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ | |
115 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ | |
116 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ | |
117 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ | |
118 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ | |
119 | #endif | |
120 | #if defined(CONFIG_OMAP_ARM_182MHZ) | |
121 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ | |
122 | #endif | |
123 | #if defined(CONFIG_OMAP_ARM_168MHZ) | |
124 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ | |
125 | #endif | |
126 | #if defined(CONFIG_OMAP_ARM_150MHZ) | |
127 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ | |
128 | #endif | |
129 | #if defined(CONFIG_OMAP_ARM_120MHZ) | |
130 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ | |
131 | #endif | |
132 | #if defined(CONFIG_OMAP_ARM_96MHZ) | |
133 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ | |
134 | #endif | |
135 | #if defined(CONFIG_OMAP_ARM_60MHZ) | |
136 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ | |
137 | #endif | |
138 | #if defined(CONFIG_OMAP_ARM_30MHZ) | |
139 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ | |
140 | #endif | |
141 | { 0, 0, 0, 0, 0 }, | |
142 | }; | |
143 | ||
144 | /*------------------------------------------------------------------------- | |
145 | * Omap1 clocks | |
146 | *-------------------------------------------------------------------------*/ | |
147 | ||
148 | static struct clk ck_ref = { | |
149 | .name = "ck_ref", | |
897dcded | 150 | .ops = &clkops_null, |
3179a019 | 151 | .rate = 12000000, |
3179a019 TL |
152 | }; |
153 | ||
154 | static struct clk ck_dpll1 = { | |
155 | .name = "ck_dpll1", | |
897dcded | 156 | .ops = &clkops_null, |
3179a019 | 157 | .parent = &ck_ref, |
3179a019 TL |
158 | }; |
159 | ||
6f62b58d PW |
160 | /* |
161 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
162 | * activation. [ FIX: SoSSI, SSR ] | |
163 | */ | |
3179a019 TL |
164 | static struct arm_idlect1_clk ck_dpll1out = { |
165 | .clk = { | |
df2c2e70 | 166 | .name = "ck_dpll1out", |
548d8495 | 167 | .ops = &clkops_generic, |
3179a019 | 168 | .parent = &ck_dpll1, |
6f62b58d PW |
169 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | |
170 | ENABLE_ON_INIT, | |
fed415e4 | 171 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
172 | .enable_bit = EN_CKOUT_ARM, |
173 | .recalc = &followparent_recalc, | |
3179a019 TL |
174 | }, |
175 | .idlect_shift = 12, | |
176 | }; | |
177 | ||
df2c2e70 ID |
178 | static struct clk sossi_ck = { |
179 | .name = "ck_sossi", | |
548d8495 | 180 | .ops = &clkops_generic, |
df2c2e70 | 181 | .parent = &ck_dpll1out.clk, |
d7e8f1f9 | 182 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, |
fed415e4 | 183 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), |
df2c2e70 ID |
184 | .enable_bit = 16, |
185 | .recalc = &omap1_sossi_recalc, | |
186 | .set_rate = &omap1_set_sossi_rate, | |
df2c2e70 ID |
187 | }; |
188 | ||
3179a019 TL |
189 | static struct clk arm_ck = { |
190 | .name = "arm_ck", | |
897dcded | 191 | .ops = &clkops_null, |
3179a019 | 192 | .parent = &ck_dpll1, |
3179a019 TL |
193 | .rate_offset = CKCTL_ARMDIV_OFFSET, |
194 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
195 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
196 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
197 | }; |
198 | ||
199 | static struct arm_idlect1_clk armper_ck = { | |
200 | .clk = { | |
201 | .name = "armper_ck", | |
548d8495 | 202 | .ops = &clkops_generic, |
3179a019 | 203 | .parent = &ck_dpll1, |
d7e8f1f9 | 204 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 205 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
206 | .enable_bit = EN_PERCK, |
207 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
208 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
209 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
210 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
211 | }, |
212 | .idlect_shift = 2, | |
213 | }; | |
214 | ||
6f62b58d PW |
215 | /* |
216 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
217 | * activation. [ GPIO code for 1510 ] | |
218 | */ | |
3179a019 TL |
219 | static struct clk arm_gpio_ck = { |
220 | .name = "arm_gpio_ck", | |
548d8495 | 221 | .ops = &clkops_generic, |
3179a019 | 222 | .parent = &ck_dpll1, |
6f62b58d | 223 | .flags = ENABLE_ON_INIT, |
fed415e4 | 224 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
225 | .enable_bit = EN_GPIOCK, |
226 | .recalc = &followparent_recalc, | |
3179a019 TL |
227 | }; |
228 | ||
229 | static struct arm_idlect1_clk armxor_ck = { | |
230 | .clk = { | |
231 | .name = "armxor_ck", | |
548d8495 | 232 | .ops = &clkops_generic, |
3179a019 | 233 | .parent = &ck_ref, |
d7e8f1f9 | 234 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 235 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
236 | .enable_bit = EN_XORPCK, |
237 | .recalc = &followparent_recalc, | |
3179a019 TL |
238 | }, |
239 | .idlect_shift = 1, | |
240 | }; | |
241 | ||
242 | static struct arm_idlect1_clk armtim_ck = { | |
243 | .clk = { | |
244 | .name = "armtim_ck", | |
548d8495 | 245 | .ops = &clkops_generic, |
3179a019 | 246 | .parent = &ck_ref, |
d7e8f1f9 | 247 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 248 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
249 | .enable_bit = EN_TIMCK, |
250 | .recalc = &followparent_recalc, | |
3179a019 TL |
251 | }, |
252 | .idlect_shift = 9, | |
253 | }; | |
254 | ||
255 | static struct arm_idlect1_clk armwdt_ck = { | |
256 | .clk = { | |
257 | .name = "armwdt_ck", | |
548d8495 | 258 | .ops = &clkops_generic, |
3179a019 | 259 | .parent = &ck_ref, |
d7e8f1f9 | 260 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 261 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
262 | .enable_bit = EN_WDTCK, |
263 | .recalc = &omap1_watchdog_recalc, | |
3179a019 TL |
264 | }, |
265 | .idlect_shift = 0, | |
266 | }; | |
267 | ||
268 | static struct clk arminth_ck16xx = { | |
269 | .name = "arminth_ck", | |
897dcded | 270 | .ops = &clkops_null, |
3179a019 | 271 | .parent = &arm_ck, |
3179a019 TL |
272 | .recalc = &followparent_recalc, |
273 | /* Note: On 16xx the frequency can be divided by 2 by programming | |
274 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | |
275 | * | |
276 | * 1510 version is in TC clocks. | |
277 | */ | |
3179a019 TL |
278 | }; |
279 | ||
280 | static struct clk dsp_ck = { | |
281 | .name = "dsp_ck", | |
548d8495 | 282 | .ops = &clkops_generic, |
3179a019 | 283 | .parent = &ck_dpll1, |
fed415e4 | 284 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), |
3179a019 TL |
285 | .enable_bit = EN_DSPCK, |
286 | .rate_offset = CKCTL_DSPDIV_OFFSET, | |
287 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
288 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
289 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
290 | }; |
291 | ||
292 | static struct clk dspmmu_ck = { | |
293 | .name = "dspmmu_ck", | |
897dcded | 294 | .ops = &clkops_null, |
3179a019 | 295 | .parent = &ck_dpll1, |
3179a019 TL |
296 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, |
297 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
298 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
299 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
300 | }; |
301 | ||
302 | static struct clk dspper_ck = { | |
303 | .name = "dspper_ck", | |
548d8495 | 304 | .ops = &clkops_dspck, |
3179a019 | 305 | .parent = &ck_dpll1, |
397fcaf7 | 306 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
307 | .enable_bit = EN_PERCK, |
308 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
309 | .recalc = &omap1_ckctl_recalc_dsp_domain, | |
d5e6072b | 310 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
3179a019 | 311 | .set_rate = &omap1_clk_set_rate_dsp_domain, |
3179a019 TL |
312 | }; |
313 | ||
314 | static struct clk dspxor_ck = { | |
315 | .name = "dspxor_ck", | |
548d8495 | 316 | .ops = &clkops_dspck, |
3179a019 | 317 | .parent = &ck_ref, |
397fcaf7 | 318 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
319 | .enable_bit = EN_XORPCK, |
320 | .recalc = &followparent_recalc, | |
3179a019 TL |
321 | }; |
322 | ||
323 | static struct clk dsptim_ck = { | |
324 | .name = "dsptim_ck", | |
548d8495 | 325 | .ops = &clkops_dspck, |
3179a019 | 326 | .parent = &ck_ref, |
397fcaf7 | 327 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
328 | .enable_bit = EN_DSPTIMCK, |
329 | .recalc = &followparent_recalc, | |
3179a019 TL |
330 | }; |
331 | ||
332 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | |
333 | static struct arm_idlect1_clk tc_ck = { | |
334 | .clk = { | |
335 | .name = "tc_ck", | |
897dcded | 336 | .ops = &clkops_null, |
3179a019 | 337 | .parent = &ck_dpll1, |
3f0a820c | 338 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
339 | .rate_offset = CKCTL_TCDIV_OFFSET, |
340 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
341 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
342 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
343 | }, |
344 | .idlect_shift = 6, | |
345 | }; | |
346 | ||
347 | static struct clk arminth_ck1510 = { | |
348 | .name = "arminth_ck", | |
897dcded | 349 | .ops = &clkops_null, |
3179a019 | 350 | .parent = &tc_ck.clk, |
3179a019 TL |
351 | .recalc = &followparent_recalc, |
352 | /* Note: On 1510 the frequency follows TC_CK | |
353 | * | |
354 | * 16xx version is in MPU clocks. | |
355 | */ | |
3179a019 TL |
356 | }; |
357 | ||
358 | static struct clk tipb_ck = { | |
359 | /* No-idle controlled by "tc_ck" */ | |
6017e295 | 360 | .name = "tipb_ck", |
897dcded | 361 | .ops = &clkops_null, |
3179a019 | 362 | .parent = &tc_ck.clk, |
3179a019 | 363 | .recalc = &followparent_recalc, |
3179a019 TL |
364 | }; |
365 | ||
366 | static struct clk l3_ocpi_ck = { | |
367 | /* No-idle controlled by "tc_ck" */ | |
368 | .name = "l3_ocpi_ck", | |
548d8495 | 369 | .ops = &clkops_generic, |
3179a019 | 370 | .parent = &tc_ck.clk, |
fed415e4 | 371 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
3179a019 TL |
372 | .enable_bit = EN_OCPI_CK, |
373 | .recalc = &followparent_recalc, | |
3179a019 TL |
374 | }; |
375 | ||
376 | static struct clk tc1_ck = { | |
377 | .name = "tc1_ck", | |
548d8495 | 378 | .ops = &clkops_generic, |
3179a019 | 379 | .parent = &tc_ck.clk, |
fed415e4 | 380 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
3179a019 TL |
381 | .enable_bit = EN_TC1_CK, |
382 | .recalc = &followparent_recalc, | |
3179a019 TL |
383 | }; |
384 | ||
6f62b58d PW |
385 | /* |
386 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
387 | * activation. [ pm.c (SRAM), CCP, Camera ] | |
388 | */ | |
3179a019 TL |
389 | static struct clk tc2_ck = { |
390 | .name = "tc2_ck", | |
548d8495 | 391 | .ops = &clkops_generic, |
3179a019 | 392 | .parent = &tc_ck.clk, |
6f62b58d | 393 | .flags = ENABLE_ON_INIT, |
fed415e4 | 394 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
3179a019 TL |
395 | .enable_bit = EN_TC2_CK, |
396 | .recalc = &followparent_recalc, | |
3179a019 TL |
397 | }; |
398 | ||
399 | static struct clk dma_ck = { | |
400 | /* No-idle controlled by "tc_ck" */ | |
401 | .name = "dma_ck", | |
897dcded | 402 | .ops = &clkops_null, |
3179a019 | 403 | .parent = &tc_ck.clk, |
3179a019 | 404 | .recalc = &followparent_recalc, |
3179a019 TL |
405 | }; |
406 | ||
407 | static struct clk dma_lcdfree_ck = { | |
408 | .name = "dma_lcdfree_ck", | |
897dcded | 409 | .ops = &clkops_null, |
3179a019 | 410 | .parent = &tc_ck.clk, |
3179a019 | 411 | .recalc = &followparent_recalc, |
3179a019 TL |
412 | }; |
413 | ||
414 | static struct arm_idlect1_clk api_ck = { | |
415 | .clk = { | |
416 | .name = "api_ck", | |
548d8495 | 417 | .ops = &clkops_generic, |
3179a019 | 418 | .parent = &tc_ck.clk, |
d7e8f1f9 | 419 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 420 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
421 | .enable_bit = EN_APICK, |
422 | .recalc = &followparent_recalc, | |
3179a019 TL |
423 | }, |
424 | .idlect_shift = 8, | |
425 | }; | |
426 | ||
427 | static struct arm_idlect1_clk lb_ck = { | |
428 | .clk = { | |
429 | .name = "lb_ck", | |
548d8495 | 430 | .ops = &clkops_generic, |
3179a019 | 431 | .parent = &tc_ck.clk, |
d7e8f1f9 | 432 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 433 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
434 | .enable_bit = EN_LBCK, |
435 | .recalc = &followparent_recalc, | |
3179a019 TL |
436 | }, |
437 | .idlect_shift = 4, | |
438 | }; | |
439 | ||
440 | static struct clk rhea1_ck = { | |
441 | .name = "rhea1_ck", | |
897dcded | 442 | .ops = &clkops_null, |
3179a019 | 443 | .parent = &tc_ck.clk, |
3179a019 | 444 | .recalc = &followparent_recalc, |
3179a019 TL |
445 | }; |
446 | ||
447 | static struct clk rhea2_ck = { | |
448 | .name = "rhea2_ck", | |
897dcded | 449 | .ops = &clkops_null, |
3179a019 | 450 | .parent = &tc_ck.clk, |
3179a019 | 451 | .recalc = &followparent_recalc, |
3179a019 TL |
452 | }; |
453 | ||
454 | static struct clk lcd_ck_16xx = { | |
455 | .name = "lcd_ck", | |
548d8495 | 456 | .ops = &clkops_generic, |
3179a019 | 457 | .parent = &ck_dpll1, |
fed415e4 | 458 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
459 | .enable_bit = EN_LCDCK, |
460 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
461 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
462 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
463 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
464 | }; |
465 | ||
466 | static struct arm_idlect1_clk lcd_ck_1510 = { | |
467 | .clk = { | |
468 | .name = "lcd_ck", | |
548d8495 | 469 | .ops = &clkops_generic, |
3179a019 | 470 | .parent = &ck_dpll1, |
d7e8f1f9 | 471 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 472 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
473 | .enable_bit = EN_LCDCK, |
474 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
475 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
476 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
477 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
478 | }, |
479 | .idlect_shift = 3, | |
480 | }; | |
481 | ||
482 | static struct clk uart1_1510 = { | |
483 | .name = "uart1_ck", | |
897dcded | 484 | .ops = &clkops_null, |
3179a019 TL |
485 | /* Direct from ULPD, no real parent */ |
486 | .parent = &armper_ck.clk, | |
487 | .rate = 12000000, | |
d7e8f1f9 | 488 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 489 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 TL |
490 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ |
491 | .set_rate = &omap1_set_uart_rate, | |
492 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
493 | }; |
494 | ||
495 | static struct uart_clk uart1_16xx = { | |
496 | .clk = { | |
497 | .name = "uart1_ck", | |
548d8495 | 498 | .ops = &clkops_uart, |
3179a019 TL |
499 | /* Direct from ULPD, no real parent */ |
500 | .parent = &armper_ck.clk, | |
501 | .rate = 48000000, | |
d7e8f1f9 RK |
502 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
503 | CLOCK_NO_IDLE_PARENT, | |
fed415e4 | 504 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 505 | .enable_bit = 29, |
3179a019 TL |
506 | }, |
507 | .sysc_addr = 0xfffb0054, | |
508 | }; | |
509 | ||
510 | static struct clk uart2_ck = { | |
511 | .name = "uart2_ck", | |
897dcded | 512 | .ops = &clkops_null, |
3179a019 TL |
513 | /* Direct from ULPD, no real parent */ |
514 | .parent = &armper_ck.clk, | |
515 | .rate = 12000000, | |
d7e8f1f9 | 516 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 517 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 TL |
518 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ |
519 | .set_rate = &omap1_set_uart_rate, | |
520 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
521 | }; |
522 | ||
523 | static struct clk uart3_1510 = { | |
524 | .name = "uart3_ck", | |
897dcded | 525 | .ops = &clkops_null, |
3179a019 TL |
526 | /* Direct from ULPD, no real parent */ |
527 | .parent = &armper_ck.clk, | |
528 | .rate = 12000000, | |
d7e8f1f9 | 529 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 530 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 TL |
531 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ |
532 | .set_rate = &omap1_set_uart_rate, | |
533 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
534 | }; |
535 | ||
536 | static struct uart_clk uart3_16xx = { | |
537 | .clk = { | |
538 | .name = "uart3_ck", | |
548d8495 | 539 | .ops = &clkops_uart, |
3179a019 TL |
540 | /* Direct from ULPD, no real parent */ |
541 | .parent = &armper_ck.clk, | |
542 | .rate = 48000000, | |
d7e8f1f9 RK |
543 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
544 | CLOCK_NO_IDLE_PARENT, | |
fed415e4 | 545 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 546 | .enable_bit = 31, |
3179a019 TL |
547 | }, |
548 | .sysc_addr = 0xfffb9854, | |
549 | }; | |
550 | ||
551 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |
552 | .name = "usb_clko", | |
548d8495 | 553 | .ops = &clkops_generic, |
3179a019 TL |
554 | /* Direct from ULPD, no parent */ |
555 | .rate = 6000000, | |
d7e8f1f9 | 556 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
fed415e4 | 557 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
3179a019 | 558 | .enable_bit = USB_MCLK_EN_BIT, |
3179a019 TL |
559 | }; |
560 | ||
561 | static struct clk usb_hhc_ck1510 = { | |
562 | .name = "usb_hhc_ck", | |
548d8495 | 563 | .ops = &clkops_generic, |
3179a019 TL |
564 | /* Direct from ULPD, no parent */ |
565 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | |
d7e8f1f9 | 566 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
fed415e4 | 567 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 568 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
3179a019 TL |
569 | }; |
570 | ||
571 | static struct clk usb_hhc_ck16xx = { | |
572 | .name = "usb_hhc_ck", | |
548d8495 | 573 | .ops = &clkops_generic, |
3179a019 TL |
574 | /* Direct from ULPD, no parent */ |
575 | .rate = 48000000, | |
576 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | |
d7e8f1f9 | 577 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
fed415e4 | 578 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
3179a019 | 579 | .enable_bit = 8 /* UHOST_EN */, |
3179a019 TL |
580 | }; |
581 | ||
582 | static struct clk usb_dc_ck = { | |
583 | .name = "usb_dc_ck", | |
548d8495 | 584 | .ops = &clkops_generic, |
3179a019 TL |
585 | /* Direct from ULPD, no parent */ |
586 | .rate = 48000000, | |
d7e8f1f9 | 587 | .flags = RATE_FIXED, |
fed415e4 | 588 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
3179a019 | 589 | .enable_bit = 4, |
3179a019 TL |
590 | }; |
591 | ||
45f780a0 CM |
592 | static struct clk usb_dc_ck7xx = { |
593 | .name = "usb_dc_ck", | |
594 | .ops = &clkops_generic, | |
595 | /* Direct from ULPD, no parent */ | |
596 | .rate = 48000000, | |
597 | .flags = RATE_FIXED, | |
598 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
599 | .enable_bit = 8, | |
600 | }; | |
601 | ||
3179a019 TL |
602 | static struct clk mclk_1510 = { |
603 | .name = "mclk", | |
548d8495 | 604 | .ops = &clkops_generic, |
3179a019 TL |
605 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
606 | .rate = 12000000, | |
d7e8f1f9 | 607 | .flags = RATE_FIXED, |
fed415e4 TL |
608 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
609 | .enable_bit = 6, | |
3179a019 TL |
610 | }; |
611 | ||
612 | static struct clk mclk_16xx = { | |
613 | .name = "mclk", | |
548d8495 | 614 | .ops = &clkops_generic, |
3179a019 | 615 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
fed415e4 | 616 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), |
3179a019 TL |
617 | .enable_bit = COM_ULPD_PLL_CLK_REQ, |
618 | .set_rate = &omap1_set_ext_clk_rate, | |
619 | .round_rate = &omap1_round_ext_clk_rate, | |
620 | .init = &omap1_init_ext_clk, | |
3179a019 TL |
621 | }; |
622 | ||
623 | static struct clk bclk_1510 = { | |
624 | .name = "bclk", | |
548d8495 | 625 | .ops = &clkops_generic, |
3179a019 TL |
626 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
627 | .rate = 12000000, | |
d7e8f1f9 | 628 | .flags = RATE_FIXED, |
3179a019 TL |
629 | }; |
630 | ||
631 | static struct clk bclk_16xx = { | |
632 | .name = "bclk", | |
548d8495 | 633 | .ops = &clkops_generic, |
3179a019 | 634 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
fed415e4 | 635 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), |
3179a019 TL |
636 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, |
637 | .set_rate = &omap1_set_ext_clk_rate, | |
638 | .round_rate = &omap1_round_ext_clk_rate, | |
639 | .init = &omap1_init_ext_clk, | |
3179a019 TL |
640 | }; |
641 | ||
642 | static struct clk mmc1_ck = { | |
b824efae | 643 | .name = "mmc_ck", |
548d8495 | 644 | .ops = &clkops_generic, |
3179a019 TL |
645 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
646 | .parent = &armper_ck.clk, | |
647 | .rate = 48000000, | |
d7e8f1f9 | 648 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 649 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 650 | .enable_bit = 23, |
3179a019 TL |
651 | }; |
652 | ||
653 | static struct clk mmc2_ck = { | |
b824efae | 654 | .name = "mmc_ck", |
d8874665 | 655 | .id = 1, |
548d8495 | 656 | .ops = &clkops_generic, |
3179a019 TL |
657 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
658 | .parent = &armper_ck.clk, | |
659 | .rate = 48000000, | |
d7e8f1f9 | 660 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 661 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 662 | .enable_bit = 20, |
3179a019 TL |
663 | }; |
664 | ||
490a5665 CM |
665 | static struct clk mmc3_ck = { |
666 | .name = "mmc_ck", | |
667 | .id = 2, | |
668 | .ops = &clkops_generic, | |
669 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | |
670 | .parent = &armper_ck.clk, | |
671 | .rate = 48000000, | |
672 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
673 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
674 | .enable_bit = 12, | |
675 | }; | |
676 | ||
3179a019 TL |
677 | static struct clk virtual_ck_mpu = { |
678 | .name = "mpu", | |
897dcded | 679 | .ops = &clkops_null, |
3179a019 TL |
680 | .parent = &arm_ck, /* Is smarter alias for */ |
681 | .recalc = &followparent_recalc, | |
682 | .set_rate = &omap1_select_table_rate, | |
683 | .round_rate = &omap1_round_to_table_rate, | |
3179a019 TL |
684 | }; |
685 | ||
b824efae TL |
686 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK |
687 | remains active during MPU idle whenever this is enabled */ | |
688 | static struct clk i2c_fck = { | |
689 | .name = "i2c_fck", | |
690 | .id = 1, | |
897dcded | 691 | .ops = &clkops_null, |
d7e8f1f9 | 692 | .flags = CLOCK_NO_IDLE_PARENT, |
b824efae TL |
693 | .parent = &armxor_ck.clk, |
694 | .recalc = &followparent_recalc, | |
b824efae TL |
695 | }; |
696 | ||
90afd5cb TL |
697 | static struct clk i2c_ick = { |
698 | .name = "i2c_ick", | |
699 | .id = 1, | |
897dcded | 700 | .ops = &clkops_null, |
d7e8f1f9 | 701 | .flags = CLOCK_NO_IDLE_PARENT, |
90afd5cb TL |
702 | .parent = &armper_ck.clk, |
703 | .recalc = &followparent_recalc, | |
90afd5cb TL |
704 | }; |
705 | ||
3179a019 | 706 | #endif |