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52650505 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap1/clock_data.c | |
3 | * | |
4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | ||
17 | #include <asm/mach-types.h> /* for machine_is_* */ | |
18 | ||
19 | #include <plat/clock.h> | |
20 | #include <plat/cpu.h> | |
21 | #include <plat/clkdev_omap.h> | |
22 | #include <plat/usb.h> /* for OTG_BASE */ | |
23 | ||
24 | #include "clock.h" | |
25 | ||
26 | /*------------------------------------------------------------------------ | |
27 | * Omap1 clocks | |
28 | *-------------------------------------------------------------------------*/ | |
29 | ||
30 | /* XXX is this necessary? */ | |
31 | static struct clk dummy_ck = { | |
32 | .name = "dummy", | |
33 | .ops = &clkops_dummy, | |
34 | .flags = RATE_FIXED, | |
35 | }; | |
36 | ||
37 | static struct clk ck_ref = { | |
38 | .name = "ck_ref", | |
39 | .ops = &clkops_null, | |
40 | .rate = 12000000, | |
41 | }; | |
42 | ||
43 | static struct clk ck_dpll1 = { | |
44 | .name = "ck_dpll1", | |
45 | .ops = &clkops_null, | |
46 | .parent = &ck_ref, | |
47 | }; | |
48 | ||
49 | /* | |
50 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
51 | * activation. [ FIX: SoSSI, SSR ] | |
52 | */ | |
53 | static struct arm_idlect1_clk ck_dpll1out = { | |
54 | .clk = { | |
55 | .name = "ck_dpll1out", | |
56 | .ops = &clkops_generic, | |
57 | .parent = &ck_dpll1, | |
58 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | | |
59 | ENABLE_ON_INIT, | |
60 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
61 | .enable_bit = EN_CKOUT_ARM, | |
62 | .recalc = &followparent_recalc, | |
63 | }, | |
64 | .idlect_shift = 12, | |
65 | }; | |
66 | ||
67 | static struct clk sossi_ck = { | |
68 | .name = "ck_sossi", | |
69 | .ops = &clkops_generic, | |
70 | .parent = &ck_dpll1out.clk, | |
71 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, | |
72 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), | |
73 | .enable_bit = 16, | |
74 | .recalc = &omap1_sossi_recalc, | |
75 | .set_rate = &omap1_set_sossi_rate, | |
76 | }; | |
77 | ||
78 | static struct clk arm_ck = { | |
79 | .name = "arm_ck", | |
80 | .ops = &clkops_null, | |
81 | .parent = &ck_dpll1, | |
82 | .rate_offset = CKCTL_ARMDIV_OFFSET, | |
83 | .recalc = &omap1_ckctl_recalc, | |
84 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
85 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
86 | }; | |
87 | ||
88 | static struct arm_idlect1_clk armper_ck = { | |
89 | .clk = { | |
90 | .name = "armper_ck", | |
91 | .ops = &clkops_generic, | |
92 | .parent = &ck_dpll1, | |
93 | .flags = CLOCK_IDLE_CONTROL, | |
94 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
95 | .enable_bit = EN_PERCK, | |
96 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
97 | .recalc = &omap1_ckctl_recalc, | |
98 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
99 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
100 | }, | |
101 | .idlect_shift = 2, | |
102 | }; | |
103 | ||
104 | /* | |
105 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
106 | * activation. [ GPIO code for 1510 ] | |
107 | */ | |
108 | static struct clk arm_gpio_ck = { | |
109 | .name = "arm_gpio_ck", | |
110 | .ops = &clkops_generic, | |
111 | .parent = &ck_dpll1, | |
112 | .flags = ENABLE_ON_INIT, | |
113 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
114 | .enable_bit = EN_GPIOCK, | |
115 | .recalc = &followparent_recalc, | |
116 | }; | |
117 | ||
118 | static struct arm_idlect1_clk armxor_ck = { | |
119 | .clk = { | |
120 | .name = "armxor_ck", | |
121 | .ops = &clkops_generic, | |
122 | .parent = &ck_ref, | |
123 | .flags = CLOCK_IDLE_CONTROL, | |
124 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
125 | .enable_bit = EN_XORPCK, | |
126 | .recalc = &followparent_recalc, | |
127 | }, | |
128 | .idlect_shift = 1, | |
129 | }; | |
130 | ||
131 | static struct arm_idlect1_clk armtim_ck = { | |
132 | .clk = { | |
133 | .name = "armtim_ck", | |
134 | .ops = &clkops_generic, | |
135 | .parent = &ck_ref, | |
136 | .flags = CLOCK_IDLE_CONTROL, | |
137 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
138 | .enable_bit = EN_TIMCK, | |
139 | .recalc = &followparent_recalc, | |
140 | }, | |
141 | .idlect_shift = 9, | |
142 | }; | |
143 | ||
144 | static struct arm_idlect1_clk armwdt_ck = { | |
145 | .clk = { | |
146 | .name = "armwdt_ck", | |
147 | .ops = &clkops_generic, | |
148 | .parent = &ck_ref, | |
149 | .flags = CLOCK_IDLE_CONTROL, | |
150 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
151 | .enable_bit = EN_WDTCK, | |
0dfc242f PW |
152 | .fixed_div = 14, |
153 | .recalc = &omap_fixed_divisor_recalc, | |
52650505 PW |
154 | }, |
155 | .idlect_shift = 0, | |
156 | }; | |
157 | ||
158 | static struct clk arminth_ck16xx = { | |
159 | .name = "arminth_ck", | |
160 | .ops = &clkops_null, | |
161 | .parent = &arm_ck, | |
162 | .recalc = &followparent_recalc, | |
163 | /* Note: On 16xx the frequency can be divided by 2 by programming | |
164 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | |
165 | * | |
166 | * 1510 version is in TC clocks. | |
167 | */ | |
168 | }; | |
169 | ||
170 | static struct clk dsp_ck = { | |
171 | .name = "dsp_ck", | |
172 | .ops = &clkops_generic, | |
173 | .parent = &ck_dpll1, | |
174 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), | |
175 | .enable_bit = EN_DSPCK, | |
176 | .rate_offset = CKCTL_DSPDIV_OFFSET, | |
177 | .recalc = &omap1_ckctl_recalc, | |
178 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
179 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
180 | }; | |
181 | ||
182 | static struct clk dspmmu_ck = { | |
183 | .name = "dspmmu_ck", | |
184 | .ops = &clkops_null, | |
185 | .parent = &ck_dpll1, | |
186 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | |
187 | .recalc = &omap1_ckctl_recalc, | |
188 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
189 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
190 | }; | |
191 | ||
192 | static struct clk dspper_ck = { | |
193 | .name = "dspper_ck", | |
194 | .ops = &clkops_dspck, | |
195 | .parent = &ck_dpll1, | |
196 | .enable_reg = DSP_IDLECT2, | |
197 | .enable_bit = EN_PERCK, | |
198 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
199 | .recalc = &omap1_ckctl_recalc_dsp_domain, | |
200 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
201 | .set_rate = &omap1_clk_set_rate_dsp_domain, | |
202 | }; | |
203 | ||
204 | static struct clk dspxor_ck = { | |
205 | .name = "dspxor_ck", | |
206 | .ops = &clkops_dspck, | |
207 | .parent = &ck_ref, | |
208 | .enable_reg = DSP_IDLECT2, | |
209 | .enable_bit = EN_XORPCK, | |
210 | .recalc = &followparent_recalc, | |
211 | }; | |
212 | ||
213 | static struct clk dsptim_ck = { | |
214 | .name = "dsptim_ck", | |
215 | .ops = &clkops_dspck, | |
216 | .parent = &ck_ref, | |
217 | .enable_reg = DSP_IDLECT2, | |
218 | .enable_bit = EN_DSPTIMCK, | |
219 | .recalc = &followparent_recalc, | |
220 | }; | |
221 | ||
222 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | |
223 | static struct arm_idlect1_clk tc_ck = { | |
224 | .clk = { | |
225 | .name = "tc_ck", | |
226 | .ops = &clkops_null, | |
227 | .parent = &ck_dpll1, | |
228 | .flags = CLOCK_IDLE_CONTROL, | |
229 | .rate_offset = CKCTL_TCDIV_OFFSET, | |
230 | .recalc = &omap1_ckctl_recalc, | |
231 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
232 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
233 | }, | |
234 | .idlect_shift = 6, | |
235 | }; | |
236 | ||
237 | static struct clk arminth_ck1510 = { | |
238 | .name = "arminth_ck", | |
239 | .ops = &clkops_null, | |
240 | .parent = &tc_ck.clk, | |
241 | .recalc = &followparent_recalc, | |
242 | /* Note: On 1510 the frequency follows TC_CK | |
243 | * | |
244 | * 16xx version is in MPU clocks. | |
245 | */ | |
246 | }; | |
247 | ||
248 | static struct clk tipb_ck = { | |
249 | /* No-idle controlled by "tc_ck" */ | |
250 | .name = "tipb_ck", | |
251 | .ops = &clkops_null, | |
252 | .parent = &tc_ck.clk, | |
253 | .recalc = &followparent_recalc, | |
254 | }; | |
255 | ||
256 | static struct clk l3_ocpi_ck = { | |
257 | /* No-idle controlled by "tc_ck" */ | |
258 | .name = "l3_ocpi_ck", | |
259 | .ops = &clkops_generic, | |
260 | .parent = &tc_ck.clk, | |
261 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | |
262 | .enable_bit = EN_OCPI_CK, | |
263 | .recalc = &followparent_recalc, | |
264 | }; | |
265 | ||
266 | static struct clk tc1_ck = { | |
267 | .name = "tc1_ck", | |
268 | .ops = &clkops_generic, | |
269 | .parent = &tc_ck.clk, | |
270 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | |
271 | .enable_bit = EN_TC1_CK, | |
272 | .recalc = &followparent_recalc, | |
273 | }; | |
274 | ||
275 | /* | |
276 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
277 | * activation. [ pm.c (SRAM), CCP, Camera ] | |
278 | */ | |
279 | static struct clk tc2_ck = { | |
280 | .name = "tc2_ck", | |
281 | .ops = &clkops_generic, | |
282 | .parent = &tc_ck.clk, | |
283 | .flags = ENABLE_ON_INIT, | |
284 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | |
285 | .enable_bit = EN_TC2_CK, | |
286 | .recalc = &followparent_recalc, | |
287 | }; | |
288 | ||
289 | static struct clk dma_ck = { | |
290 | /* No-idle controlled by "tc_ck" */ | |
291 | .name = "dma_ck", | |
292 | .ops = &clkops_null, | |
293 | .parent = &tc_ck.clk, | |
294 | .recalc = &followparent_recalc, | |
295 | }; | |
296 | ||
297 | static struct clk dma_lcdfree_ck = { | |
298 | .name = "dma_lcdfree_ck", | |
299 | .ops = &clkops_null, | |
300 | .parent = &tc_ck.clk, | |
301 | .recalc = &followparent_recalc, | |
302 | }; | |
303 | ||
304 | static struct arm_idlect1_clk api_ck = { | |
305 | .clk = { | |
306 | .name = "api_ck", | |
307 | .ops = &clkops_generic, | |
308 | .parent = &tc_ck.clk, | |
309 | .flags = CLOCK_IDLE_CONTROL, | |
310 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
311 | .enable_bit = EN_APICK, | |
312 | .recalc = &followparent_recalc, | |
313 | }, | |
314 | .idlect_shift = 8, | |
315 | }; | |
316 | ||
317 | static struct arm_idlect1_clk lb_ck = { | |
318 | .clk = { | |
319 | .name = "lb_ck", | |
320 | .ops = &clkops_generic, | |
321 | .parent = &tc_ck.clk, | |
322 | .flags = CLOCK_IDLE_CONTROL, | |
323 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
324 | .enable_bit = EN_LBCK, | |
325 | .recalc = &followparent_recalc, | |
326 | }, | |
327 | .idlect_shift = 4, | |
328 | }; | |
329 | ||
330 | static struct clk rhea1_ck = { | |
331 | .name = "rhea1_ck", | |
332 | .ops = &clkops_null, | |
333 | .parent = &tc_ck.clk, | |
334 | .recalc = &followparent_recalc, | |
335 | }; | |
336 | ||
337 | static struct clk rhea2_ck = { | |
338 | .name = "rhea2_ck", | |
339 | .ops = &clkops_null, | |
340 | .parent = &tc_ck.clk, | |
341 | .recalc = &followparent_recalc, | |
342 | }; | |
343 | ||
344 | static struct clk lcd_ck_16xx = { | |
345 | .name = "lcd_ck", | |
346 | .ops = &clkops_generic, | |
347 | .parent = &ck_dpll1, | |
348 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
349 | .enable_bit = EN_LCDCK, | |
350 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
351 | .recalc = &omap1_ckctl_recalc, | |
352 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
353 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
354 | }; | |
355 | ||
356 | static struct arm_idlect1_clk lcd_ck_1510 = { | |
357 | .clk = { | |
358 | .name = "lcd_ck", | |
359 | .ops = &clkops_generic, | |
360 | .parent = &ck_dpll1, | |
361 | .flags = CLOCK_IDLE_CONTROL, | |
362 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
363 | .enable_bit = EN_LCDCK, | |
364 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
365 | .recalc = &omap1_ckctl_recalc, | |
366 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
367 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
368 | }, | |
369 | .idlect_shift = 3, | |
370 | }; | |
371 | ||
372 | static struct clk uart1_1510 = { | |
373 | .name = "uart1_ck", | |
374 | .ops = &clkops_null, | |
375 | /* Direct from ULPD, no real parent */ | |
376 | .parent = &armper_ck.clk, | |
377 | .rate = 12000000, | |
378 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
379 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
380 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | |
381 | .set_rate = &omap1_set_uart_rate, | |
382 | .recalc = &omap1_uart_recalc, | |
383 | }; | |
384 | ||
385 | static struct uart_clk uart1_16xx = { | |
386 | .clk = { | |
387 | .name = "uart1_ck", | |
388 | .ops = &clkops_uart, | |
389 | /* Direct from ULPD, no real parent */ | |
390 | .parent = &armper_ck.clk, | |
391 | .rate = 48000000, | |
392 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | |
393 | CLOCK_NO_IDLE_PARENT, | |
394 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
395 | .enable_bit = 29, | |
396 | }, | |
397 | .sysc_addr = 0xfffb0054, | |
398 | }; | |
399 | ||
400 | static struct clk uart2_ck = { | |
401 | .name = "uart2_ck", | |
402 | .ops = &clkops_null, | |
403 | /* Direct from ULPD, no real parent */ | |
404 | .parent = &armper_ck.clk, | |
405 | .rate = 12000000, | |
406 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
407 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
408 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | |
409 | .set_rate = &omap1_set_uart_rate, | |
410 | .recalc = &omap1_uart_recalc, | |
411 | }; | |
412 | ||
413 | static struct clk uart3_1510 = { | |
414 | .name = "uart3_ck", | |
415 | .ops = &clkops_null, | |
416 | /* Direct from ULPD, no real parent */ | |
417 | .parent = &armper_ck.clk, | |
418 | .rate = 12000000, | |
419 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
420 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
421 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | |
422 | .set_rate = &omap1_set_uart_rate, | |
423 | .recalc = &omap1_uart_recalc, | |
424 | }; | |
425 | ||
426 | static struct uart_clk uart3_16xx = { | |
427 | .clk = { | |
428 | .name = "uart3_ck", | |
429 | .ops = &clkops_uart, | |
430 | /* Direct from ULPD, no real parent */ | |
431 | .parent = &armper_ck.clk, | |
432 | .rate = 48000000, | |
433 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | |
434 | CLOCK_NO_IDLE_PARENT, | |
435 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
436 | .enable_bit = 31, | |
437 | }, | |
438 | .sysc_addr = 0xfffb9854, | |
439 | }; | |
440 | ||
441 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |
442 | .name = "usb_clko", | |
443 | .ops = &clkops_generic, | |
444 | /* Direct from ULPD, no parent */ | |
445 | .rate = 6000000, | |
446 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | |
447 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | |
448 | .enable_bit = USB_MCLK_EN_BIT, | |
449 | }; | |
450 | ||
451 | static struct clk usb_hhc_ck1510 = { | |
452 | .name = "usb_hhc_ck", | |
453 | .ops = &clkops_generic, | |
454 | /* Direct from ULPD, no parent */ | |
455 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | |
456 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | |
457 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
458 | .enable_bit = USB_HOST_HHC_UHOST_EN, | |
459 | }; | |
460 | ||
461 | static struct clk usb_hhc_ck16xx = { | |
462 | .name = "usb_hhc_ck", | |
463 | .ops = &clkops_generic, | |
464 | /* Direct from ULPD, no parent */ | |
465 | .rate = 48000000, | |
466 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | |
467 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | |
468 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | |
469 | .enable_bit = 8 /* UHOST_EN */, | |
470 | }; | |
471 | ||
472 | static struct clk usb_dc_ck = { | |
473 | .name = "usb_dc_ck", | |
474 | .ops = &clkops_generic, | |
475 | /* Direct from ULPD, no parent */ | |
476 | .rate = 48000000, | |
477 | .flags = RATE_FIXED, | |
478 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
479 | .enable_bit = 4, | |
480 | }; | |
481 | ||
482 | static struct clk usb_dc_ck7xx = { | |
483 | .name = "usb_dc_ck", | |
484 | .ops = &clkops_generic, | |
485 | /* Direct from ULPD, no parent */ | |
486 | .rate = 48000000, | |
487 | .flags = RATE_FIXED, | |
488 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
489 | .enable_bit = 8, | |
490 | }; | |
491 | ||
492 | static struct clk mclk_1510 = { | |
493 | .name = "mclk", | |
494 | .ops = &clkops_generic, | |
495 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
496 | .rate = 12000000, | |
497 | .flags = RATE_FIXED, | |
498 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
499 | .enable_bit = 6, | |
500 | }; | |
501 | ||
502 | static struct clk mclk_16xx = { | |
503 | .name = "mclk", | |
504 | .ops = &clkops_generic, | |
505 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
506 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), | |
507 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | |
508 | .set_rate = &omap1_set_ext_clk_rate, | |
509 | .round_rate = &omap1_round_ext_clk_rate, | |
510 | .init = &omap1_init_ext_clk, | |
511 | }; | |
512 | ||
513 | static struct clk bclk_1510 = { | |
514 | .name = "bclk", | |
515 | .ops = &clkops_generic, | |
516 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
517 | .rate = 12000000, | |
518 | .flags = RATE_FIXED, | |
519 | }; | |
520 | ||
521 | static struct clk bclk_16xx = { | |
522 | .name = "bclk", | |
523 | .ops = &clkops_generic, | |
524 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
525 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), | |
526 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | |
527 | .set_rate = &omap1_set_ext_clk_rate, | |
528 | .round_rate = &omap1_round_ext_clk_rate, | |
529 | .init = &omap1_init_ext_clk, | |
530 | }; | |
531 | ||
532 | static struct clk mmc1_ck = { | |
b92c170d | 533 | .name = "mmc1_ck", |
52650505 PW |
534 | .ops = &clkops_generic, |
535 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | |
536 | .parent = &armper_ck.clk, | |
537 | .rate = 48000000, | |
538 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
539 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
540 | .enable_bit = 23, | |
541 | }; | |
542 | ||
543 | static struct clk mmc2_ck = { | |
b92c170d | 544 | .name = "mmc2_ck", |
52650505 PW |
545 | .ops = &clkops_generic, |
546 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | |
547 | .parent = &armper_ck.clk, | |
548 | .rate = 48000000, | |
549 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
550 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
551 | .enable_bit = 20, | |
552 | }; | |
553 | ||
554 | static struct clk mmc3_ck = { | |
b92c170d | 555 | .name = "mmc3_ck", |
52650505 PW |
556 | .ops = &clkops_generic, |
557 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | |
558 | .parent = &armper_ck.clk, | |
559 | .rate = 48000000, | |
560 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
561 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
562 | .enable_bit = 12, | |
563 | }; | |
564 | ||
565 | static struct clk virtual_ck_mpu = { | |
566 | .name = "mpu", | |
567 | .ops = &clkops_null, | |
568 | .parent = &arm_ck, /* Is smarter alias for */ | |
569 | .recalc = &followparent_recalc, | |
570 | .set_rate = &omap1_select_table_rate, | |
571 | .round_rate = &omap1_round_to_table_rate, | |
572 | }; | |
573 | ||
574 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | |
575 | remains active during MPU idle whenever this is enabled */ | |
576 | static struct clk i2c_fck = { | |
577 | .name = "i2c_fck", | |
52650505 PW |
578 | .ops = &clkops_null, |
579 | .flags = CLOCK_NO_IDLE_PARENT, | |
580 | .parent = &armxor_ck.clk, | |
581 | .recalc = &followparent_recalc, | |
582 | }; | |
583 | ||
584 | static struct clk i2c_ick = { | |
585 | .name = "i2c_ick", | |
52650505 PW |
586 | .ops = &clkops_null, |
587 | .flags = CLOCK_NO_IDLE_PARENT, | |
588 | .parent = &armper_ck.clk, | |
589 | .recalc = &followparent_recalc, | |
590 | }; | |
591 | ||
592 | /* | |
593 | * clkdev integration | |
594 | */ | |
595 | ||
596 | static struct omap_clk omap_clks[] = { | |
597 | /* non-ULPD clocks */ | |
598 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), | |
e8ae6b6e | 599 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
52650505 PW |
600 | /* CK_GEN1 clocks */ |
601 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | |
602 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | |
603 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | |
604 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | |
605 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | |
606 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | |
607 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | |
608 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | |
609 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | |
610 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | |
611 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | |
612 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | |
613 | /* CK_GEN2 clocks */ | |
614 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | |
615 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | |
616 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | |
617 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | |
618 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | |
619 | /* CK_GEN3 clocks */ | |
620 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | |
621 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | |
622 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), | |
623 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | |
624 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | |
625 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | |
626 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | |
e8ae6b6e | 627 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
52650505 PW |
628 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), |
629 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | |
630 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | |
631 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), | |
632 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | |
633 | /* ULPD clocks */ | |
634 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | |
635 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | |
636 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | |
637 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | |
638 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | |
639 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | |
640 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | |
641 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | |
642 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | |
643 | CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), | |
644 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | |
645 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | |
646 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | |
647 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | |
648 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | |
649 | CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), | |
650 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | |
651 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | |
652 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | |
653 | /* Virtual clocks */ | |
654 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | |
bf92a407 | 655 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
52650505 | 656 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), |
bf92a407 | 657 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), |
c5c4dce4 CM |
658 | CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), |
659 | CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), | |
660 | CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), | |
661 | CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX), | |
52650505 PW |
662 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), |
663 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | |
664 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | |
665 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | |
666 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | |
667 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | |
668 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | |
669 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | |
670 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | |
671 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | |
672 | }; | |
673 | ||
674 | /* | |
675 | * init | |
676 | */ | |
677 | ||
9b11769f | 678 | static struct clk_functions omap1_clk_functions = { |
52650505 PW |
679 | .clk_enable = omap1_clk_enable, |
680 | .clk_disable = omap1_clk_disable, | |
681 | .clk_round_rate = omap1_clk_round_rate, | |
682 | .clk_set_rate = omap1_clk_set_rate, | |
683 | .clk_disable_unused = omap1_clk_disable_unused, | |
684 | }; | |
685 | ||
686 | int __init omap1_clk_init(void) | |
687 | { | |
688 | struct omap_clk *c; | |
689 | const struct omap_clock_config *info; | |
690 | int crystal_type = 0; /* Default 12 MHz */ | |
691 | u32 reg, cpu_mask; | |
692 | ||
693 | #ifdef CONFIG_DEBUG_LL | |
694 | /* | |
695 | * Resets some clocks that may be left on from bootloader, | |
696 | * but leaves serial clocks on. | |
697 | */ | |
698 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | |
699 | #endif | |
700 | ||
701 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ | |
702 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | |
703 | omap_writew(reg, SOFT_REQ_REG); | |
704 | if (!cpu_is_omap15xx()) | |
705 | omap_writew(0, SOFT_REQ_REG2); | |
706 | ||
707 | clk_init(&omap1_clk_functions); | |
708 | ||
709 | /* By default all idlect1 clocks are allowed to idle */ | |
710 | arm_idlect1_mask = ~0; | |
711 | ||
712 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | |
713 | clk_preinit(c->lk.clk); | |
714 | ||
715 | cpu_mask = 0; | |
716 | if (cpu_is_omap16xx()) | |
717 | cpu_mask |= CK_16XX; | |
718 | if (cpu_is_omap1510()) | |
719 | cpu_mask |= CK_1510; | |
720 | if (cpu_is_omap7xx()) | |
721 | cpu_mask |= CK_7XX; | |
722 | if (cpu_is_omap310()) | |
723 | cpu_mask |= CK_310; | |
724 | ||
725 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | |
726 | if (c->cpu & cpu_mask) { | |
727 | clkdev_add(&c->lk); | |
728 | clk_register(c->lk.clk); | |
729 | } | |
730 | ||
731 | /* Pointers to these clocks are needed by code in clock.c */ | |
732 | api_ck_p = clk_get(NULL, "api_ck"); | |
733 | ck_dpll1_p = clk_get(NULL, "ck_dpll1"); | |
734 | ck_ref_p = clk_get(NULL, "ck_ref"); | |
735 | ||
736 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | |
737 | if (info != NULL) { | |
738 | if (!cpu_is_omap15xx()) | |
739 | crystal_type = info->system_clock_type; | |
740 | } | |
741 | ||
742 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | |
743 | ck_ref.rate = 13000000; | |
744 | #elif defined(CONFIG_ARCH_OMAP16XX) | |
745 | if (crystal_type == 2) | |
746 | ck_ref.rate = 19200000; | |
747 | #endif | |
748 | ||
749 | pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " | |
750 | "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | |
751 | omap_readw(ARM_CKCTL)); | |
752 | ||
753 | /* We want to be in syncronous scalable mode */ | |
754 | omap_writew(0x1000, ARM_SYSST); | |
755 | ||
756 | #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER | |
757 | /* Use values set by bootloader. Determine PLL rate and recalculate | |
758 | * dependent clocks as if kernel had changed PLL or divisors. | |
759 | */ | |
760 | { | |
761 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | |
762 | ||
763 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | |
764 | if (pll_ctl_val & 0x10) { | |
765 | /* PLL enabled, apply multiplier and divisor */ | |
766 | if (pll_ctl_val & 0xf80) | |
767 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | |
768 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | |
769 | } else { | |
770 | /* PLL disabled, apply bypass divisor */ | |
771 | switch (pll_ctl_val & 0xc) { | |
772 | case 0: | |
773 | break; | |
774 | case 0x4: | |
775 | ck_dpll1.rate /= 2; | |
776 | break; | |
777 | default: | |
778 | ck_dpll1.rate /= 4; | |
779 | break; | |
780 | } | |
781 | } | |
782 | } | |
783 | #else | |
784 | /* Find the highest supported frequency and enable it */ | |
785 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | |
786 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | |
787 | /* Guess sane values (60MHz) */ | |
788 | omap_writew(0x2290, DPLL_CTL); | |
789 | omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); | |
790 | ck_dpll1.rate = 60000000; | |
791 | } | |
792 | #endif | |
793 | propagate_rate(&ck_dpll1); | |
794 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | |
795 | propagate_rate(&ck_ref); | |
796 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | |
797 | "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", | |
798 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | |
799 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | |
800 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | |
801 | ||
802 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) | |
803 | /* Select slicer output as OMAP input clock */ | |
804 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); | |
805 | #endif | |
806 | ||
807 | /* Amstrad Delta wants BCLK high when inactive */ | |
808 | if (machine_is_ams_delta()) | |
809 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | |
810 | (1 << SDW_MCLK_INV_BIT), | |
811 | ULPD_CLOCK_CTRL); | |
812 | ||
813 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ | |
814 | /* (on 730, bit 13 must not be cleared) */ | |
815 | if (cpu_is_omap7xx()) | |
816 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | |
817 | else | |
818 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | |
819 | ||
820 | /* Put DSP/MPUI into reset until needed */ | |
821 | omap_writew(0, ARM_RSTCT1); | |
822 | omap_writew(1, ARM_RSTCT2); | |
823 | omap_writew(0x400, ARM_IDLECT1); | |
824 | ||
825 | /* | |
826 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | |
827 | * of the ARM_IDLECT2 register must be set to zero. The power-on | |
828 | * default value of this bit is one. | |
829 | */ | |
830 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | |
831 | ||
832 | /* | |
833 | * Only enable those clocks we will need, let the drivers | |
834 | * enable other clocks as necessary | |
835 | */ | |
836 | clk_enable(&armper_ck.clk); | |
837 | clk_enable(&armxor_ck.clk); | |
838 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | |
839 | ||
840 | if (cpu_is_omap15xx()) | |
841 | clk_enable(&arm_gpio_ck); | |
842 | ||
843 | return 0; | |
844 | } |