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52650505 PW |
1 | /* |
2 | * linux/arch/arm/mach-omap1/clock_data.c | |
3 | * | |
51c19541 | 4 | * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation |
52650505 PW |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
fb2fc920 PW |
11 | * |
12 | * To do: | |
13 | * - Clocks that are only available on some chips should be marked with the | |
14 | * chips that they are present on. | |
52650505 PW |
15 | */ |
16 | ||
17 | #include <linux/kernel.h> | |
2c799cef | 18 | #include <linux/io.h> |
52650505 | 19 | #include <linux/clk.h> |
6560ee07 JK |
20 | #include <linux/cpufreq.h> |
21 | #include <linux/delay.h> | |
52650505 PW |
22 | |
23 | #include <asm/mach-types.h> /* for machine_is_* */ | |
24 | ||
e4c060db | 25 | #include "soc.h" |
52650505 | 26 | |
2c799cef | 27 | #include <mach/hardware.h> |
b924b204 | 28 | #include <mach/usb.h> /* for OTG_BASE */ |
2c799cef | 29 | |
622297fd TL |
30 | #include "../plat-omap/sram.h" |
31 | ||
2e3ee9f4 | 32 | #include "iomap.h" |
52650505 PW |
33 | #include "clock.h" |
34 | ||
fb2fc920 PW |
35 | /* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ |
36 | #define IDL_CLKOUT_ARM_SHIFT 12 | |
37 | #define IDLTIM_ARM_SHIFT 9 | |
38 | #define IDLAPI_ARM_SHIFT 8 | |
39 | #define IDLIF_ARM_SHIFT 6 | |
40 | #define IDLLB_ARM_SHIFT 4 /* undocumented? */ | |
41 | #define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */ | |
42 | #define IDLPER_ARM_SHIFT 2 | |
43 | #define IDLXORP_ARM_SHIFT 1 | |
44 | #define IDLWDT_ARM_SHIFT 0 | |
45 | ||
46 | /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */ | |
47 | #define CONF_MOD_UART3_CLK_MODE_R 31 | |
48 | #define CONF_MOD_UART2_CLK_MODE_R 30 | |
49 | #define CONF_MOD_UART1_CLK_MODE_R 29 | |
50 | #define CONF_MOD_MMC_SD_CLK_REQ_R 23 | |
51 | #define CONF_MOD_MCBSP3_AUXON 20 | |
52 | ||
53 | /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */ | |
54 | #define CONF_MOD_SOSSI_CLK_EN_R 16 | |
55 | ||
56 | /* Some OTG_SYSCON_2-specific bit fields */ | |
57 | #define OTG_SYSCON_2_UHOST_EN_SHIFT 8 | |
58 | ||
59 | /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */ | |
60 | #define SOFT_MMC2_DPLL_REQ_SHIFT 13 | |
61 | #define SOFT_MMC_DPLL_REQ_SHIFT 12 | |
62 | #define SOFT_UART3_DPLL_REQ_SHIFT 11 | |
63 | #define SOFT_UART2_DPLL_REQ_SHIFT 10 | |
64 | #define SOFT_UART1_DPLL_REQ_SHIFT 9 | |
65 | #define SOFT_USB_OTG_DPLL_REQ_SHIFT 8 | |
66 | #define SOFT_CAM_DPLL_REQ_SHIFT 7 | |
67 | #define SOFT_COM_MCKO_REQ_SHIFT 6 | |
68 | #define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */ | |
69 | #define USB_REQ_EN_SHIFT 4 | |
70 | #define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */ | |
71 | #define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */ | |
72 | #define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */ | |
73 | #define SOFT_DPLL_REQ_SHIFT 0 | |
74 | ||
75 | /* | |
52650505 | 76 | * Omap1 clocks |
fb2fc920 | 77 | */ |
52650505 | 78 | |
52650505 PW |
79 | static struct clk ck_ref = { |
80 | .name = "ck_ref", | |
81 | .ops = &clkops_null, | |
82 | .rate = 12000000, | |
83 | }; | |
84 | ||
85 | static struct clk ck_dpll1 = { | |
86 | .name = "ck_dpll1", | |
87 | .ops = &clkops_null, | |
88 | .parent = &ck_ref, | |
89 | }; | |
90 | ||
91 | /* | |
92 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
93 | * activation. [ FIX: SoSSI, SSR ] | |
94 | */ | |
95 | static struct arm_idlect1_clk ck_dpll1out = { | |
96 | .clk = { | |
97 | .name = "ck_dpll1out", | |
98 | .ops = &clkops_generic, | |
99 | .parent = &ck_dpll1, | |
100 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | | |
101 | ENABLE_ON_INIT, | |
102 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
103 | .enable_bit = EN_CKOUT_ARM, | |
104 | .recalc = &followparent_recalc, | |
105 | }, | |
fb2fc920 | 106 | .idlect_shift = IDL_CLKOUT_ARM_SHIFT, |
52650505 PW |
107 | }; |
108 | ||
109 | static struct clk sossi_ck = { | |
110 | .name = "ck_sossi", | |
111 | .ops = &clkops_generic, | |
112 | .parent = &ck_dpll1out.clk, | |
113 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, | |
114 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), | |
fb2fc920 | 115 | .enable_bit = CONF_MOD_SOSSI_CLK_EN_R, |
52650505 PW |
116 | .recalc = &omap1_sossi_recalc, |
117 | .set_rate = &omap1_set_sossi_rate, | |
118 | }; | |
119 | ||
120 | static struct clk arm_ck = { | |
121 | .name = "arm_ck", | |
122 | .ops = &clkops_null, | |
123 | .parent = &ck_dpll1, | |
124 | .rate_offset = CKCTL_ARMDIV_OFFSET, | |
125 | .recalc = &omap1_ckctl_recalc, | |
126 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
127 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
128 | }; | |
129 | ||
130 | static struct arm_idlect1_clk armper_ck = { | |
131 | .clk = { | |
132 | .name = "armper_ck", | |
133 | .ops = &clkops_generic, | |
134 | .parent = &ck_dpll1, | |
135 | .flags = CLOCK_IDLE_CONTROL, | |
136 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
137 | .enable_bit = EN_PERCK, | |
138 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
139 | .recalc = &omap1_ckctl_recalc, | |
140 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
141 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
142 | }, | |
fb2fc920 | 143 | .idlect_shift = IDLPER_ARM_SHIFT, |
52650505 PW |
144 | }; |
145 | ||
146 | /* | |
147 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
148 | * activation. [ GPIO code for 1510 ] | |
149 | */ | |
150 | static struct clk arm_gpio_ck = { | |
77640aab | 151 | .name = "ick", |
52650505 PW |
152 | .ops = &clkops_generic, |
153 | .parent = &ck_dpll1, | |
154 | .flags = ENABLE_ON_INIT, | |
155 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
156 | .enable_bit = EN_GPIOCK, | |
157 | .recalc = &followparent_recalc, | |
158 | }; | |
159 | ||
160 | static struct arm_idlect1_clk armxor_ck = { | |
161 | .clk = { | |
162 | .name = "armxor_ck", | |
163 | .ops = &clkops_generic, | |
164 | .parent = &ck_ref, | |
165 | .flags = CLOCK_IDLE_CONTROL, | |
166 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
167 | .enable_bit = EN_XORPCK, | |
168 | .recalc = &followparent_recalc, | |
169 | }, | |
fb2fc920 | 170 | .idlect_shift = IDLXORP_ARM_SHIFT, |
52650505 PW |
171 | }; |
172 | ||
173 | static struct arm_idlect1_clk armtim_ck = { | |
174 | .clk = { | |
175 | .name = "armtim_ck", | |
176 | .ops = &clkops_generic, | |
177 | .parent = &ck_ref, | |
178 | .flags = CLOCK_IDLE_CONTROL, | |
179 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
180 | .enable_bit = EN_TIMCK, | |
181 | .recalc = &followparent_recalc, | |
182 | }, | |
fb2fc920 | 183 | .idlect_shift = IDLTIM_ARM_SHIFT, |
52650505 PW |
184 | }; |
185 | ||
186 | static struct arm_idlect1_clk armwdt_ck = { | |
187 | .clk = { | |
188 | .name = "armwdt_ck", | |
189 | .ops = &clkops_generic, | |
190 | .parent = &ck_ref, | |
191 | .flags = CLOCK_IDLE_CONTROL, | |
192 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
193 | .enable_bit = EN_WDTCK, | |
0dfc242f PW |
194 | .fixed_div = 14, |
195 | .recalc = &omap_fixed_divisor_recalc, | |
52650505 | 196 | }, |
fb2fc920 | 197 | .idlect_shift = IDLWDT_ARM_SHIFT, |
52650505 PW |
198 | }; |
199 | ||
200 | static struct clk arminth_ck16xx = { | |
201 | .name = "arminth_ck", | |
202 | .ops = &clkops_null, | |
203 | .parent = &arm_ck, | |
204 | .recalc = &followparent_recalc, | |
205 | /* Note: On 16xx the frequency can be divided by 2 by programming | |
206 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | |
207 | * | |
208 | * 1510 version is in TC clocks. | |
209 | */ | |
210 | }; | |
211 | ||
212 | static struct clk dsp_ck = { | |
213 | .name = "dsp_ck", | |
214 | .ops = &clkops_generic, | |
215 | .parent = &ck_dpll1, | |
216 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), | |
217 | .enable_bit = EN_DSPCK, | |
218 | .rate_offset = CKCTL_DSPDIV_OFFSET, | |
219 | .recalc = &omap1_ckctl_recalc, | |
220 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
221 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
222 | }; | |
223 | ||
224 | static struct clk dspmmu_ck = { | |
225 | .name = "dspmmu_ck", | |
226 | .ops = &clkops_null, | |
227 | .parent = &ck_dpll1, | |
228 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | |
229 | .recalc = &omap1_ckctl_recalc, | |
230 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
231 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
232 | }; | |
233 | ||
234 | static struct clk dspper_ck = { | |
235 | .name = "dspper_ck", | |
236 | .ops = &clkops_dspck, | |
237 | .parent = &ck_dpll1, | |
238 | .enable_reg = DSP_IDLECT2, | |
239 | .enable_bit = EN_PERCK, | |
240 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
241 | .recalc = &omap1_ckctl_recalc_dsp_domain, | |
242 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
243 | .set_rate = &omap1_clk_set_rate_dsp_domain, | |
244 | }; | |
245 | ||
246 | static struct clk dspxor_ck = { | |
247 | .name = "dspxor_ck", | |
248 | .ops = &clkops_dspck, | |
249 | .parent = &ck_ref, | |
250 | .enable_reg = DSP_IDLECT2, | |
251 | .enable_bit = EN_XORPCK, | |
252 | .recalc = &followparent_recalc, | |
253 | }; | |
254 | ||
255 | static struct clk dsptim_ck = { | |
256 | .name = "dsptim_ck", | |
257 | .ops = &clkops_dspck, | |
258 | .parent = &ck_ref, | |
259 | .enable_reg = DSP_IDLECT2, | |
260 | .enable_bit = EN_DSPTIMCK, | |
261 | .recalc = &followparent_recalc, | |
262 | }; | |
263 | ||
52650505 PW |
264 | static struct arm_idlect1_clk tc_ck = { |
265 | .clk = { | |
266 | .name = "tc_ck", | |
267 | .ops = &clkops_null, | |
268 | .parent = &ck_dpll1, | |
269 | .flags = CLOCK_IDLE_CONTROL, | |
270 | .rate_offset = CKCTL_TCDIV_OFFSET, | |
271 | .recalc = &omap1_ckctl_recalc, | |
272 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
273 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
274 | }, | |
fb2fc920 | 275 | .idlect_shift = IDLIF_ARM_SHIFT, |
52650505 PW |
276 | }; |
277 | ||
278 | static struct clk arminth_ck1510 = { | |
279 | .name = "arminth_ck", | |
280 | .ops = &clkops_null, | |
281 | .parent = &tc_ck.clk, | |
282 | .recalc = &followparent_recalc, | |
283 | /* Note: On 1510 the frequency follows TC_CK | |
284 | * | |
285 | * 16xx version is in MPU clocks. | |
286 | */ | |
287 | }; | |
288 | ||
289 | static struct clk tipb_ck = { | |
290 | /* No-idle controlled by "tc_ck" */ | |
291 | .name = "tipb_ck", | |
292 | .ops = &clkops_null, | |
293 | .parent = &tc_ck.clk, | |
294 | .recalc = &followparent_recalc, | |
295 | }; | |
296 | ||
297 | static struct clk l3_ocpi_ck = { | |
298 | /* No-idle controlled by "tc_ck" */ | |
299 | .name = "l3_ocpi_ck", | |
300 | .ops = &clkops_generic, | |
301 | .parent = &tc_ck.clk, | |
302 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | |
303 | .enable_bit = EN_OCPI_CK, | |
304 | .recalc = &followparent_recalc, | |
305 | }; | |
306 | ||
307 | static struct clk tc1_ck = { | |
308 | .name = "tc1_ck", | |
309 | .ops = &clkops_generic, | |
310 | .parent = &tc_ck.clk, | |
311 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | |
312 | .enable_bit = EN_TC1_CK, | |
313 | .recalc = &followparent_recalc, | |
314 | }; | |
315 | ||
316 | /* | |
317 | * FIXME: This clock seems to be necessary but no-one has asked for its | |
318 | * activation. [ pm.c (SRAM), CCP, Camera ] | |
319 | */ | |
320 | static struct clk tc2_ck = { | |
321 | .name = "tc2_ck", | |
322 | .ops = &clkops_generic, | |
323 | .parent = &tc_ck.clk, | |
324 | .flags = ENABLE_ON_INIT, | |
325 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | |
326 | .enable_bit = EN_TC2_CK, | |
327 | .recalc = &followparent_recalc, | |
328 | }; | |
329 | ||
330 | static struct clk dma_ck = { | |
331 | /* No-idle controlled by "tc_ck" */ | |
332 | .name = "dma_ck", | |
333 | .ops = &clkops_null, | |
334 | .parent = &tc_ck.clk, | |
335 | .recalc = &followparent_recalc, | |
336 | }; | |
337 | ||
338 | static struct clk dma_lcdfree_ck = { | |
339 | .name = "dma_lcdfree_ck", | |
340 | .ops = &clkops_null, | |
341 | .parent = &tc_ck.clk, | |
342 | .recalc = &followparent_recalc, | |
343 | }; | |
344 | ||
345 | static struct arm_idlect1_clk api_ck = { | |
346 | .clk = { | |
347 | .name = "api_ck", | |
348 | .ops = &clkops_generic, | |
349 | .parent = &tc_ck.clk, | |
350 | .flags = CLOCK_IDLE_CONTROL, | |
351 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
352 | .enable_bit = EN_APICK, | |
353 | .recalc = &followparent_recalc, | |
354 | }, | |
fb2fc920 | 355 | .idlect_shift = IDLAPI_ARM_SHIFT, |
52650505 PW |
356 | }; |
357 | ||
358 | static struct arm_idlect1_clk lb_ck = { | |
359 | .clk = { | |
360 | .name = "lb_ck", | |
361 | .ops = &clkops_generic, | |
362 | .parent = &tc_ck.clk, | |
363 | .flags = CLOCK_IDLE_CONTROL, | |
364 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
365 | .enable_bit = EN_LBCK, | |
366 | .recalc = &followparent_recalc, | |
367 | }, | |
fb2fc920 | 368 | .idlect_shift = IDLLB_ARM_SHIFT, |
52650505 PW |
369 | }; |
370 | ||
371 | static struct clk rhea1_ck = { | |
372 | .name = "rhea1_ck", | |
373 | .ops = &clkops_null, | |
374 | .parent = &tc_ck.clk, | |
375 | .recalc = &followparent_recalc, | |
376 | }; | |
377 | ||
378 | static struct clk rhea2_ck = { | |
379 | .name = "rhea2_ck", | |
380 | .ops = &clkops_null, | |
381 | .parent = &tc_ck.clk, | |
382 | .recalc = &followparent_recalc, | |
383 | }; | |
384 | ||
385 | static struct clk lcd_ck_16xx = { | |
386 | .name = "lcd_ck", | |
387 | .ops = &clkops_generic, | |
388 | .parent = &ck_dpll1, | |
389 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
390 | .enable_bit = EN_LCDCK, | |
391 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
392 | .recalc = &omap1_ckctl_recalc, | |
393 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
394 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
395 | }; | |
396 | ||
397 | static struct arm_idlect1_clk lcd_ck_1510 = { | |
398 | .clk = { | |
399 | .name = "lcd_ck", | |
400 | .ops = &clkops_generic, | |
401 | .parent = &ck_dpll1, | |
402 | .flags = CLOCK_IDLE_CONTROL, | |
403 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | |
404 | .enable_bit = EN_LCDCK, | |
405 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
406 | .recalc = &omap1_ckctl_recalc, | |
407 | .round_rate = omap1_clk_round_rate_ckctl_arm, | |
408 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
409 | }, | |
fb2fc920 | 410 | .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT, |
52650505 PW |
411 | }; |
412 | ||
fb2fc920 PW |
413 | /* |
414 | * XXX The enable_bit here is misused - it simply switches between 12MHz | |
415 | * and 48MHz. Reimplement with clksel. | |
416 | * | |
417 | * XXX does this need SYSC register handling? | |
418 | */ | |
52650505 PW |
419 | static struct clk uart1_1510 = { |
420 | .name = "uart1_ck", | |
421 | .ops = &clkops_null, | |
422 | /* Direct from ULPD, no real parent */ | |
423 | .parent = &armper_ck.clk, | |
424 | .rate = 12000000, | |
425 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
426 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
fb2fc920 | 427 | .enable_bit = CONF_MOD_UART1_CLK_MODE_R, |
52650505 PW |
428 | .set_rate = &omap1_set_uart_rate, |
429 | .recalc = &omap1_uart_recalc, | |
430 | }; | |
431 | ||
fb2fc920 PW |
432 | /* |
433 | * XXX The enable_bit here is misused - it simply switches between 12MHz | |
434 | * and 48MHz. Reimplement with clksel. | |
435 | * | |
436 | * XXX SYSC register handling does not belong in the clock framework | |
437 | */ | |
52650505 PW |
438 | static struct uart_clk uart1_16xx = { |
439 | .clk = { | |
440 | .name = "uart1_ck", | |
fb2fc920 | 441 | .ops = &clkops_uart_16xx, |
52650505 PW |
442 | /* Direct from ULPD, no real parent */ |
443 | .parent = &armper_ck.clk, | |
444 | .rate = 48000000, | |
51c19541 | 445 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
52650505 | 446 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
fb2fc920 | 447 | .enable_bit = CONF_MOD_UART1_CLK_MODE_R, |
52650505 PW |
448 | }, |
449 | .sysc_addr = 0xfffb0054, | |
450 | }; | |
451 | ||
fb2fc920 PW |
452 | /* |
453 | * XXX The enable_bit here is misused - it simply switches between 12MHz | |
454 | * and 48MHz. Reimplement with clksel. | |
455 | * | |
456 | * XXX does this need SYSC register handling? | |
457 | */ | |
52650505 PW |
458 | static struct clk uart2_ck = { |
459 | .name = "uart2_ck", | |
460 | .ops = &clkops_null, | |
461 | /* Direct from ULPD, no real parent */ | |
462 | .parent = &armper_ck.clk, | |
463 | .rate = 12000000, | |
464 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
465 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
fb2fc920 | 466 | .enable_bit = CONF_MOD_UART2_CLK_MODE_R, |
52650505 PW |
467 | .set_rate = &omap1_set_uart_rate, |
468 | .recalc = &omap1_uart_recalc, | |
469 | }; | |
470 | ||
fb2fc920 PW |
471 | /* |
472 | * XXX The enable_bit here is misused - it simply switches between 12MHz | |
473 | * and 48MHz. Reimplement with clksel. | |
474 | * | |
475 | * XXX does this need SYSC register handling? | |
476 | */ | |
52650505 PW |
477 | static struct clk uart3_1510 = { |
478 | .name = "uart3_ck", | |
479 | .ops = &clkops_null, | |
480 | /* Direct from ULPD, no real parent */ | |
481 | .parent = &armper_ck.clk, | |
482 | .rate = 12000000, | |
483 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | |
484 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | |
fb2fc920 | 485 | .enable_bit = CONF_MOD_UART3_CLK_MODE_R, |
52650505 PW |
486 | .set_rate = &omap1_set_uart_rate, |
487 | .recalc = &omap1_uart_recalc, | |
488 | }; | |
489 | ||
fb2fc920 PW |
490 | /* |
491 | * XXX The enable_bit here is misused - it simply switches between 12MHz | |
492 | * and 48MHz. Reimplement with clksel. | |
493 | * | |
494 | * XXX SYSC register handling does not belong in the clock framework | |
495 | */ | |
52650505 PW |
496 | static struct uart_clk uart3_16xx = { |
497 | .clk = { | |
498 | .name = "uart3_ck", | |
fb2fc920 | 499 | .ops = &clkops_uart_16xx, |
52650505 PW |
500 | /* Direct from ULPD, no real parent */ |
501 | .parent = &armper_ck.clk, | |
502 | .rate = 48000000, | |
51c19541 | 503 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
52650505 | 504 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
fb2fc920 | 505 | .enable_bit = CONF_MOD_UART3_CLK_MODE_R, |
52650505 PW |
506 | }, |
507 | .sysc_addr = 0xfffb9854, | |
508 | }; | |
509 | ||
510 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |
511 | .name = "usb_clko", | |
512 | .ops = &clkops_generic, | |
513 | /* Direct from ULPD, no parent */ | |
514 | .rate = 6000000, | |
51c19541 | 515 | .flags = ENABLE_REG_32BIT, |
52650505 PW |
516 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
517 | .enable_bit = USB_MCLK_EN_BIT, | |
518 | }; | |
519 | ||
520 | static struct clk usb_hhc_ck1510 = { | |
521 | .name = "usb_hhc_ck", | |
522 | .ops = &clkops_generic, | |
523 | /* Direct from ULPD, no parent */ | |
524 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | |
51c19541 | 525 | .flags = ENABLE_REG_32BIT, |
52650505 PW |
526 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
527 | .enable_bit = USB_HOST_HHC_UHOST_EN, | |
528 | }; | |
529 | ||
530 | static struct clk usb_hhc_ck16xx = { | |
531 | .name = "usb_hhc_ck", | |
532 | .ops = &clkops_generic, | |
533 | /* Direct from ULPD, no parent */ | |
534 | .rate = 48000000, | |
535 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | |
51c19541 | 536 | .flags = ENABLE_REG_32BIT, |
52650505 | 537 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
fb2fc920 | 538 | .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT |
52650505 PW |
539 | }; |
540 | ||
541 | static struct clk usb_dc_ck = { | |
542 | .name = "usb_dc_ck", | |
543 | .ops = &clkops_generic, | |
544 | /* Direct from ULPD, no parent */ | |
545 | .rate = 48000000, | |
52650505 | 546 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
fb2fc920 | 547 | .enable_bit = USB_REQ_EN_SHIFT, |
52650505 PW |
548 | }; |
549 | ||
550 | static struct clk usb_dc_ck7xx = { | |
551 | .name = "usb_dc_ck", | |
552 | .ops = &clkops_generic, | |
553 | /* Direct from ULPD, no parent */ | |
554 | .rate = 48000000, | |
52650505 | 555 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
fb2fc920 | 556 | .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT, |
52650505 PW |
557 | }; |
558 | ||
8b8fbd39 CM |
559 | static struct clk uart1_7xx = { |
560 | .name = "uart1_ck", | |
561 | .ops = &clkops_generic, | |
562 | /* Direct from ULPD, no parent */ | |
563 | .rate = 12000000, | |
564 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
565 | .enable_bit = 9, | |
566 | }; | |
567 | ||
568 | static struct clk uart2_7xx = { | |
569 | .name = "uart2_ck", | |
570 | .ops = &clkops_generic, | |
571 | /* Direct from ULPD, no parent */ | |
572 | .rate = 12000000, | |
573 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | |
574 | .enable_bit = 11, | |
575 | }; | |
576 | ||
52650505 PW |
577 | static struct clk mclk_1510 = { |
578 | .name = "mclk", | |
579 | .ops = &clkops_generic, | |
580 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
581 | .rate = 12000000, | |
52650505 | 582 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
fb2fc920 | 583 | .enable_bit = SOFT_COM_MCKO_REQ_SHIFT, |
52650505 PW |
584 | }; |
585 | ||
586 | static struct clk mclk_16xx = { | |
587 | .name = "mclk", | |
588 | .ops = &clkops_generic, | |
589 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
590 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), | |
591 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | |
592 | .set_rate = &omap1_set_ext_clk_rate, | |
593 | .round_rate = &omap1_round_ext_clk_rate, | |
594 | .init = &omap1_init_ext_clk, | |
595 | }; | |
596 | ||
597 | static struct clk bclk_1510 = { | |
598 | .name = "bclk", | |
599 | .ops = &clkops_generic, | |
600 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
601 | .rate = 12000000, | |
52650505 PW |
602 | }; |
603 | ||
604 | static struct clk bclk_16xx = { | |
605 | .name = "bclk", | |
606 | .ops = &clkops_generic, | |
607 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | |
608 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), | |
609 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | |
610 | .set_rate = &omap1_set_ext_clk_rate, | |
611 | .round_rate = &omap1_round_ext_clk_rate, | |
612 | .init = &omap1_init_ext_clk, | |
613 | }; | |
614 | ||
615 | static struct clk mmc1_ck = { | |
b92c170d | 616 | .name = "mmc1_ck", |
52650505 PW |
617 | .ops = &clkops_generic, |
618 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | |
619 | .parent = &armper_ck.clk, | |
620 | .rate = 48000000, | |
51c19541 | 621 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
52650505 | 622 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
fb2fc920 | 623 | .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R, |
52650505 PW |
624 | }; |
625 | ||
fb2fc920 PW |
626 | /* |
627 | * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as | |
628 | * CONF_MOD_MCBSP3_AUXON ?? | |
629 | */ | |
52650505 | 630 | static struct clk mmc2_ck = { |
b92c170d | 631 | .name = "mmc2_ck", |
52650505 PW |
632 | .ops = &clkops_generic, |
633 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | |
634 | .parent = &armper_ck.clk, | |
635 | .rate = 48000000, | |
51c19541 | 636 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
52650505 PW |
637 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
638 | .enable_bit = 20, | |
639 | }; | |
640 | ||
641 | static struct clk mmc3_ck = { | |
b92c170d | 642 | .name = "mmc3_ck", |
52650505 PW |
643 | .ops = &clkops_generic, |
644 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | |
645 | .parent = &armper_ck.clk, | |
646 | .rate = 48000000, | |
51c19541 | 647 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
52650505 | 648 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
fb2fc920 | 649 | .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT, |
52650505 PW |
650 | }; |
651 | ||
652 | static struct clk virtual_ck_mpu = { | |
653 | .name = "mpu", | |
654 | .ops = &clkops_null, | |
655 | .parent = &arm_ck, /* Is smarter alias for */ | |
656 | .recalc = &followparent_recalc, | |
657 | .set_rate = &omap1_select_table_rate, | |
658 | .round_rate = &omap1_round_to_table_rate, | |
659 | }; | |
660 | ||
661 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | |
662 | remains active during MPU idle whenever this is enabled */ | |
663 | static struct clk i2c_fck = { | |
664 | .name = "i2c_fck", | |
52650505 PW |
665 | .ops = &clkops_null, |
666 | .flags = CLOCK_NO_IDLE_PARENT, | |
667 | .parent = &armxor_ck.clk, | |
668 | .recalc = &followparent_recalc, | |
669 | }; | |
670 | ||
671 | static struct clk i2c_ick = { | |
672 | .name = "i2c_ick", | |
52650505 PW |
673 | .ops = &clkops_null, |
674 | .flags = CLOCK_NO_IDLE_PARENT, | |
675 | .parent = &armper_ck.clk, | |
676 | .recalc = &followparent_recalc, | |
677 | }; | |
678 | ||
679 | /* | |
680 | * clkdev integration | |
681 | */ | |
682 | ||
683 | static struct omap_clk omap_clks[] = { | |
684 | /* non-ULPD clocks */ | |
685 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), | |
e8ae6b6e | 686 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
52650505 PW |
687 | /* CK_GEN1 clocks */ |
688 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | |
689 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | |
690 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | |
691 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | |
77640aab | 692 | CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310), |
52650505 PW |
693 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
694 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | |
695 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | |
696 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | |
697 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | |
698 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | |
699 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | |
700 | /* CK_GEN2 clocks */ | |
701 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | |
702 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | |
703 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | |
704 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | |
705 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | |
706 | /* CK_GEN3 clocks */ | |
707 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | |
708 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | |
709 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), | |
710 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | |
711 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | |
712 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | |
713 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | |
e8ae6b6e | 714 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
52650505 PW |
715 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), |
716 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | |
717 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | |
718 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), | |
719 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | |
720 | /* ULPD clocks */ | |
721 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | |
722 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | |
8b8fbd39 | 723 | CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX), |
52650505 | 724 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), |
8b8fbd39 | 725 | CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX), |
52650505 PW |
726 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), |
727 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | |
728 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | |
729 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | |
730 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | |
731 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | |
732 | CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), | |
733 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | |
734 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | |
735 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | |
736 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | |
737 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | |
738 | CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), | |
739 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | |
740 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | |
741 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | |
742 | /* Virtual clocks */ | |
743 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | |
f7bb0d9a BC |
744 | CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX), |
745 | CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX), | |
746 | CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX), | |
c5c4dce4 CM |
747 | CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX), |
748 | CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX), | |
749 | CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX), | |
750 | CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX), | |
52650505 PW |
751 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), |
752 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | |
753 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | |
754 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | |
755 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | |
756 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | |
757 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | |
758 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | |
759 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | |
760 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | |
761 | }; | |
762 | ||
763 | /* | |
764 | * init | |
765 | */ | |
766 | ||
e9b7086b TL |
767 | static void __init omap1_show_rates(void) |
768 | { | |
7852ec05 PW |
769 | pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", |
770 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | |
771 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | |
772 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | |
e9b7086b TL |
773 | } |
774 | ||
24ce2705 JK |
775 | u32 cpu_mask; |
776 | ||
52650505 PW |
777 | int __init omap1_clk_init(void) |
778 | { | |
779 | struct omap_clk *c; | |
52650505 | 780 | int crystal_type = 0; /* Default 12 MHz */ |
24ce2705 | 781 | u32 reg; |
52650505 PW |
782 | |
783 | #ifdef CONFIG_DEBUG_LL | |
784 | /* | |
785 | * Resets some clocks that may be left on from bootloader, | |
786 | * but leaves serial clocks on. | |
787 | */ | |
788 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | |
789 | #endif | |
790 | ||
791 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ | |
792 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | |
793 | omap_writew(reg, SOFT_REQ_REG); | |
794 | if (!cpu_is_omap15xx()) | |
795 | omap_writew(0, SOFT_REQ_REG2); | |
796 | ||
52650505 PW |
797 | /* By default all idlect1 clocks are allowed to idle */ |
798 | arm_idlect1_mask = ~0; | |
799 | ||
800 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | |
801 | clk_preinit(c->lk.clk); | |
802 | ||
803 | cpu_mask = 0; | |
24ce2705 JK |
804 | if (cpu_is_omap1710()) |
805 | cpu_mask |= CK_1710; | |
52650505 PW |
806 | if (cpu_is_omap16xx()) |
807 | cpu_mask |= CK_16XX; | |
808 | if (cpu_is_omap1510()) | |
809 | cpu_mask |= CK_1510; | |
810 | if (cpu_is_omap7xx()) | |
811 | cpu_mask |= CK_7XX; | |
812 | if (cpu_is_omap310()) | |
813 | cpu_mask |= CK_310; | |
814 | ||
815 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | |
816 | if (c->cpu & cpu_mask) { | |
817 | clkdev_add(&c->lk); | |
818 | clk_register(c->lk.clk); | |
819 | } | |
820 | ||
821 | /* Pointers to these clocks are needed by code in clock.c */ | |
822 | api_ck_p = clk_get(NULL, "api_ck"); | |
823 | ck_dpll1_p = clk_get(NULL, "ck_dpll1"); | |
824 | ck_ref_p = clk_get(NULL, "ck_ref"); | |
825 | ||
65ae65c9 JK |
826 | if (cpu_is_omap7xx()) |
827 | ck_ref.rate = 13000000; | |
828 | if (cpu_is_omap16xx() && crystal_type == 2) | |
52650505 | 829 | ck_ref.rate = 19200000; |
52650505 | 830 | |
7852ec05 PW |
831 | pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", |
832 | omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | |
52650505 PW |
833 | omap_readw(ARM_CKCTL)); |
834 | ||
835 | /* We want to be in syncronous scalable mode */ | |
836 | omap_writew(0x1000, ARM_SYSST); | |
837 | ||
e9b7086b TL |
838 | |
839 | /* | |
840 | * Initially use the values set by bootloader. Determine PLL rate and | |
841 | * recalculate dependent clocks as if kernel had changed PLL or | |
842 | * divisors. See also omap1_clk_late_init() that can reprogram dpll1 | |
843 | * after the SRAM is initialized. | |
52650505 PW |
844 | */ |
845 | { | |
846 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | |
847 | ||
848 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | |
849 | if (pll_ctl_val & 0x10) { | |
850 | /* PLL enabled, apply multiplier and divisor */ | |
851 | if (pll_ctl_val & 0xf80) | |
852 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | |
853 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | |
854 | } else { | |
855 | /* PLL disabled, apply bypass divisor */ | |
856 | switch (pll_ctl_val & 0xc) { | |
857 | case 0: | |
858 | break; | |
859 | case 0x4: | |
860 | ck_dpll1.rate /= 2; | |
861 | break; | |
862 | default: | |
863 | ck_dpll1.rate /= 4; | |
864 | break; | |
865 | } | |
866 | } | |
867 | } | |
52650505 PW |
868 | propagate_rate(&ck_dpll1); |
869 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | |
870 | propagate_rate(&ck_ref); | |
e9b7086b | 871 | omap1_show_rates(); |
65ae65c9 JK |
872 | if (machine_is_omap_perseus2() || machine_is_omap_fsample()) { |
873 | /* Select slicer output as OMAP input clock */ | |
874 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, | |
875 | OMAP7XX_PCC_UPLD_CTRL); | |
876 | } | |
52650505 PW |
877 | |
878 | /* Amstrad Delta wants BCLK high when inactive */ | |
879 | if (machine_is_ams_delta()) | |
880 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | |
881 | (1 << SDW_MCLK_INV_BIT), | |
882 | ULPD_CLOCK_CTRL); | |
883 | ||
884 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ | |
885 | /* (on 730, bit 13 must not be cleared) */ | |
886 | if (cpu_is_omap7xx()) | |
887 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | |
888 | else | |
889 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | |
890 | ||
891 | /* Put DSP/MPUI into reset until needed */ | |
892 | omap_writew(0, ARM_RSTCT1); | |
893 | omap_writew(1, ARM_RSTCT2); | |
894 | omap_writew(0x400, ARM_IDLECT1); | |
895 | ||
896 | /* | |
897 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | |
898 | * of the ARM_IDLECT2 register must be set to zero. The power-on | |
899 | * default value of this bit is one. | |
900 | */ | |
901 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | |
902 | ||
903 | /* | |
904 | * Only enable those clocks we will need, let the drivers | |
905 | * enable other clocks as necessary | |
906 | */ | |
907 | clk_enable(&armper_ck.clk); | |
908 | clk_enable(&armxor_ck.clk); | |
909 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | |
910 | ||
911 | if (cpu_is_omap15xx()) | |
912 | clk_enable(&arm_gpio_ck); | |
913 | ||
914 | return 0; | |
915 | } | |
e9b7086b TL |
916 | |
917 | #define OMAP1_DPLL1_SANE_VALUE 60000000 | |
918 | ||
919 | void __init omap1_clk_late_init(void) | |
920 | { | |
6560ee07 JK |
921 | unsigned long rate = ck_dpll1.rate; |
922 | ||
e9b7086b TL |
923 | /* Find the highest supported frequency and enable it */ |
924 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | |
925 | pr_err("System frequencies not set, using default. Check your config.\n"); | |
f9e5908f JK |
926 | /* |
927 | * Reprogramming the DPLL is tricky, it must be done from SRAM. | |
928 | */ | |
929 | omap_sram_reprogram_clock(0x2290, 0x0005); | |
e9b7086b TL |
930 | ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE; |
931 | } | |
932 | propagate_rate(&ck_dpll1); | |
933 | omap1_show_rates(); | |
6560ee07 | 934 | loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate); |
e9b7086b | 935 | } |