[deliverable/linux.git] / arch / arm / mach-omap1 / include / mach / hardware.h

/*
 * arch/arm/mach-omap1/include/mach/hardware.h
 *
 * Hardware definitions for TI OMAP processors and boards
 *
 * NOTE: Please put device driver specific defines into a separate header
 *	 file for each driver.
 *
 * Copyright (C) 2001 RidgeRun, Inc.
 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
 *
 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
 *                          and Dirk Behme <dirk.behme@de.bosch.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __ASM_ARCH_OMAP_HARDWARE_H
#define __ASM_ARCH_OMAP_HARDWARE_H

#include <asm/sizes.h>
#ifndef __ASSEMBLER__
#include <asm/types.h>
#include <plat/cpu.h>

/*
 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
 */
extern u8 omap_readb(u32 pa);
extern u16 omap_readw(u32 pa);
extern u32 omap_readl(u32 pa);
extern void omap_writeb(u8 v, u32 pa);
extern void omap_writew(u16 v, u32 pa);
extern void omap_writel(u32 v, u32 pa);

#include <plat/tc.h>

/* Almost all documentation for chip and board memory maps assumes
 * BM is clear.  Most devel boards have a switch to control booting
 * from NOR flash (using external chipselect 3) rather than mask ROM,
 * which uses BM to interchange the physical CS0 and CS3 addresses.
 */
static inline u32 omap_cs0m_phys(void)
{
	return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
			?  OMAP_CS3_PHYS : 0;
}

static inline u32 omap_cs3_phys(void)
{
	return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
			? 0 : OMAP_CS3_PHYS;
}

#endif	/* ifndef __ASSEMBLER__ */

#include <plat/serial.h>

/*
 * ---------------------------------------------------------------------------
 * Common definitions for all OMAP processors
 * NOTE: Put all processor or board specific parts to the special header
 *	 files.
 * ---------------------------------------------------------------------------
 */

/*
 * ----------------------------------------------------------------------------
 * Timers
 * ----------------------------------------------------------------------------
 */
#define OMAP_MPU_TIMER1_BASE	(0xfffec500)
#define OMAP_MPU_TIMER2_BASE	(0xfffec600)
#define OMAP_MPU_TIMER3_BASE	(0xfffec700)
#define MPU_TIMER_FREE		(1 << 6)
#define MPU_TIMER_CLOCK_ENABLE	(1 << 5)
#define MPU_TIMER_AR		(1 << 1)
#define MPU_TIMER_ST		(1 << 0)

/*
 * ----------------------------------------------------------------------------
 * Clocks
 * ----------------------------------------------------------------------------
 */
#define CLKGEN_REG_BASE		(0xfffece00)
#define ARM_CKCTL		(CLKGEN_REG_BASE + 0x0)
#define ARM_IDLECT1		(CLKGEN_REG_BASE + 0x4)
#define ARM_IDLECT2		(CLKGEN_REG_BASE + 0x8)
#define ARM_EWUPCT		(CLKGEN_REG_BASE + 0xC)
#define ARM_RSTCT1		(CLKGEN_REG_BASE + 0x10)
#define ARM_RSTCT2		(CLKGEN_REG_BASE + 0x14)
#define ARM_SYSST		(CLKGEN_REG_BASE + 0x18)
#define ARM_IDLECT3		(CLKGEN_REG_BASE + 0x24)

#define CK_RATEF		1
#define CK_IDLEF		2
#define CK_ENABLEF		4
#define CK_SELECTF		8
#define SETARM_IDLE_SHIFT

/* DPLL control registers */
#define DPLL_CTL		(0xfffecf00)

/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
#define DSP_CKCTL		(DSP_CONFIG_REG_BASE + 0x0)
#define DSP_IDLECT1		(DSP_CONFIG_REG_BASE + 0x4)
#define DSP_IDLECT2		(DSP_CONFIG_REG_BASE + 0x8)
#define DSP_RSTCT2		(DSP_CONFIG_REG_BASE + 0x14)

/*
 * ---------------------------------------------------------------------------
 * UPLD
 * ---------------------------------------------------------------------------
 */
#define ULPD_REG_BASE		(0xfffe0800)
#define ULPD_IT_STATUS		(ULPD_REG_BASE + 0x14)
#define ULPD_SETUP_ANALOG_CELL_3	(ULPD_REG_BASE + 0x24)
#define ULPD_CLOCK_CTRL		(ULPD_REG_BASE + 0x30)
#	define DIS_USB_PVCI_CLK		(1 << 5)	/* no USB/FAC synch */
#	define USB_MCLK_EN		(1 << 4)	/* enable W4_USB_CLKO */
#define ULPD_SOFT_REQ		(ULPD_REG_BASE + 0x34)
#	define SOFT_UDC_REQ		(1 << 4)
#	define SOFT_USB_CLK_REQ		(1 << 3)
#	define SOFT_DPLL_REQ		(1 << 0)
#define ULPD_DPLL_CTRL		(ULPD_REG_BASE + 0x3c)
#define ULPD_STATUS_REQ		(ULPD_REG_BASE + 0x40)
#define ULPD_APLL_CTRL		(ULPD_REG_BASE + 0x4c)
#define ULPD_POWER_CTRL		(ULPD_REG_BASE + 0x50)
#define ULPD_SOFT_DISABLE_REQ_REG	(ULPD_REG_BASE + 0x68)
#	define DIS_MMC2_DPLL_REQ	(1 << 11)
#	define DIS_MMC1_DPLL_REQ	(1 << 10)
#	define DIS_UART3_DPLL_REQ	(1 << 9)
#	define DIS_UART2_DPLL_REQ	(1 << 8)
#	define DIS_UART1_DPLL_REQ	(1 << 7)
#	define DIS_USB_HOST_DPLL_REQ	(1 << 6)
#define ULPD_SDW_CLK_DIV_CTRL_SEL	(ULPD_REG_BASE + 0x74)
#define ULPD_CAM_CLK_CTRL	(ULPD_REG_BASE + 0x7c)

/*
 * ---------------------------------------------------------------------------
 * Watchdog timer
 * ---------------------------------------------------------------------------
 */

/* Watchdog timer within the OMAP3.2 gigacell */
#define OMAP_MPU_WATCHDOG_BASE	(0xfffec800)
#define OMAP_WDT_TIMER		(OMAP_MPU_WATCHDOG_BASE + 0x0)
#define OMAP_WDT_LOAD_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_READ_TIM	(OMAP_MPU_WATCHDOG_BASE + 0x4)
#define OMAP_WDT_TIMER_MODE	(OMAP_MPU_WATCHDOG_BASE + 0x8)

/*
 * ---------------------------------------------------------------------------
 * Interrupts
 * ---------------------------------------------------------------------------
 */
#ifdef CONFIG_ARCH_OMAP1

/*
 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
 * or something similar.. -- PFM.
 */

#define OMAP_IH1_BASE		0xfffecb00
#define OMAP_IH2_BASE		0xfffe0000

#define OMAP_IH1_ITR		(OMAP_IH1_BASE + 0x00)
#define OMAP_IH1_MIR		(OMAP_IH1_BASE + 0x04)
#define OMAP_IH1_SIR_IRQ	(OMAP_IH1_BASE + 0x10)
#define OMAP_IH1_SIR_FIQ	(OMAP_IH1_BASE + 0x14)
#define OMAP_IH1_CONTROL	(OMAP_IH1_BASE + 0x18)
#define OMAP_IH1_ILR0		(OMAP_IH1_BASE + 0x1c)
#define OMAP_IH1_ISR		(OMAP_IH1_BASE + 0x9c)

#define OMAP_IH2_ITR		(OMAP_IH2_BASE + 0x00)
#define OMAP_IH2_MIR		(OMAP_IH2_BASE + 0x04)
#define OMAP_IH2_SIR_IRQ	(OMAP_IH2_BASE + 0x10)
#define OMAP_IH2_SIR_FIQ	(OMAP_IH2_BASE + 0x14)
#define OMAP_IH2_CONTROL	(OMAP_IH2_BASE + 0x18)
#define OMAP_IH2_ILR0		(OMAP_IH2_BASE + 0x1c)
#define OMAP_IH2_ISR		(OMAP_IH2_BASE + 0x9c)

#define IRQ_ITR_REG_OFFSET	0x00
#define IRQ_MIR_REG_OFFSET	0x04
#define IRQ_SIR_IRQ_REG_OFFSET	0x10
#define IRQ_SIR_FIQ_REG_OFFSET	0x14
#define IRQ_CONTROL_REG_OFFSET	0x18
#define IRQ_ISR_REG_OFFSET	0x9c
#define IRQ_ILR0_REG_OFFSET	0x1c
#define IRQ_GMR_REG_OFFSET	0xa0

#endif

/*
 * ----------------------------------------------------------------------------
 * System control registers
 * ----------------------------------------------------------------------------
 */
#define MOD_CONF_CTRL_0		0xfffe1080
#define MOD_CONF_CTRL_1		0xfffe1110

/*
 * ----------------------------------------------------------------------------
 * Pin multiplexing registers
 * ----------------------------------------------------------------------------
 */
#define FUNC_MUX_CTRL_0		0xfffe1000
#define FUNC_MUX_CTRL_1		0xfffe1004
#define FUNC_MUX_CTRL_2		0xfffe1008
#define COMP_MODE_CTRL_0	0xfffe100c
#define FUNC_MUX_CTRL_3		0xfffe1010
#define FUNC_MUX_CTRL_4		0xfffe1014
#define FUNC_MUX_CTRL_5		0xfffe1018
#define FUNC_MUX_CTRL_6		0xfffe101C
#define FUNC_MUX_CTRL_7		0xfffe1020
#define FUNC_MUX_CTRL_8		0xfffe1024
#define FUNC_MUX_CTRL_9		0xfffe1028
#define FUNC_MUX_CTRL_A		0xfffe102C
#define FUNC_MUX_CTRL_B		0xfffe1030
#define FUNC_MUX_CTRL_C		0xfffe1034
#define FUNC_MUX_CTRL_D		0xfffe1038
#define PULL_DWN_CTRL_0		0xfffe1040
#define PULL_DWN_CTRL_1		0xfffe1044
#define PULL_DWN_CTRL_2		0xfffe1048
#define PULL_DWN_CTRL_3		0xfffe104c
#define PULL_DWN_CTRL_4		0xfffe10ac

/* OMAP-1610 specific multiplexing registers */
#define FUNC_MUX_CTRL_E		0xfffe1090
#define FUNC_MUX_CTRL_F		0xfffe1094
#define FUNC_MUX_CTRL_10	0xfffe1098
#define FUNC_MUX_CTRL_11	0xfffe109c
#define FUNC_MUX_CTRL_12	0xfffe10a0
#define PU_PD_SEL_0		0xfffe10b4
#define PU_PD_SEL_1		0xfffe10b8
#define PU_PD_SEL_2		0xfffe10bc
#define PU_PD_SEL_3		0xfffe10c0
#define PU_PD_SEL_4		0xfffe10c4

/* Timer32K for 1610 and 1710*/
#define OMAP_TIMER32K_BASE	0xFFFBC400

/*
 * ---------------------------------------------------------------------------
 * TIPB bus interface
 * ---------------------------------------------------------------------------
 */
#define TIPB_PUBLIC_CNTL_BASE		0xfffed300
#define MPU_PUBLIC_TIPB_CNTL		(TIPB_PUBLIC_CNTL_BASE + 0x8)
#define TIPB_PRIVATE_CNTL_BASE		0xfffeca00
#define MPU_PRIVATE_TIPB_CNTL		(TIPB_PRIVATE_CNTL_BASE + 0x8)

/*
 * ----------------------------------------------------------------------------
 * MPUI interface
 * ----------------------------------------------------------------------------
 */
#define MPUI_BASE			(0xfffec900)
#define MPUI_CTRL			(MPUI_BASE + 0x0)
#define MPUI_DEBUG_ADDR			(MPUI_BASE + 0x4)
#define MPUI_DEBUG_DATA			(MPUI_BASE + 0x8)
#define MPUI_DEBUG_FLAG			(MPUI_BASE + 0xc)
#define MPUI_STATUS_REG			(MPUI_BASE + 0x10)
#define MPUI_DSP_STATUS			(MPUI_BASE + 0x14)
#define MPUI_DSP_BOOT_CONFIG		(MPUI_BASE + 0x18)
#define MPUI_DSP_API_CONFIG		(MPUI_BASE + 0x1c)

/*
 * ----------------------------------------------------------------------------
 * LED Pulse Generator
 * ----------------------------------------------------------------------------
 */
#define OMAP_LPG1_BASE			0xfffbd000
#define OMAP_LPG2_BASE			0xfffbd800
#define OMAP_LPG1_LCR			(OMAP_LPG1_BASE + 0x00)
#define OMAP_LPG1_PMR			(OMAP_LPG1_BASE + 0x04)
#define OMAP_LPG2_LCR			(OMAP_LPG2_BASE + 0x00)
#define OMAP_LPG2_PMR			(OMAP_LPG2_BASE + 0x04)

/*
 * ----------------------------------------------------------------------------
 * Pulse-Width Light
 * ----------------------------------------------------------------------------
 */
#define OMAP_PWL_BASE			0xfffb5800
#define OMAP_PWL_ENABLE			(OMAP_PWL_BASE + 0x00)
#define OMAP_PWL_CLK_ENABLE		(OMAP_PWL_BASE + 0x04)

/*
 * ---------------------------------------------------------------------------
 * Processor specific defines
 * ---------------------------------------------------------------------------
 */

#include "omap7xx.h"
#include "omap1510.h"
#include "omap16xx.h"

#endif	/* __ASM_ARCH_OMAP_HARDWARE_H */
Commit	Line	Data
3eff851b TL	1	/*
3eff851b TL	2	* arch/arm/mach-omap1/include/mach/hardware.h
dbc04161 TL	3	*
	4	* Hardware definitions for TI OMAP processors and boards
	5	*
	6	* NOTE: Please put device driver specific defines into a separate header
	7	* file for each driver.
	8	*
	9	* Copyright (C) 2001 RidgeRun, Inc.
	10	* Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
	11	*
	12	* Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
	13	* and Dirk Behme <dirk.behme@de.bosch.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms of the GNU General Public License as published by the
	17	* Free Software Foundation; either version 2 of the License, or (at your
	18	* option) any later version.
	19	*
	20	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	21	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	22	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	23	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	24	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	25	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	26	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	29	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	30	*
	31	* You should have received a copy of the GNU General Public License along
	32	* with this program; if not, write to the Free Software Foundation, Inc.,
	33	* 675 Mass Ave, Cambridge, MA 02139, USA.
3eff851b TL	34	*/
3eff851b TL	35
dbc04161 TL	36	#ifndef __ASM_ARCH_OMAP_HARDWARE_H
dbc04161 TL	37	#define __ASM_ARCH_OMAP_HARDWARE_H
2c799cef	38
dbc04161	39	#include <asm/sizes.h>
2c799cef	40	#ifndef __ASSEMBLER__
dbc04161 TL	41	#include <asm/types.h>
	42	#include <plat/cpu.h>
	43
2c799cef TL	44	/*
	45	* NOTE: Please use ioremap + __raw_read/write where possible instead of these
	46	*/
	47	extern u8 omap_readb(u32 pa);
	48	extern u16 omap_readw(u32 pa);
	49	extern u32 omap_readl(u32 pa);
	50	extern void omap_writeb(u8 v, u32 pa);
	51	extern void omap_writew(u16 v, u32 pa);
	52	extern void omap_writel(u32 v, u32 pa);
	53
	54	#include <plat/tc.h>
	55
	56	/* Almost all documentation for chip and board memory maps assumes
	57	* BM is clear. Most devel boards have a switch to control booting
	58	* from NOR flash (using external chipselect 3) rather than mask ROM,
	59	* which uses BM to interchange the physical CS0 and CS3 addresses.
	60	*/
	61	static inline u32 omap_cs0m_phys(void)
	62	{
	63	return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
	64	? OMAP_CS3_PHYS : 0;
	65	}
	66
	67	static inline u32 omap_cs3_phys(void)
	68	{
	69	return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
	70	? 0 : OMAP_CS3_PHYS;
	71	}
	72
dbc04161 TL	73	#endif /* ifndef __ASSEMBLER__ */
	74
	75	#include <plat/serial.h>
	76
	77	/*
	78	* ---------------------------------------------------------------------------
	79	* Common definitions for all OMAP processors
	80	* NOTE: Put all processor or board specific parts to the special header
	81	* files.
	82	* ---------------------------------------------------------------------------
	83	*/
	84
	85	/*
	86	* ----------------------------------------------------------------------------
	87	* Timers
	88	* ----------------------------------------------------------------------------
	89	*/
	90	#define OMAP_MPU_TIMER1_BASE (0xfffec500)
	91	#define OMAP_MPU_TIMER2_BASE (0xfffec600)
	92	#define OMAP_MPU_TIMER3_BASE (0xfffec700)
	93	#define MPU_TIMER_FREE (1 << 6)
	94	#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
	95	#define MPU_TIMER_AR (1 << 1)
	96	#define MPU_TIMER_ST (1 << 0)
	97
	98	/*
	99	* ----------------------------------------------------------------------------
	100	* Clocks
	101	* ----------------------------------------------------------------------------
	102	*/
	103	#define CLKGEN_REG_BASE (0xfffece00)
	104	#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
	105	#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
	106	#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
	107	#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
	108	#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
	109	#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
	110	#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
	111	#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
	112
	113	#define CK_RATEF 1
	114	#define CK_IDLEF 2
	115	#define CK_ENABLEF 4
	116	#define CK_SELECTF 8
	117	#define SETARM_IDLE_SHIFT
	118
	119	/* DPLL control registers */
	120	#define DPLL_CTL (0xfffecf00)
	121
	122	/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
	123	#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000)
	124	#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
	125	#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
	126	#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
	127	#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14)
	128
	129	/*
	130	* ---------------------------------------------------------------------------
	131	* UPLD
	132	* ---------------------------------------------------------------------------
	133	*/
	134	#define ULPD_REG_BASE (0xfffe0800)
	135	#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
	136	#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
137	#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
138	# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
139	# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
140	#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34)
141	# define SOFT_UDC_REQ (1 << 4)
142	# define SOFT_USB_CLK_REQ (1 << 3)
143	# define SOFT_DPLL_REQ (1 << 0)
144	#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c)
145	#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40)
146	#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c)
147	#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50)
148	#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68)
149	# define DIS_MMC2_DPLL_REQ (1 << 11)
150	# define DIS_MMC1_DPLL_REQ (1 << 10)
151	# define DIS_UART3_DPLL_REQ (1 << 9)
152	# define DIS_UART2_DPLL_REQ (1 << 8)
153	# define DIS_UART1_DPLL_REQ (1 << 7)
154	# define DIS_USB_HOST_DPLL_REQ (1 << 6)
155	#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74)
156	#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c)
157
158	/*
159	* ---------------------------------------------------------------------------
160	* Watchdog timer
161	* ---------------------------------------------------------------------------
162	*/
163
164	/* Watchdog timer within the OMAP3.2 gigacell */
165	#define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
166	#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
167	#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
168	#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
169	#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
170
171	/*
172	* ---------------------------------------------------------------------------
173	* Interrupts
174	* ---------------------------------------------------------------------------
175	*/
176	#ifdef CONFIG_ARCH_OMAP1
177
178	/*
179	* XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
180	* or something similar.. -- PFM.
181	*/
182
183	#define OMAP_IH1_BASE 0xfffecb00
184	#define OMAP_IH2_BASE 0xfffe0000
185
186	#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
187	#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
188	#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
189	#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
190	#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
191	#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
192	#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
193
194	#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
195	#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
196	#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
197	#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
198	#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
199	#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
200	#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
201
202	#define IRQ_ITR_REG_OFFSET 0x00
203	#define IRQ_MIR_REG_OFFSET 0x04
204	#define IRQ_SIR_IRQ_REG_OFFSET 0x10
205	#define IRQ_SIR_FIQ_REG_OFFSET 0x14
206	#define IRQ_CONTROL_REG_OFFSET 0x18
207	#define IRQ_ISR_REG_OFFSET 0x9c
208	#define IRQ_ILR0_REG_OFFSET 0x1c
209	#define IRQ_GMR_REG_OFFSET 0xa0
210
2c799cef	211	#endif
2c799cef	212
dbc04161 TL	213	/*
	214	* ----------------------------------------------------------------------------
	215	* System control registers
	216	* ----------------------------------------------------------------------------
	217	*/
	218	#define MOD_CONF_CTRL_0 0xfffe1080
	219	#define MOD_CONF_CTRL_1 0xfffe1110
	220
	221	/*
	222	* ----------------------------------------------------------------------------
	223	* Pin multiplexing registers
	224	* ----------------------------------------------------------------------------
	225	*/
	226	#define FUNC_MUX_CTRL_0 0xfffe1000
	227	#define FUNC_MUX_CTRL_1 0xfffe1004
	228	#define FUNC_MUX_CTRL_2 0xfffe1008
	229	#define COMP_MODE_CTRL_0 0xfffe100c
	230	#define FUNC_MUX_CTRL_3 0xfffe1010
	231	#define FUNC_MUX_CTRL_4 0xfffe1014
	232	#define FUNC_MUX_CTRL_5 0xfffe1018
	233	#define FUNC_MUX_CTRL_6 0xfffe101C
	234	#define FUNC_MUX_CTRL_7 0xfffe1020
	235	#define FUNC_MUX_CTRL_8 0xfffe1024
	236	#define FUNC_MUX_CTRL_9 0xfffe1028
	237	#define FUNC_MUX_CTRL_A 0xfffe102C
	238	#define FUNC_MUX_CTRL_B 0xfffe1030
	239	#define FUNC_MUX_CTRL_C 0xfffe1034
	240	#define FUNC_MUX_CTRL_D 0xfffe1038
	241	#define PULL_DWN_CTRL_0 0xfffe1040
	242	#define PULL_DWN_CTRL_1 0xfffe1044
	243	#define PULL_DWN_CTRL_2 0xfffe1048
	244	#define PULL_DWN_CTRL_3 0xfffe104c
	245	#define PULL_DWN_CTRL_4 0xfffe10ac
	246
	247	/* OMAP-1610 specific multiplexing registers */
	248	#define FUNC_MUX_CTRL_E 0xfffe1090
	249	#define FUNC_MUX_CTRL_F 0xfffe1094
	250	#define FUNC_MUX_CTRL_10 0xfffe1098
	251	#define FUNC_MUX_CTRL_11 0xfffe109c
	252	#define FUNC_MUX_CTRL_12 0xfffe10a0
	253	#define PU_PD_SEL_0 0xfffe10b4
	254	#define PU_PD_SEL_1 0xfffe10b8
	255	#define PU_PD_SEL_2 0xfffe10bc
	256	#define PU_PD_SEL_3 0xfffe10c0
	257	#define PU_PD_SEL_4 0xfffe10c4
	258
	259	/* Timer32K for 1610 and 1710*/
	260	#define OMAP_TIMER32K_BASE 0xFFFBC400
	261
	262	/*
	263	* ---------------------------------------------------------------------------
	264	* TIPB bus interface
	265	* ---------------------------------------------------------------------------
	266	*/
	267	#define TIPB_PUBLIC_CNTL_BASE 0xfffed300
	268	#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
	269	#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
	270	#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
	271
	272	/*
	273	* ----------------------------------------------------------------------------
	274	* MPUI interface
	275	* ----------------------------------------------------------------------------
	276	*/
277	#define MPUI_BASE (0xfffec900)
278	#define MPUI_CTRL (MPUI_BASE + 0x0)
279	#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
280	#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
281	#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
282	#define MPUI_STATUS_REG (MPUI_BASE + 0x10)
283	#define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
284	#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
285	#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
286
287	/*
288	* ----------------------------------------------------------------------------
289	* LED Pulse Generator
290	* ----------------------------------------------------------------------------
291	*/
292	#define OMAP_LPG1_BASE 0xfffbd000
293	#define OMAP_LPG2_BASE 0xfffbd800
294	#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
295	#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
296	#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
297	#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
298
299	/*
300	* ----------------------------------------------------------------------------
301	* Pulse-Width Light
302	* ----------------------------------------------------------------------------
303	*/
304	#define OMAP_PWL_BASE 0xfffb5800
305	#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00)
306	#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04)
307
308	/*
309	* ---------------------------------------------------------------------------
310	* Processor specific defines
311	* ---------------------------------------------------------------------------
312	*/
313
68cb700c TL	314	#include "omap7xx.h"
	315	#include "omap1510.h"
	316	#include "omap16xx.h"
dbc04161 TL	317
dbc04161 TL	318	#endif /* __ASM_ARCH_OMAP_HARDWARE_H */