Commit | Line | Data |
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1da177e4 | 1 | /* |
3b59b6be | 2 | * linux/arch/arm/mach-omap1/time.c |
1da177e4 LT |
3 | * |
4 | * OMAP Timers | |
5 | * | |
6 | * Copyright (C) 2004 Nokia Corporation | |
b3402cf5 | 7 | * Partial timer rewrite and additional dynamic tick timer support by |
1da177e4 LT |
8 | * Tony Lindgen <tony@atomide.com> and |
9 | * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
10 | * | |
11 | * MPU timer code based on the older MPU timer code for OMAP | |
12 | * Copyright (C) 2000 RidgeRun, Inc. | |
13 | * Author: Greg Lonnon <glonnon@ridgerun.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
30 | * | |
31 | * You should have received a copy of the GNU General Public License along | |
32 | * with this program; if not, write to the Free Software Foundation, Inc., | |
33 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
34 | */ | |
35 | ||
1da177e4 LT |
36 | #include <linux/kernel.h> |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
1da177e4 | 40 | #include <linux/spinlock.h> |
075192ae KH |
41 | #include <linux/clk.h> |
42 | #include <linux/err.h> | |
43 | #include <linux/clocksource.h> | |
44 | #include <linux/clockchips.h> | |
fced80c7 | 45 | #include <linux/io.h> |
38ff87f7 | 46 | #include <linux/sched_clock.h> |
1da177e4 | 47 | |
1da177e4 | 48 | #include <asm/irq.h> |
f376ea17 | 49 | |
2e3ee9f4 | 50 | #include <mach/hardware.h> |
1da177e4 LT |
51 | #include <asm/mach/irq.h> |
52 | #include <asm/mach/time.h> | |
53 | ||
2e3ee9f4 | 54 | #include "iomap.h" |
4e65331c | 55 | #include "common.h" |
1da177e4 | 56 | |
05b5ca9b TL |
57 | #ifdef CONFIG_OMAP_MPU_TIMER |
58 | ||
1da177e4 LT |
59 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE |
60 | #define OMAP_MPU_TIMER_OFFSET 0x100 | |
61 | ||
1da177e4 LT |
62 | typedef struct { |
63 | u32 cntl; /* CNTL_TIMER, R/W */ | |
64 | u32 load_tim; /* LOAD_TIM, W */ | |
65 | u32 read_tim; /* READ_TIM, R */ | |
66 | } omap_mpu_timer_regs_t; | |
67 | ||
94113260 | 68 | #define omap_mpu_timer_base(n) \ |
111c7751 | 69 | ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ |
1da177e4 LT |
70 | (n)*OMAP_MPU_TIMER_OFFSET)) |
71 | ||
f376ea17 | 72 | static inline unsigned long notrace omap_mpu_timer_read(int nr) |
1da177e4 | 73 | { |
111c7751 RK |
74 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
75 | return readl(&timer->read_tim); | |
1da177e4 LT |
76 | } |
77 | ||
075192ae | 78 | static inline void omap_mpu_set_autoreset(int nr) |
1da177e4 | 79 | { |
111c7751 | 80 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
1da177e4 | 81 | |
111c7751 | 82 | writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); |
1da177e4 LT |
83 | } |
84 | ||
075192ae | 85 | static inline void omap_mpu_remove_autoreset(int nr) |
1da177e4 | 86 | { |
111c7751 | 87 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
1da177e4 | 88 | |
111c7751 | 89 | writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); |
1da177e4 LT |
90 | } |
91 | ||
075192ae KH |
92 | static inline void omap_mpu_timer_start(int nr, unsigned long load_val, |
93 | int autoreset) | |
94 | { | |
111c7751 RK |
95 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
96 | unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST; | |
075192ae | 97 | |
111c7751 RK |
98 | if (autoreset) |
99 | timerflags |= MPU_TIMER_AR; | |
075192ae | 100 | |
111c7751 | 101 | writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); |
075192ae | 102 | udelay(1); |
111c7751 | 103 | writel(load_val, &timer->load_tim); |
075192ae | 104 | udelay(1); |
111c7751 | 105 | writel(timerflags, &timer->cntl); |
075192ae | 106 | } |
1da177e4 | 107 | |
06cad098 KH |
108 | static inline void omap_mpu_timer_stop(int nr) |
109 | { | |
111c7751 | 110 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr); |
06cad098 | 111 | |
111c7751 | 112 | writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); |
06cad098 KH |
113 | } |
114 | ||
1da177e4 | 115 | /* |
075192ae KH |
116 | * --------------------------------------------------------------------------- |
117 | * MPU timer 1 ... count down to zero, interrupt, reload | |
118 | * --------------------------------------------------------------------------- | |
1da177e4 | 119 | */ |
075192ae | 120 | static int omap_mpu_set_next_event(unsigned long cycles, |
06cad098 | 121 | struct clock_event_device *evt) |
1da177e4 | 122 | { |
075192ae KH |
123 | omap_mpu_timer_start(0, cycles, 0); |
124 | return 0; | |
125 | } | |
1da177e4 | 126 | |
29105e10 | 127 | static int omap_mpu_set_oneshot(struct clock_event_device *evt) |
075192ae | 128 | { |
29105e10 VK |
129 | omap_mpu_timer_stop(0); |
130 | omap_mpu_remove_autoreset(0); | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static int omap_mpu_set_periodic(struct clock_event_device *evt) | |
135 | { | |
136 | omap_mpu_set_autoreset(0); | |
137 | return 0; | |
1da177e4 LT |
138 | } |
139 | ||
075192ae | 140 | static struct clock_event_device clockevent_mpu_timer1 = { |
29105e10 VK |
141 | .name = "mpu_timer1", |
142 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
143 | CLOCK_EVT_FEAT_ONESHOT, | |
144 | .set_next_event = omap_mpu_set_next_event, | |
145 | .set_state_periodic = omap_mpu_set_periodic, | |
146 | .set_state_oneshot = omap_mpu_set_oneshot, | |
075192ae KH |
147 | }; |
148 | ||
149 | static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id) | |
1da177e4 | 150 | { |
075192ae | 151 | struct clock_event_device *evt = &clockevent_mpu_timer1; |
1da177e4 | 152 | |
075192ae | 153 | evt->event_handler(evt); |
1da177e4 LT |
154 | |
155 | return IRQ_HANDLED; | |
156 | } | |
157 | ||
075192ae KH |
158 | static struct irqaction omap_mpu_timer1_irq = { |
159 | .name = "mpu_timer1", | |
fe806d04 | 160 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
075192ae | 161 | .handler = omap_mpu_timer1_interrupt, |
1da177e4 LT |
162 | }; |
163 | ||
075192ae KH |
164 | static __init void omap_init_mpu_timer(unsigned long rate) |
165 | { | |
075192ae KH |
166 | setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); |
167 | omap_mpu_timer_start(0, (rate / HZ) - 1, 1); | |
168 | ||
320ab2b0 | 169 | clockevent_mpu_timer1.cpumask = cpumask_of(0); |
838a2ae8 SG |
170 | clockevents_config_and_register(&clockevent_mpu_timer1, rate, |
171 | 1, -1); | |
075192ae KH |
172 | } |
173 | ||
174 | ||
175 | /* | |
176 | * --------------------------------------------------------------------------- | |
177 | * MPU timer 2 ... free running 32-bit clock source and scheduler clock | |
178 | * --------------------------------------------------------------------------- | |
179 | */ | |
180 | ||
50f6dca6 | 181 | static u64 notrace omap_mpu_read_sched_clock(void) |
f376ea17 | 182 | { |
2f0778af | 183 | return ~omap_mpu_timer_read(1); |
f376ea17 TL |
184 | } |
185 | ||
075192ae KH |
186 | static void __init omap_init_clocksource(unsigned long rate) |
187 | { | |
933e54a5 | 188 | omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1); |
075192ae KH |
189 | static char err[] __initdata = KERN_ERR |
190 | "%s: can't register clocksource!\n"; | |
191 | ||
075192ae | 192 | omap_mpu_timer_start(1, ~0, 1); |
50f6dca6 | 193 | sched_clock_register(omap_mpu_read_sched_clock, 32, rate); |
075192ae | 194 | |
933e54a5 RK |
195 | if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, |
196 | 300, 32, clocksource_mmio_readl_down)) | |
197 | printk(err, "mpu_timer2"); | |
1da177e4 LT |
198 | } |
199 | ||
05b5ca9b | 200 | static void __init omap_mpu_timer_init(void) |
1da177e4 | 201 | { |
075192ae KH |
202 | struct clk *ck_ref = clk_get(NULL, "ck_ref"); |
203 | unsigned long rate; | |
204 | ||
205 | BUG_ON(IS_ERR(ck_ref)); | |
206 | ||
207 | rate = clk_get_rate(ck_ref); | |
208 | clk_put(ck_ref); | |
209 | ||
210 | /* PTV = 0 */ | |
211 | rate /= 2; | |
212 | ||
213 | omap_init_mpu_timer(rate); | |
214 | omap_init_clocksource(rate); | |
05b5ca9b TL |
215 | } |
216 | ||
217 | #else | |
218 | static inline void omap_mpu_timer_init(void) | |
219 | { | |
220 | pr_err("Bogus timer, should not happen\n"); | |
221 | } | |
222 | #endif /* CONFIG_OMAP_MPU_TIMER */ | |
223 | ||
05b5ca9b TL |
224 | /* |
225 | * --------------------------------------------------------------------------- | |
226 | * Timer initialization | |
227 | * --------------------------------------------------------------------------- | |
228 | */ | |
6bb27d73 | 229 | void __init omap1_timer_init(void) |
05b5ca9b | 230 | { |
18799911 | 231 | if (omap_32k_timer_init() != 0) |
05b5ca9b | 232 | omap_mpu_timer_init(); |
1da177e4 | 233 | } |