[deliverable/linux.git] / arch / arm / mach-omap1 / time.c

/*
 * linux/arch/arm/mach-omap1/time.c
 *
 * OMAP Timers
 *
 * Copyright (C) 2004 Nokia Corporation
 * Partial timer rewrite and additional dynamic tick timer support by
 * Tony Lindgen <tony@atomide.com> and
 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
 *
 * MPU timer code based on the older MPU timer code for OMAP
 * Copyright (C) 2000 RidgeRun, Inc.
 * Author: Greg Lonnon <glonnon@ridgerun.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/sched.h>

#include <asm/system.h>
#include <mach/hardware.h>
#include <asm/leds.h>
#include <asm/irq.h>
#include <asm/sched_clock.h>

#include <asm/mach/irq.h>
#include <asm/mach/time.h>

#include <plat/common.h>

#ifdef CONFIG_OMAP_MPU_TIMER

#define OMAP_MPU_TIMER_BASE		OMAP_MPU_TIMER1_BASE
#define OMAP_MPU_TIMER_OFFSET		0x100

typedef struct {
	u32 cntl;			/* CNTL_TIMER, R/W */
	u32 load_tim;			/* LOAD_TIM,   W */
	u32 read_tim;			/* READ_TIM,   R */
} omap_mpu_timer_regs_t;

#define omap_mpu_timer_base(n)							\
((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE +	\
				 (n)*OMAP_MPU_TIMER_OFFSET))

static inline unsigned long notrace omap_mpu_timer_read(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	return timer->read_tim;
}

static inline void omap_mpu_set_autoreset(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);

	timer->cntl = timer->cntl | MPU_TIMER_AR;
}

static inline void omap_mpu_remove_autoreset(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);

	timer->cntl = timer->cntl & ~MPU_TIMER_AR;
}

static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
					int autoreset)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);

	if (autoreset) timerflags |= MPU_TIMER_AR;

	timer->cntl = MPU_TIMER_CLOCK_ENABLE;
	udelay(1);
	timer->load_tim = load_val;
        udelay(1);
	timer->cntl = timerflags;
}

static inline void omap_mpu_timer_stop(int nr)
{
	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);

	timer->cntl &= ~MPU_TIMER_ST;
}

/*
 * ---------------------------------------------------------------------------
 * MPU timer 1 ... count down to zero, interrupt, reload
 * ---------------------------------------------------------------------------
 */
static int omap_mpu_set_next_event(unsigned long cycles,
				   struct clock_event_device *evt)
{
	omap_mpu_timer_start(0, cycles, 0);
	return 0;
}

static void omap_mpu_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		omap_mpu_set_autoreset(0);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		omap_mpu_timer_stop(0);
		omap_mpu_remove_autoreset(0);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device clockevent_mpu_timer1 = {
	.name		= "mpu_timer1",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.shift		= 32,
	.set_next_event	= omap_mpu_set_next_event,
	.set_mode	= omap_mpu_set_mode,
};

static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = &clockevent_mpu_timer1;

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction omap_mpu_timer1_irq = {
	.name		= "mpu_timer1",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= omap_mpu_timer1_interrupt,
};

static __init void omap_init_mpu_timer(unsigned long rate)
{
	setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
	omap_mpu_timer_start(0, (rate / HZ) - 1, 1);

	clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
					    clockevent_mpu_timer1.shift);
	clockevent_mpu_timer1.max_delta_ns =
		clockevent_delta2ns(-1, &clockevent_mpu_timer1);
	clockevent_mpu_timer1.min_delta_ns =
		clockevent_delta2ns(1, &clockevent_mpu_timer1);

	clockevent_mpu_timer1.cpumask = cpumask_of(0);
	clockevents_register_device(&clockevent_mpu_timer1);
}


/*
 * ---------------------------------------------------------------------------
 * MPU timer 2 ... free running 32-bit clock source and scheduler clock
 * ---------------------------------------------------------------------------
 */

static unsigned long omap_mpu_timer2_overflows;

static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
{
	omap_mpu_timer2_overflows++;
	return IRQ_HANDLED;
}

static struct irqaction omap_mpu_timer2_irq = {
	.name		= "mpu_timer2",
	.flags		= IRQF_DISABLED,
	.handler	= omap_mpu_timer2_interrupt,
};

static cycle_t mpu_read(struct clocksource *cs)
{
	return ~omap_mpu_timer_read(1);
}

static struct clocksource clocksource_mpu = {
	.name		= "mpu_timer2",
	.rating		= 300,
	.read		= mpu_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static DEFINE_CLOCK_DATA(cd);

static inline unsigned long long notrace _omap_mpu_sched_clock(void)
{
	u32 cyc = mpu_read(&clocksource_mpu);
	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}

#ifndef CONFIG_OMAP_32K_TIMER
unsigned long long notrace sched_clock(void)
{
	return _omap_mpu_sched_clock();
}
#else
static unsigned long long notrace omap_mpu_sched_clock(void)
{
	return _omap_mpu_sched_clock();
}
#endif

static void notrace mpu_update_sched_clock(void)
{
	u32 cyc = mpu_read(&clocksource_mpu);
	update_sched_clock(&cd, cyc, (u32)~0);
}

static void __init omap_init_clocksource(unsigned long rate)
{
	static char err[] __initdata = KERN_ERR
			"%s: can't register clocksource!\n";

	setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
	omap_mpu_timer_start(1, ~0, 1);
	init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);

	if (clocksource_register_hz(&clocksource_mpu, rate))
		printk(err, clocksource_mpu.name);
}

static void __init omap_mpu_timer_init(void)
{
	struct clk	*ck_ref = clk_get(NULL, "ck_ref");
	unsigned long	rate;

	BUG_ON(IS_ERR(ck_ref));

	rate = clk_get_rate(ck_ref);
	clk_put(ck_ref);

	/* PTV = 0 */
	rate /= 2;

	omap_init_mpu_timer(rate);
	omap_init_clocksource(rate);
}

#else
static inline void omap_mpu_timer_init(void)
{
	pr_err("Bogus timer, should not happen\n");
}
#endif	/* CONFIG_OMAP_MPU_TIMER */

#if defined(CONFIG_OMAP_MPU_TIMER) && defined(CONFIG_OMAP_32K_TIMER)
static unsigned long long (*preferred_sched_clock)(void);

unsigned long long notrace sched_clock(void)
{
	if (!preferred_sched_clock)
		return 0;

	return preferred_sched_clock();
}

static inline void preferred_sched_clock_init(bool use_32k_sched_clock)
{
	if (use_32k_sched_clock)
		preferred_sched_clock = omap_32k_sched_clock;
	else
		preferred_sched_clock = omap_mpu_sched_clock;
}
#else
static inline void preferred_sched_clock_init(bool use_32k_sched_clcok)
{
}
#endif

static inline int omap_32k_timer_usable(void)
{
	int res = false;

	if (cpu_is_omap730() || cpu_is_omap15xx())
		return res;

#ifdef CONFIG_OMAP_32K_TIMER
	res = omap_32k_timer_init();
#endif

	return res;
}

/*
 * ---------------------------------------------------------------------------
 * Timer initialization
 * ---------------------------------------------------------------------------
 */
static void __init omap_timer_init(void)
{
	if (omap_32k_timer_usable()) {
		preferred_sched_clock_init(1);
	} else {
		omap_mpu_timer_init();
		preferred_sched_clock_init(0);
	}
}

struct sys_timer omap_timer = {
	.init		= omap_timer_init,
};
Commit	Line	Data
1da177e4	1	/*
3b59b6be	2	* linux/arch/arm/mach-omap1/time.c
1da177e4 LT	3	*
	4	* OMAP Timers
	5	*
	6	* Copyright (C) 2004 Nokia Corporation
b3402cf5	7	* Partial timer rewrite and additional dynamic tick timer support by
1da177e4 LT	8	* Tony Lindgen <tony@atomide.com> and
	9	* Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
	10	*
	11	* MPU timer code based on the older MPU timer code for OMAP
	12	* Copyright (C) 2000 RidgeRun, Inc.
	13	* Author: Greg Lonnon <glonnon@ridgerun.com>
	14	*
	15	* This program is free software; you can redistribute it and/or modify it
	16	* under the terms of the GNU General Public License as published by the
	17	* Free Software Foundation; either version 2 of the License, or (at your
	18	* option) any later version.
	19	*
	20	* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
	21	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
	22	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
	23	* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
	24	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
	25	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
	26	* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
	29	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	30	*
	31	* You should have received a copy of the GNU General Public License along
	32	* with this program; if not, write to the Free Software Foundation, Inc.,
	33	* 675 Mass Ave, Cambridge, MA 02139, USA.
	34	*/
	35
1da177e4 LT	36	#include <linux/kernel.h>
	37	#include <linux/init.h>
	38	#include <linux/delay.h>
	39	#include <linux/interrupt.h>
	40	#include <linux/sched.h>
	41	#include <linux/spinlock.h>
075192ae KH	42	#include <linux/clk.h>
	43	#include <linux/err.h>
	44	#include <linux/clocksource.h>
	45	#include <linux/clockchips.h>
fced80c7	46	#include <linux/io.h>
f376ea17	47	#include <linux/sched.h>
1da177e4 LT	48
1da177e4 LT	49	#include <asm/system.h>
a09e64fb	50	#include <mach/hardware.h>
1da177e4 LT	51	#include <asm/leds.h>
1da177e4 LT	52	#include <asm/irq.h>
f376ea17 TL	53	#include <asm/sched_clock.h>
f376ea17 TL	54
1da177e4 LT	55	#include <asm/mach/irq.h>
	56	#include <asm/mach/time.h>
	57
706afdda	58	#include <plat/common.h>
1da177e4	59
05b5ca9b TL	60	#ifdef CONFIG_OMAP_MPU_TIMER
05b5ca9b TL	61
1da177e4 LT	62	#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
	63	#define OMAP_MPU_TIMER_OFFSET 0x100
	64
1da177e4 LT	65	typedef struct {
	66	u32 cntl; /* CNTL_TIMER, R/W */
	67	u32 load_tim; /* LOAD_TIM, W */
	68	u32 read_tim; /* READ_TIM, R */
	69	} omap_mpu_timer_regs_t;
	70
94113260 TL	71	#define omap_mpu_timer_base(n) \
94113260 TL	72	((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
1da177e4 LT	73	(n)*OMAP_MPU_TIMER_OFFSET))
1da177e4 LT	74
f376ea17	75	static inline unsigned long notrace omap_mpu_timer_read(int nr)
1da177e4 LT	76	{
	77	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	78	return timer->read_tim;
	79	}
	80
075192ae	81	static inline void omap_mpu_set_autoreset(int nr)
1da177e4 LT	82	{
	83	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	84
075192ae	85	timer->cntl = timer->cntl \| MPU_TIMER_AR;
1da177e4 LT	86	}
1da177e4 LT	87
075192ae	88	static inline void omap_mpu_remove_autoreset(int nr)
1da177e4	89	{
075192ae	90	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
1da177e4	91
075192ae	92	timer->cntl = timer->cntl & ~MPU_TIMER_AR;
1da177e4 LT	93	}
1da177e4 LT	94
075192ae KH	95	static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
	96	int autoreset)
	97	{
	98	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	99	unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE \| MPU_TIMER_ST);
	100
	101	if (autoreset) timerflags \|= MPU_TIMER_AR;
	102
	103	timer->cntl = MPU_TIMER_CLOCK_ENABLE;
	104	udelay(1);
	105	timer->load_tim = load_val;
	106	udelay(1);
	107	timer->cntl = timerflags;
	108	}
1da177e4	109
06cad098 KH	110	static inline void omap_mpu_timer_stop(int nr)
	111	{
	112	volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
	113
	114	timer->cntl &= ~MPU_TIMER_ST;
	115	}
	116
1da177e4	117	/*
075192ae KH	118	* ---------------------------------------------------------------------------
	119	* MPU timer 1 ... count down to zero, interrupt, reload
	120	* ---------------------------------------------------------------------------
1da177e4	121	*/
075192ae	122	static int omap_mpu_set_next_event(unsigned long cycles,
06cad098	123	struct clock_event_device *evt)
1da177e4	124	{
075192ae KH	125	omap_mpu_timer_start(0, cycles, 0);
	126	return 0;
	127	}
1da177e4	128
075192ae KH	129	static void omap_mpu_set_mode(enum clock_event_mode mode,
	130	struct clock_event_device *evt)
	131	{
	132	switch (mode) {
	133	case CLOCK_EVT_MODE_PERIODIC:
	134	omap_mpu_set_autoreset(0);
	135	break;
	136	case CLOCK_EVT_MODE_ONESHOT:
06cad098	137	omap_mpu_timer_stop(0);
075192ae KH	138	omap_mpu_remove_autoreset(0);
	139	break;
	140	case CLOCK_EVT_MODE_UNUSED:
	141	case CLOCK_EVT_MODE_SHUTDOWN:
18de5bc4	142	case CLOCK_EVT_MODE_RESUME:
075192ae KH	143	break;
075192ae KH	144	}
1da177e4 LT	145	}
1da177e4 LT	146
075192ae KH	147	static struct clock_event_device clockevent_mpu_timer1 = {
075192ae KH	148	.name = "mpu_timer1",
c6b349ed	149	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
075192ae KH	150	.shift = 32,
	151	.set_next_event = omap_mpu_set_next_event,
	152	.set_mode = omap_mpu_set_mode,
	153	};
	154
	155	static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
1da177e4	156	{
075192ae	157	struct clock_event_device *evt = &clockevent_mpu_timer1;
1da177e4	158
075192ae	159	evt->event_handler(evt);
1da177e4 LT	160
	161	return IRQ_HANDLED;
	162	}
	163
075192ae KH	164	static struct irqaction omap_mpu_timer1_irq = {
075192ae KH	165	.name = "mpu_timer1",
b30fabad	166	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
075192ae	167	.handler = omap_mpu_timer1_interrupt,
1da177e4 LT	168	};
1da177e4 LT	169
075192ae KH	170	static __init void omap_init_mpu_timer(unsigned long rate)
075192ae KH	171	{
075192ae KH	172	setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
	173	omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
	174
	175	clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
	176	clockevent_mpu_timer1.shift);
	177	clockevent_mpu_timer1.max_delta_ns =
	178	clockevent_delta2ns(-1, &clockevent_mpu_timer1);
	179	clockevent_mpu_timer1.min_delta_ns =
	180	clockevent_delta2ns(1, &clockevent_mpu_timer1);
	181
320ab2b0	182	clockevent_mpu_timer1.cpumask = cpumask_of(0);
075192ae KH	183	clockevents_register_device(&clockevent_mpu_timer1);
	184	}
	185
	186
	187	/*
	188	* ---------------------------------------------------------------------------
	189	* MPU timer 2 ... free running 32-bit clock source and scheduler clock
	190	* ---------------------------------------------------------------------------
	191	*/
	192
	193	static unsigned long omap_mpu_timer2_overflows;
	194
	195	static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
1da177e4	196	{
075192ae	197	omap_mpu_timer2_overflows++;
1da177e4 LT	198	return IRQ_HANDLED;
	199	}
	200
075192ae KH	201	static struct irqaction omap_mpu_timer2_irq = {
075192ae KH	202	.name = "mpu_timer2",
52e405ea	203	.flags = IRQF_DISABLED,
075192ae	204	.handler = omap_mpu_timer2_interrupt,
1da177e4 LT	205	};
1da177e4 LT	206
8e19608e	207	static cycle_t mpu_read(struct clocksource *cs)
1da177e4	208	{
075192ae KH	209	return ~omap_mpu_timer_read(1);
	210	}
	211
	212	static struct clocksource clocksource_mpu = {
	213	.name = "mpu_timer2",
	214	.rating = 300,
	215	.read = mpu_read,
	216	.mask = CLOCKSOURCE_MASK(32),
075192ae KH	217	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	218	};
	219
f376ea17 TL	220	static DEFINE_CLOCK_DATA(cd);
f376ea17 TL	221
4912cf04 TL	222	static inline unsigned long long notrace _omap_mpu_sched_clock(void)
	223	{
	224	u32 cyc = mpu_read(&clocksource_mpu);
	225	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
	226	}
	227
	228	#ifndef CONFIG_OMAP_32K_TIMER
	229	unsigned long long notrace sched_clock(void)
	230	{
	231	return _omap_mpu_sched_clock();
	232	}
	233	#else
	234	static unsigned long long notrace omap_mpu_sched_clock(void)
	235	{
	236	return _omap_mpu_sched_clock();
	237	}
	238	#endif
	239
f376ea17 TL	240	static void notrace mpu_update_sched_clock(void)
	241	{
	242	u32 cyc = mpu_read(&clocksource_mpu);
	243	update_sched_clock(&cd, cyc, (u32)~0);
	244	}
	245
075192ae KH	246	static void __init omap_init_clocksource(unsigned long rate)
	247	{
	248	static char err[] __initdata = KERN_ERR
	249	"%s: can't register clocksource!\n";
	250
075192ae KH	251	setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
075192ae KH	252	omap_mpu_timer_start(1, ~0, 1);
f376ea17	253	init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);
075192ae	254
8437c25e	255	if (clocksource_register_hz(&clocksource_mpu, rate))
075192ae	256	printk(err, clocksource_mpu.name);
1da177e4 LT	257	}
1da177e4 LT	258
05b5ca9b	259	static void __init omap_mpu_timer_init(void)
1da177e4	260	{
075192ae KH	261	struct clk *ck_ref = clk_get(NULL, "ck_ref");
	262	unsigned long rate;
	263
	264	BUG_ON(IS_ERR(ck_ref));
	265
	266	rate = clk_get_rate(ck_ref);
	267	clk_put(ck_ref);
	268
	269	/* PTV = 0 */
	270	rate /= 2;
	271
	272	omap_init_mpu_timer(rate);
	273	omap_init_clocksource(rate);
05b5ca9b TL	274	}
	275
	276	#else
	277	static inline void omap_mpu_timer_init(void)
	278	{
	279	pr_err("Bogus timer, should not happen\n");
	280	}
	281	#endif /* CONFIG_OMAP_MPU_TIMER */
	282
4912cf04 TL	283	#if defined(CONFIG_OMAP_MPU_TIMER) && defined(CONFIG_OMAP_32K_TIMER)
	284	static unsigned long long (*preferred_sched_clock)(void);
	285
	286	unsigned long long notrace sched_clock(void)
	287	{
	288	if (!preferred_sched_clock)
	289	return 0;
	290
	291	return preferred_sched_clock();
	292	}
	293
	294	static inline void preferred_sched_clock_init(bool use_32k_sched_clock)
	295	{
	296	if (use_32k_sched_clock)
	297	preferred_sched_clock = omap_32k_sched_clock;
	298	else
	299	preferred_sched_clock = omap_mpu_sched_clock;
	300	}
	301	#else
	302	static inline void preferred_sched_clock_init(bool use_32k_sched_clcok)
	303	{
	304	}
	305	#endif
	306
05b5ca9b TL	307	static inline int omap_32k_timer_usable(void)
	308	{
	309	int res = false;
	310
	311	if (cpu_is_omap730() \|\| cpu_is_omap15xx())
	312	return res;
	313
	314	#ifdef CONFIG_OMAP_32K_TIMER
	315	res = omap_32k_timer_init();
	316	#endif
	317
	318	return res;
	319	}
	320
	321	/*
	322	* ---------------------------------------------------------------------------
	323	* Timer initialization
	324	* ---------------------------------------------------------------------------
	325	*/
	326	static void __init omap_timer_init(void)
	327	{
4912cf04 TL	328	if (omap_32k_timer_usable()) {
	329	preferred_sched_clock_init(1);
	330	} else {
05b5ca9b	331	omap_mpu_timer_init();
4912cf04 TL	332	preferred_sched_clock_init(0);
4912cf04 TL	333	}
1da177e4 LT	334	}
	335
	336	struct sys_timer omap_timer = {
	337	.init = omap_timer_init,
1da177e4	338	};