Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3b59b6be | 2 | * linux/arch/arm/mach-omap1/time.c |
1da177e4 LT |
3 | * |
4 | * OMAP Timers | |
5 | * | |
6 | * Copyright (C) 2004 Nokia Corporation | |
b3402cf5 | 7 | * Partial timer rewrite and additional dynamic tick timer support by |
1da177e4 LT |
8 | * Tony Lindgen <tony@atomide.com> and |
9 | * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
10 | * | |
11 | * MPU timer code based on the older MPU timer code for OMAP | |
12 | * Copyright (C) 2000 RidgeRun, Inc. | |
13 | * Author: Greg Lonnon <glonnon@ridgerun.com> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify it | |
16 | * under the terms of the GNU General Public License as published by the | |
17 | * Free Software Foundation; either version 2 of the License, or (at your | |
18 | * option) any later version. | |
19 | * | |
20 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
21 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
22 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
23 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
24 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
25 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
26 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
27 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
28 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
29 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
30 | * | |
31 | * You should have received a copy of the GNU General Public License along | |
32 | * with this program; if not, write to the Free Software Foundation, Inc., | |
33 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
34 | */ | |
35 | ||
1da177e4 LT |
36 | #include <linux/kernel.h> |
37 | #include <linux/init.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/spinlock.h> | |
075192ae KH |
42 | #include <linux/clk.h> |
43 | #include <linux/err.h> | |
44 | #include <linux/clocksource.h> | |
45 | #include <linux/clockchips.h> | |
fced80c7 | 46 | #include <linux/io.h> |
f376ea17 | 47 | #include <linux/sched.h> |
1da177e4 LT |
48 | |
49 | #include <asm/system.h> | |
a09e64fb | 50 | #include <mach/hardware.h> |
1da177e4 LT |
51 | #include <asm/leds.h> |
52 | #include <asm/irq.h> | |
f376ea17 TL |
53 | #include <asm/sched_clock.h> |
54 | ||
1da177e4 LT |
55 | #include <asm/mach/irq.h> |
56 | #include <asm/mach/time.h> | |
57 | ||
706afdda | 58 | #include <plat/common.h> |
1da177e4 | 59 | |
1da177e4 LT |
60 | #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE |
61 | #define OMAP_MPU_TIMER_OFFSET 0x100 | |
62 | ||
1da177e4 LT |
63 | typedef struct { |
64 | u32 cntl; /* CNTL_TIMER, R/W */ | |
65 | u32 load_tim; /* LOAD_TIM, W */ | |
66 | u32 read_tim; /* READ_TIM, R */ | |
67 | } omap_mpu_timer_regs_t; | |
68 | ||
94113260 TL |
69 | #define omap_mpu_timer_base(n) \ |
70 | ((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ | |
1da177e4 LT |
71 | (n)*OMAP_MPU_TIMER_OFFSET)) |
72 | ||
f376ea17 | 73 | static inline unsigned long notrace omap_mpu_timer_read(int nr) |
1da177e4 LT |
74 | { |
75 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | |
76 | return timer->read_tim; | |
77 | } | |
78 | ||
075192ae | 79 | static inline void omap_mpu_set_autoreset(int nr) |
1da177e4 LT |
80 | { |
81 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | |
82 | ||
075192ae | 83 | timer->cntl = timer->cntl | MPU_TIMER_AR; |
1da177e4 LT |
84 | } |
85 | ||
075192ae | 86 | static inline void omap_mpu_remove_autoreset(int nr) |
1da177e4 | 87 | { |
075192ae | 88 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); |
1da177e4 | 89 | |
075192ae | 90 | timer->cntl = timer->cntl & ~MPU_TIMER_AR; |
1da177e4 LT |
91 | } |
92 | ||
075192ae KH |
93 | static inline void omap_mpu_timer_start(int nr, unsigned long load_val, |
94 | int autoreset) | |
95 | { | |
96 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | |
97 | unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST); | |
98 | ||
99 | if (autoreset) timerflags |= MPU_TIMER_AR; | |
100 | ||
101 | timer->cntl = MPU_TIMER_CLOCK_ENABLE; | |
102 | udelay(1); | |
103 | timer->load_tim = load_val; | |
104 | udelay(1); | |
105 | timer->cntl = timerflags; | |
106 | } | |
1da177e4 | 107 | |
06cad098 KH |
108 | static inline void omap_mpu_timer_stop(int nr) |
109 | { | |
110 | volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); | |
111 | ||
112 | timer->cntl &= ~MPU_TIMER_ST; | |
113 | } | |
114 | ||
1da177e4 | 115 | /* |
075192ae KH |
116 | * --------------------------------------------------------------------------- |
117 | * MPU timer 1 ... count down to zero, interrupt, reload | |
118 | * --------------------------------------------------------------------------- | |
1da177e4 | 119 | */ |
075192ae | 120 | static int omap_mpu_set_next_event(unsigned long cycles, |
06cad098 | 121 | struct clock_event_device *evt) |
1da177e4 | 122 | { |
075192ae KH |
123 | omap_mpu_timer_start(0, cycles, 0); |
124 | return 0; | |
125 | } | |
1da177e4 | 126 | |
075192ae KH |
127 | static void omap_mpu_set_mode(enum clock_event_mode mode, |
128 | struct clock_event_device *evt) | |
129 | { | |
130 | switch (mode) { | |
131 | case CLOCK_EVT_MODE_PERIODIC: | |
132 | omap_mpu_set_autoreset(0); | |
133 | break; | |
134 | case CLOCK_EVT_MODE_ONESHOT: | |
06cad098 | 135 | omap_mpu_timer_stop(0); |
075192ae KH |
136 | omap_mpu_remove_autoreset(0); |
137 | break; | |
138 | case CLOCK_EVT_MODE_UNUSED: | |
139 | case CLOCK_EVT_MODE_SHUTDOWN: | |
18de5bc4 | 140 | case CLOCK_EVT_MODE_RESUME: |
075192ae KH |
141 | break; |
142 | } | |
1da177e4 LT |
143 | } |
144 | ||
075192ae KH |
145 | static struct clock_event_device clockevent_mpu_timer1 = { |
146 | .name = "mpu_timer1", | |
c6b349ed | 147 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
075192ae KH |
148 | .shift = 32, |
149 | .set_next_event = omap_mpu_set_next_event, | |
150 | .set_mode = omap_mpu_set_mode, | |
151 | }; | |
152 | ||
153 | static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id) | |
1da177e4 | 154 | { |
075192ae | 155 | struct clock_event_device *evt = &clockevent_mpu_timer1; |
1da177e4 | 156 | |
075192ae | 157 | evt->event_handler(evt); |
1da177e4 LT |
158 | |
159 | return IRQ_HANDLED; | |
160 | } | |
161 | ||
075192ae KH |
162 | static struct irqaction omap_mpu_timer1_irq = { |
163 | .name = "mpu_timer1", | |
b30fabad | 164 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
075192ae | 165 | .handler = omap_mpu_timer1_interrupt, |
1da177e4 LT |
166 | }; |
167 | ||
075192ae KH |
168 | static __init void omap_init_mpu_timer(unsigned long rate) |
169 | { | |
075192ae KH |
170 | setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); |
171 | omap_mpu_timer_start(0, (rate / HZ) - 1, 1); | |
172 | ||
173 | clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC, | |
174 | clockevent_mpu_timer1.shift); | |
175 | clockevent_mpu_timer1.max_delta_ns = | |
176 | clockevent_delta2ns(-1, &clockevent_mpu_timer1); | |
177 | clockevent_mpu_timer1.min_delta_ns = | |
178 | clockevent_delta2ns(1, &clockevent_mpu_timer1); | |
179 | ||
320ab2b0 | 180 | clockevent_mpu_timer1.cpumask = cpumask_of(0); |
075192ae KH |
181 | clockevents_register_device(&clockevent_mpu_timer1); |
182 | } | |
183 | ||
184 | ||
185 | /* | |
186 | * --------------------------------------------------------------------------- | |
187 | * MPU timer 2 ... free running 32-bit clock source and scheduler clock | |
188 | * --------------------------------------------------------------------------- | |
189 | */ | |
190 | ||
191 | static unsigned long omap_mpu_timer2_overflows; | |
192 | ||
193 | static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id) | |
1da177e4 | 194 | { |
075192ae | 195 | omap_mpu_timer2_overflows++; |
1da177e4 LT |
196 | return IRQ_HANDLED; |
197 | } | |
198 | ||
075192ae KH |
199 | static struct irqaction omap_mpu_timer2_irq = { |
200 | .name = "mpu_timer2", | |
52e405ea | 201 | .flags = IRQF_DISABLED, |
075192ae | 202 | .handler = omap_mpu_timer2_interrupt, |
1da177e4 LT |
203 | }; |
204 | ||
8e19608e | 205 | static cycle_t mpu_read(struct clocksource *cs) |
1da177e4 | 206 | { |
075192ae KH |
207 | return ~omap_mpu_timer_read(1); |
208 | } | |
209 | ||
210 | static struct clocksource clocksource_mpu = { | |
211 | .name = "mpu_timer2", | |
212 | .rating = 300, | |
213 | .read = mpu_read, | |
214 | .mask = CLOCKSOURCE_MASK(32), | |
075192ae KH |
215 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
216 | }; | |
217 | ||
f376ea17 TL |
218 | static DEFINE_CLOCK_DATA(cd); |
219 | ||
220 | static void notrace mpu_update_sched_clock(void) | |
221 | { | |
222 | u32 cyc = mpu_read(&clocksource_mpu); | |
223 | update_sched_clock(&cd, cyc, (u32)~0); | |
224 | } | |
225 | ||
075192ae KH |
226 | static void __init omap_init_clocksource(unsigned long rate) |
227 | { | |
228 | static char err[] __initdata = KERN_ERR | |
229 | "%s: can't register clocksource!\n"; | |
230 | ||
075192ae KH |
231 | setup_irq(INT_TIMER2, &omap_mpu_timer2_irq); |
232 | omap_mpu_timer_start(1, ~0, 1); | |
f376ea17 | 233 | init_sched_clock(&cd, mpu_update_sched_clock, 32, rate); |
075192ae | 234 | |
8437c25e | 235 | if (clocksource_register_hz(&clocksource_mpu, rate)) |
075192ae | 236 | printk(err, clocksource_mpu.name); |
1da177e4 LT |
237 | } |
238 | ||
1da177e4 LT |
239 | /* |
240 | * --------------------------------------------------------------------------- | |
241 | * Timer initialization | |
242 | * --------------------------------------------------------------------------- | |
243 | */ | |
3b59b6be | 244 | static void __init omap_timer_init(void) |
1da177e4 | 245 | { |
075192ae KH |
246 | struct clk *ck_ref = clk_get(NULL, "ck_ref"); |
247 | unsigned long rate; | |
248 | ||
249 | BUG_ON(IS_ERR(ck_ref)); | |
250 | ||
251 | rate = clk_get_rate(ck_ref); | |
252 | clk_put(ck_ref); | |
253 | ||
254 | /* PTV = 0 */ | |
255 | rate /= 2; | |
256 | ||
257 | omap_init_mpu_timer(rate); | |
258 | omap_init_clocksource(rate); | |
d8328f3b PW |
259 | /* |
260 | * XXX Since this file seems to deal mostly with the MPU timer, | |
261 | * this doesn't seem like the correct place for the sync timer | |
262 | * clocksource init. | |
263 | */ | |
264 | if (!cpu_is_omap7xx() && !cpu_is_omap15xx()) | |
265 | omap_init_clocksource_32k(); | |
1da177e4 LT |
266 | } |
267 | ||
268 | struct sys_timer omap_timer = { | |
269 | .init = omap_timer_init, | |
1da177e4 | 270 | }; |