Commit | Line | Data |
---|---|---|
21278aea RH |
1 | menu "TI OMAP/AM/DM/DRA Family" |
2 | depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 | |
3 | ||
68ac8f7d | 4 | config ARCH_OMAP2 |
f558b275 | 5 | bool "TI OMAP2" |
4b0ed696 | 6 | depends on ARCH_MULTI_V6 |
59d92875 | 7 | select ARCH_OMAP2PLUS |
68ac8f7d | 8 | select CPU_V6 |
ecc46cfd | 9 | select SOC_HAS_OMAP2_SDRC |
68ac8f7d TL |
10 | |
11 | config ARCH_OMAP3 | |
f558b275 | 12 | bool "TI OMAP3" |
4b0ed696 | 13 | depends on ARCH_MULTI_V7 |
59d92875 | 14 | select ARCH_OMAP2PLUS |
15e0d9e3 | 15 | select ARM_CPU_SUSPEND if PM |
0ee7261c | 16 | select OMAP_INTERCONNECT |
b1b3f49c | 17 | select PM_OPP if PM |
464ed18e | 18 | select PM if CPU_IDLE |
b1b3f49c | 19 | select SOC_HAS_OMAP2_SDRC |
2e4094bd | 20 | select ARM_ERRATA_430973 |
68ac8f7d TL |
21 | |
22 | config ARCH_OMAP4 | |
f558b275 | 23 | bool "TI OMAP4" |
4b0ed696 | 24 | depends on ARCH_MULTI_V7 |
59d92875 | 25 | select ARCH_OMAP2PLUS |
b1b3f49c RK |
26 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
27 | select ARM_CPU_SUSPEND if PM | |
28 | select ARM_ERRATA_720789 | |
29 | select ARM_GIC | |
4c3ffffd | 30 | select HAVE_ARM_SCU if SMP |
a894fcc2 | 31 | select HAVE_ARM_TWD if SMP |
b1b3f49c | 32 | select OMAP_INTERCONNECT |
3fa60975 | 33 | select OMAP_INTERCONNECT_BARRIER |
a641f3a6 RK |
34 | select PL310_ERRATA_588369 if CACHE_L2X0 |
35 | select PL310_ERRATA_727915 if CACHE_L2X0 | |
f5a6422d | 36 | select PM_OPP if PM |
464ed18e | 37 | select PM if CPU_IDLE |
7a981995 S |
38 | select ARM_ERRATA_754322 |
39 | select ARM_ERRATA_775420 | |
8d29bdba | 40 | select OMAP_INTERCONNECT |
68ac8f7d | 41 | |
35eb4298 S |
42 | config SOC_OMAP5 |
43 | bool "TI OMAP5" | |
4b0ed696 | 44 | depends on ARCH_MULTI_V7 |
59d92875 | 45 | select ARCH_OMAP2PLUS |
b1b3f49c | 46 | select ARM_CPU_SUSPEND if PM |
35eb4298 | 47 | select ARM_GIC |
896eba3b | 48 | select HAVE_ARM_SCU if SMP |
8a4da6e3 | 49 | select HAVE_ARM_ARCH_TIMER |
f82a3133 | 50 | select ARM_ERRATA_798181 if SMP |
d8f8004e | 51 | select OMAP_INTERCONNECT |
3fa60975 | 52 | select OMAP_INTERCONNECT_BARRIER |
d8f8004e | 53 | select PM_OPP if PM |
6a3b764b | 54 | select ZONE_DMA if ARM_LPAE |
35eb4298 | 55 | |
59d92875 | 56 | config SOC_AM33XX |
1085189f | 57 | bool "TI AM33XX" |
59d92875 AB |
58 | depends on ARCH_MULTI_V7 |
59 | select ARCH_OMAP2PLUS | |
60 | select ARM_CPU_SUSPEND if PM | |
59d92875 AB |
61 | |
62 | config SOC_AM43XX | |
63 | bool "TI AM43x" | |
64 | depends on ARCH_MULTI_V7 | |
59d92875 | 65 | select ARCH_OMAP2PLUS |
59d92875 | 66 | select ARM_GIC |
59d92875 | 67 | select MACH_OMAP_GENERIC |
d941f86f | 68 | select MIGHT_HAVE_CACHE_L2X0 |
f87d089d | 69 | select HAVE_ARM_SCU |
0b3e6fca | 70 | select GENERIC_CLOCKEVENTS_BROADCAST |
54011103 | 71 | select HAVE_ARM_TWD |
65db875d DG |
72 | select ARM_ERRATA_754322 |
73 | select ARM_ERRATA_775420 | |
59d92875 | 74 | |
68b9f608 TK |
75 | config SOC_DRA7XX |
76 | bool "TI DRA7XX" | |
77 | depends on ARCH_MULTI_V7 | |
78 | select ARCH_OMAP2PLUS | |
79 | select ARM_CPU_SUSPEND if PM | |
80 | select ARM_GIC | |
d2e104c6 | 81 | select HAVE_ARM_SCU if SMP |
68b9f608 | 82 | select HAVE_ARM_ARCH_TIMER |
5c61e619 | 83 | select IRQ_CROSSBAR |
209431ef | 84 | select ARM_ERRATA_798181 if SMP |
d2e104c6 | 85 | select OMAP_INTERCONNECT |
3fa60975 | 86 | select OMAP_INTERCONNECT_BARRIER |
d2e104c6 | 87 | select PM_OPP if PM |
6a3b764b | 88 | select ZONE_DMA if ARM_LPAE |
68b9f608 | 89 | |
59d92875 AB |
90 | config ARCH_OMAP2PLUS |
91 | bool | |
92 | select ARCH_HAS_BANDGAP | |
59d92875 AB |
93 | select ARCH_HAS_HOLES_MEMORYMODEL |
94 | select ARCH_OMAP | |
59d92875 | 95 | select CLKSRC_MMIO |
59d92875 | 96 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 97 | select GPIOLIB |
f2acae69 | 98 | select MACH_OMAP_GENERIC |
18640193 | 99 | select MEMORY |
da4d8145 | 100 | select MFD_SYSCON |
59d92875 | 101 | select OMAP_DM_TIMER |
18640193 | 102 | select OMAP_GPMC |
59d92875 | 103 | select PINCTRL |
59d92875 | 104 | select SOC_BUS |
8598066c | 105 | select OMAP_IRQCHIP |
429ac200 | 106 | select CLKSRC_TI_32K |
59d92875 AB |
107 | help |
108 | Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 | |
109 | ||
3fa60975 RK |
110 | config OMAP_INTERCONNECT_BARRIER |
111 | bool | |
112 | select ARM_HEAVY_MB | |
113 | ||
59d92875 AB |
114 | |
115 | if ARCH_OMAP2PLUS | |
116 | ||
117 | menu "TI OMAP2/3/4 Specific Features" | |
118 | ||
119 | config ARCH_OMAP2PLUS_TYPICAL | |
120 | bool "Typical OMAP configuration" | |
121 | default y | |
122 | select AEABI | |
123 | select HIGHMEM | |
124 | select I2C | |
125 | select I2C_OMAP | |
126 | select MENELAUS if ARCH_OMAP2 | |
8dd21c93 | 127 | select NEON if CPU_V7 |
464ed18e | 128 | select PM |
59d92875 | 129 | select REGULATOR |
fc827928 | 130 | select REGULATOR_FIXED_VOLTAGE |
59d92875 AB |
131 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 |
132 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 | |
133 | select VFP | |
134 | help | |
135 | Compile a kernel suitable for booting most boards | |
136 | ||
137 | config SOC_HAS_OMAP2_SDRC | |
138 | bool "OMAP2 SDRAM Controller support" | |
139 | ||
140 | config SOC_HAS_REALTIME_COUNTER | |
141 | bool "Real time free running counter" | |
f18153f9 | 142 | depends on SOC_OMAP5 || SOC_DRA7XX |
59d92875 AB |
143 | default y |
144 | ||
1dbae815 | 145 | comment "OMAP Core Type" |
f558b275 | 146 | depends on ARCH_OMAP2 |
1dbae815 | 147 | |
59b479e0 | 148 | config SOC_OMAP2420 |
1dbae815 | 149 | bool "OMAP2420 support" |
f558b275 | 150 | depends on ARCH_OMAP2 |
ffb63e34 | 151 | default y |
77900a2f | 152 | select OMAP_DM_TIMER |
ecc46cfd | 153 | select SOC_HAS_OMAP2_SDRC |
1dbae815 | 154 | |
59b479e0 | 155 | config SOC_OMAP2430 |
72d0f1c3 | 156 | bool "OMAP2430 support" |
f558b275 | 157 | depends on ARCH_OMAP2 |
ffb63e34 | 158 | default y |
ecc46cfd | 159 | select SOC_HAS_OMAP2_SDRC |
72d0f1c3 | 160 | |
59b479e0 | 161 | config SOC_OMAP3430 |
cc26b3b0 | 162 | bool "OMAP3430 support" |
f558b275 | 163 | depends on ARCH_OMAP3 |
ffb63e34 | 164 | default y |
ecc46cfd | 165 | select SOC_HAS_OMAP2_SDRC |
cc26b3b0 | 166 | |
33959553 | 167 | config SOC_TI81XX |
a920360f | 168 | bool "TI81XX support" |
f558b275 | 169 | depends on ARCH_OMAP3 |
4bd7be22 HP |
170 | default y |
171 | ||
ddaa912a TL |
172 | config OMAP_PACKAGE_CBC |
173 | bool | |
174 | ||
175 | config OMAP_PACKAGE_CBB | |
176 | bool | |
177 | ||
178 | config OMAP_PACKAGE_CUS | |
179 | bool | |
180 | ||
662c8b55 TL |
181 | config OMAP_PACKAGE_CBP |
182 | bool | |
183 | ||
f2acae69 | 184 | comment "OMAP Legacy Platform Data Board Type" |
f558b275 | 185 | depends on ARCH_OMAP2PLUS |
1dbae815 TL |
186 | |
187 | config MACH_OMAP_GENERIC | |
f2acae69 | 188 | bool |
1dbae815 | 189 | |
1b52d5df KV |
190 | config MACH_OMAP2_TUSB6010 |
191 | bool | |
59b479e0 | 192 | depends on ARCH_OMAP2 && SOC_OMAP2420 |
1b52d5df KV |
193 | default y if MACH_NOKIA_N8X0 |
194 | ||
49265651 NK |
195 | config MACH_OMAP_LDP |
196 | bool "OMAP3 LDP board" | |
a8eb7ca0 | 197 | depends on ARCH_OMAP3 |
ffb63e34 | 198 | default y |
ca5742bd | 199 | select OMAP_PACKAGE_CBB |
49265651 | 200 | |
549f95ed TL |
201 | config MACH_OMAP3517EVM |
202 | bool "OMAP3517/ AM3517 EVM board" | |
203 | depends on ARCH_OMAP3 | |
204 | default y | |
205 | ||
da177247 GI |
206 | config MACH_OMAP3_PANDORA |
207 | bool "OMAP3 Pandora" | |
a8eb7ca0 | 208 | depends on ARCH_OMAP3 |
ffb63e34 | 209 | default y |
ca5742bd | 210 | select OMAP_PACKAGE_CBB |
6fdc29e2 | 211 | |
d2fbf345 TL |
212 | config MACH_NOKIA_N810 |
213 | bool | |
214 | ||
215 | config MACH_NOKIA_N810_WIMAX | |
216 | bool | |
217 | ||
63138812 KV |
218 | config MACH_NOKIA_N8X0 |
219 | bool "Nokia N800/N810" | |
59b479e0 | 220 | depends on SOC_OMAP2420 |
ffb63e34 | 221 | default y |
d2fbf345 TL |
222 | select MACH_NOKIA_N810 |
223 | select MACH_NOKIA_N810_WIMAX | |
63138812 | 224 | |
ffe7f95b | 225 | config MACH_NOKIA_RX51 |
cc067797 | 226 | bool "Nokia N900 (RX-51) phone" |
a8eb7ca0 | 227 | depends on ARCH_OMAP3 |
ffb63e34 | 228 | default y |
ca5742bd | 229 | select OMAP_PACKAGE_CBB |
577145f4 | 230 | |
18862cbe PW |
231 | config OMAP3_SDRC_AC_TIMING |
232 | bool "Enable SDRC AC timing register changes" | |
a8eb7ca0 | 233 | depends on ARCH_OMAP3 |
18862cbe PW |
234 | default n |
235 | help | |
236 | If you know that none of your system initiators will attempt to | |
237 | access SDRAM during CORE DVFS, select Y here. This should boost | |
238 | SDRAM performance at lower CORE OPPs. There are relatively few | |
239 | users who will wish to say yes at this point - almost everyone will | |
240 | wish to say no. Selecting yes without understanding what is | |
241 | going on could result in system crashes; | |
242 | ||
4a54db61 TL |
243 | endmenu |
244 | ||
245 | endif | |
21278aea | 246 | |
c0053bd5 NM |
247 | config OMAP5_ERRATA_801819 |
248 | bool "Errata 801819: An eviction from L1 data cache might stall indefinitely" | |
249 | depends on SOC_OMAP5 || SOC_DRA7XX | |
250 | help | |
251 | A livelock can occur in the L2 cache arbitration that might prevent | |
252 | a snoop from completing. Under certain conditions this can cause the | |
253 | system to deadlock. | |
254 | ||
21278aea | 255 | endmenu |