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6fdc29e2 SMK |
1 | /* |
2 | * linux/arch/arm/mach-omap2/board-3430sdp.c | |
3 | * | |
4 | * Copyright (C) 2007 Texas Instruments | |
5 | * | |
6 | * Modified from mach-omap2/board-generic.c | |
7 | * | |
8 | * Initial code: Syed Mohammed Khasim | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/input.h> | |
6135434a | 20 | #include <linux/input/matrix_keypad.h> |
6fdc29e2 | 21 | #include <linux/spi/spi.h> |
b07682b6 | 22 | #include <linux/i2c/twl.h> |
6fdc29e2 SMK |
23 | #include <linux/regulator/machine.h> |
24 | #include <linux/io.h> | |
25 | #include <linux/gpio.h> | |
3a63833e | 26 | #include <linux/mmc/host.h> |
2203747c | 27 | #include <linux/platform_data/spi-omap2-mcspi.h> |
77f86144 | 28 | #include <linux/platform_data/omap-twl4030.h> |
51482be9 | 29 | #include <linux/usb/phy.h> |
6fdc29e2 | 30 | |
6fdc29e2 SMK |
31 | #include <asm/mach-types.h> |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
34 | ||
4e65331c | 35 | #include "common.h" |
45c3eb7d | 36 | #include <linux/omap-dma.h> |
a0b38cc4 | 37 | #include <video/omapdss.h> |
dac8eb5f | 38 | #include <video/omap-panel-tfp410.h> |
6fdc29e2 | 39 | |
99f0b8d6 | 40 | #include "gpmc.h" |
60628152 | 41 | #include "gpmc-smc91x.h" |
6fdc29e2 | 42 | |
e4c060db | 43 | #include "soc.h" |
04aeae77 | 44 | #include "board-flash.h" |
ca5742bd | 45 | #include "mux.h" |
17a722ca | 46 | #include "sdram-qimonda-hyb18m512160af-6.h" |
d02a900b | 47 | #include "hsmmc.h" |
bb4de3df | 48 | #include "pm.h" |
4814ced5 | 49 | #include "control.h" |
96974a24 | 50 | #include "common-board-devices.h" |
6fdc29e2 SMK |
51 | |
52 | #define CONFIG_DISABLE_HFCLK 1 | |
53 | ||
6fdc29e2 SMK |
54 | #define SDP3430_TS_GPIO_IRQ_SDPV1 3 |
55 | #define SDP3430_TS_GPIO_IRQ_SDPV2 2 | |
56 | ||
57 | #define ENABLE_VAUX3_DEDICATED 0x03 | |
58 | #define ENABLE_VAUX3_DEV_GRP 0x20 | |
59 | ||
60 | #define TWL4030_MSECURE_GPIO 22 | |
61 | ||
bead4375 | 62 | static uint32_t board_keymap[] = { |
6fdc29e2 SMK |
63 | KEY(0, 0, KEY_LEFT), |
64 | KEY(0, 1, KEY_RIGHT), | |
65 | KEY(0, 2, KEY_A), | |
66 | KEY(0, 3, KEY_B), | |
67 | KEY(0, 4, KEY_C), | |
68 | KEY(1, 0, KEY_DOWN), | |
69 | KEY(1, 1, KEY_UP), | |
70 | KEY(1, 2, KEY_E), | |
71 | KEY(1, 3, KEY_F), | |
72 | KEY(1, 4, KEY_G), | |
73 | KEY(2, 0, KEY_ENTER), | |
74 | KEY(2, 1, KEY_I), | |
75 | KEY(2, 2, KEY_J), | |
76 | KEY(2, 3, KEY_K), | |
77 | KEY(2, 4, KEY_3), | |
78 | KEY(3, 0, KEY_M), | |
79 | KEY(3, 1, KEY_N), | |
80 | KEY(3, 2, KEY_O), | |
81 | KEY(3, 3, KEY_P), | |
82 | KEY(3, 4, KEY_Q), | |
83 | KEY(4, 0, KEY_R), | |
84 | KEY(4, 1, KEY_4), | |
85 | KEY(4, 2, KEY_T), | |
86 | KEY(4, 3, KEY_U), | |
87 | KEY(4, 4, KEY_D), | |
88 | KEY(5, 0, KEY_V), | |
89 | KEY(5, 1, KEY_W), | |
90 | KEY(5, 2, KEY_L), | |
91 | KEY(5, 3, KEY_S), | |
92 | KEY(5, 4, KEY_H), | |
93 | 0 | |
94 | }; | |
95 | ||
4f543332 TL |
96 | static struct matrix_keymap_data board_map_data = { |
97 | .keymap = board_keymap, | |
98 | .keymap_size = ARRAY_SIZE(board_keymap), | |
99 | }; | |
100 | ||
6fdc29e2 | 101 | static struct twl4030_keypad_data sdp3430_kp_data = { |
4f543332 | 102 | .keymap_data = &board_map_data, |
6fdc29e2 SMK |
103 | .rows = 5, |
104 | .cols = 6, | |
6fdc29e2 SMK |
105 | .rep = 1, |
106 | }; | |
107 | ||
d9056ce2 TV |
108 | #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8 |
109 | #define SDP3430_LCD_PANEL_ENABLE_GPIO 5 | |
110 | ||
bc593f5d IG |
111 | static struct gpio sdp3430_dss_gpios[] __initdata = { |
112 | {SDP3430_LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW, "LCD reset" }, | |
113 | {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"}, | |
114 | }; | |
115 | ||
d9056ce2 TV |
116 | static void __init sdp3430_display_init(void) |
117 | { | |
118 | int r; | |
119 | ||
bc593f5d IG |
120 | r = gpio_request_array(sdp3430_dss_gpios, |
121 | ARRAY_SIZE(sdp3430_dss_gpios)); | |
122 | if (r) | |
123 | printk(KERN_ERR "failed to get LCD control GPIOs\n"); | |
d9056ce2 | 124 | |
d9056ce2 TV |
125 | } |
126 | ||
127 | static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) | |
128 | { | |
bc593f5d IG |
129 | gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1); |
130 | gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1); | |
d9056ce2 | 131 | |
d9056ce2 TV |
132 | return 0; |
133 | } | |
134 | ||
135 | static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) | |
136 | { | |
bc593f5d IG |
137 | gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0); |
138 | gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0); | |
d9056ce2 TV |
139 | } |
140 | ||
d9056ce2 TV |
141 | static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) |
142 | { | |
143 | return 0; | |
144 | } | |
145 | ||
146 | static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev) | |
147 | { | |
148 | } | |
149 | ||
150 | ||
151 | static struct omap_dss_device sdp3430_lcd_device = { | |
152 | .name = "lcd", | |
153 | .driver_name = "sharp_ls_panel", | |
154 | .type = OMAP_DISPLAY_TYPE_DPI, | |
155 | .phy.dpi.data_lines = 16, | |
156 | .platform_enable = sdp3430_panel_enable_lcd, | |
157 | .platform_disable = sdp3430_panel_disable_lcd, | |
6fdc29e2 SMK |
158 | }; |
159 | ||
2e6f2ee7 | 160 | static struct tfp410_platform_data dvi_panel = { |
e813a55e | 161 | .power_down_gpio = -1, |
ca2e16fa | 162 | .i2c_bus_num = -1, |
89747c91 BW |
163 | }; |
164 | ||
d9056ce2 TV |
165 | static struct omap_dss_device sdp3430_dvi_device = { |
166 | .name = "dvi", | |
d9056ce2 | 167 | .type = OMAP_DISPLAY_TYPE_DPI, |
2e6f2ee7 | 168 | .driver_name = "tfp410", |
89747c91 | 169 | .data = &dvi_panel, |
d9056ce2 | 170 | .phy.dpi.data_lines = 24, |
6fdc29e2 SMK |
171 | }; |
172 | ||
d9056ce2 TV |
173 | static struct omap_dss_device sdp3430_tv_device = { |
174 | .name = "tv", | |
175 | .driver_name = "venc", | |
176 | .type = OMAP_DISPLAY_TYPE_VENC, | |
177 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | |
178 | .platform_enable = sdp3430_panel_enable_tv, | |
179 | .platform_disable = sdp3430_panel_disable_tv, | |
6fdc29e2 SMK |
180 | }; |
181 | ||
d9056ce2 TV |
182 | |
183 | static struct omap_dss_device *sdp3430_dss_devices[] = { | |
6fdc29e2 | 184 | &sdp3430_lcd_device, |
d9056ce2 TV |
185 | &sdp3430_dvi_device, |
186 | &sdp3430_tv_device, | |
6fdc29e2 SMK |
187 | }; |
188 | ||
d9056ce2 TV |
189 | static struct omap_dss_board_info sdp3430_dss_data = { |
190 | .num_devices = ARRAY_SIZE(sdp3430_dss_devices), | |
191 | .devices = sdp3430_dss_devices, | |
192 | .default_device = &sdp3430_lcd_device, | |
193 | }; | |
194 | ||
68ff0423 | 195 | static struct omap2_hsmmc_info mmc[] = { |
6fdc29e2 SMK |
196 | { |
197 | .mmc = 1, | |
198 | /* 8 bits (default) requires S6.3 == ON, | |
199 | * so the SIM card isn't used; else 4 bits. | |
200 | */ | |
3a63833e | 201 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
6fdc29e2 | 202 | .gpio_wp = 4, |
3b972bf0 | 203 | .deferred = true, |
6fdc29e2 SMK |
204 | }, |
205 | { | |
206 | .mmc = 2, | |
3a63833e | 207 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
6fdc29e2 | 208 | .gpio_wp = 7, |
3b972bf0 | 209 | .deferred = true, |
6fdc29e2 SMK |
210 | }, |
211 | {} /* Terminator */ | |
212 | }; | |
213 | ||
77f86144 PU |
214 | static struct omap_tw4030_pdata omap_twl4030_audio_data = { |
215 | .voice_connected = true, | |
216 | .custom_routing = true, | |
217 | ||
218 | .has_hs = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT, | |
219 | .has_hf = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT, | |
220 | ||
221 | .has_mainmic = true, | |
222 | .has_submic = true, | |
223 | .has_hsmic = true, | |
224 | .has_linein = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT, | |
225 | }; | |
226 | ||
6fdc29e2 SMK |
227 | static int sdp3430_twl_gpio_setup(struct device *dev, |
228 | unsigned gpio, unsigned ngpio) | |
229 | { | |
230 | /* gpio + 0 is "mmc0_cd" (input/IRQ), | |
231 | * gpio + 1 is "mmc1_cd" (input/IRQ) | |
232 | */ | |
233 | mmc[0].gpio_cd = gpio + 0; | |
234 | mmc[1].gpio_cd = gpio + 1; | |
3b972bf0 | 235 | omap_hsmmc_late_init(mmc); |
6fdc29e2 | 236 | |
6fdc29e2 | 237 | /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ |
bc593f5d | 238 | gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl"); |
6fdc29e2 SMK |
239 | |
240 | /* gpio + 15 is "sub_lcd_nRST" (output) */ | |
bc593f5d | 241 | gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST"); |
6fdc29e2 | 242 | |
77f86144 PU |
243 | omap_twl4030_audio_data.jack_detect = gpio + 2; |
244 | omap_twl4030_audio_init("SDP3430", &omap_twl4030_audio_data); | |
245 | ||
6fdc29e2 SMK |
246 | return 0; |
247 | } | |
248 | ||
249 | static struct twl4030_gpio_platform_data sdp3430_gpio_data = { | |
6fdc29e2 SMK |
250 | .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) |
251 | | BIT(16) | BIT(17), | |
252 | .setup = sdp3430_twl_gpio_setup, | |
253 | }; | |
254 | ||
73a92aa4 RN |
255 | /* regulator consumer mappings */ |
256 | ||
4b087ff8 RN |
257 | /* ads7846 on SPI */ |
258 | static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { | |
259 | REGULATOR_SUPPLY("vcc", "spi1.0"), | |
260 | }; | |
261 | ||
73a92aa4 | 262 | static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { |
0005ae73 | 263 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), |
73a92aa4 RN |
264 | }; |
265 | ||
266 | static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { | |
0005ae73 | 267 | REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), |
73a92aa4 RN |
268 | }; |
269 | ||
270 | static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { | |
0005ae73 | 271 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), |
73a92aa4 RN |
272 | }; |
273 | ||
6fdc29e2 SMK |
274 | /* |
275 | * Apply all the fixed voltages since most versions of U-Boot | |
276 | * don't bother with that initialization. | |
277 | */ | |
278 | ||
279 | /* VAUX1 for mainboard (irda and sub-lcd) */ | |
280 | static struct regulator_init_data sdp3430_vaux1 = { | |
281 | .constraints = { | |
282 | .min_uV = 2800000, | |
283 | .max_uV = 2800000, | |
284 | .apply_uV = true, | |
285 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
286 | | REGULATOR_MODE_STANDBY, | |
287 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
288 | | REGULATOR_CHANGE_STATUS, | |
289 | }, | |
290 | }; | |
291 | ||
292 | /* VAUX2 for camera module */ | |
293 | static struct regulator_init_data sdp3430_vaux2 = { | |
294 | .constraints = { | |
295 | .min_uV = 2800000, | |
296 | .max_uV = 2800000, | |
297 | .apply_uV = true, | |
298 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
299 | | REGULATOR_MODE_STANDBY, | |
300 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
301 | | REGULATOR_CHANGE_STATUS, | |
302 | }, | |
303 | }; | |
304 | ||
305 | /* VAUX3 for LCD board */ | |
306 | static struct regulator_init_data sdp3430_vaux3 = { | |
307 | .constraints = { | |
308 | .min_uV = 2800000, | |
309 | .max_uV = 2800000, | |
310 | .apply_uV = true, | |
311 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
312 | | REGULATOR_MODE_STANDBY, | |
313 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
314 | | REGULATOR_CHANGE_STATUS, | |
315 | }, | |
4b087ff8 RN |
316 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies), |
317 | .consumer_supplies = sdp3430_vaux3_supplies, | |
6fdc29e2 SMK |
318 | }; |
319 | ||
320 | /* VAUX4 for OMAP VDD_CSI2 (camera) */ | |
321 | static struct regulator_init_data sdp3430_vaux4 = { | |
322 | .constraints = { | |
323 | .min_uV = 1800000, | |
324 | .max_uV = 1800000, | |
325 | .apply_uV = true, | |
326 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
327 | | REGULATOR_MODE_STANDBY, | |
328 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
329 | | REGULATOR_CHANGE_STATUS, | |
330 | }, | |
331 | }; | |
332 | ||
333 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ | |
334 | static struct regulator_init_data sdp3430_vmmc1 = { | |
335 | .constraints = { | |
336 | .min_uV = 1850000, | |
337 | .max_uV = 3150000, | |
338 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
339 | | REGULATOR_MODE_STANDBY, | |
340 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
341 | | REGULATOR_CHANGE_MODE | |
342 | | REGULATOR_CHANGE_STATUS, | |
343 | }, | |
73a92aa4 RN |
344 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies), |
345 | .consumer_supplies = sdp3430_vmmc1_supplies, | |
6fdc29e2 SMK |
346 | }; |
347 | ||
348 | /* VMMC2 for MMC2 card */ | |
349 | static struct regulator_init_data sdp3430_vmmc2 = { | |
350 | .constraints = { | |
351 | .min_uV = 1850000, | |
352 | .max_uV = 1850000, | |
353 | .apply_uV = true, | |
354 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
355 | | REGULATOR_MODE_STANDBY, | |
356 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
357 | | REGULATOR_CHANGE_STATUS, | |
358 | }, | |
73a92aa4 RN |
359 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies), |
360 | .consumer_supplies = sdp3430_vmmc2_supplies, | |
6fdc29e2 SMK |
361 | }; |
362 | ||
363 | /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ | |
364 | static struct regulator_init_data sdp3430_vsim = { | |
365 | .constraints = { | |
366 | .min_uV = 1800000, | |
367 | .max_uV = 3000000, | |
368 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
369 | | REGULATOR_MODE_STANDBY, | |
370 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
371 | | REGULATOR_CHANGE_MODE | |
372 | | REGULATOR_CHANGE_STATUS, | |
373 | }, | |
73a92aa4 RN |
374 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies), |
375 | .consumer_supplies = sdp3430_vsim_supplies, | |
6fdc29e2 SMK |
376 | }; |
377 | ||
6fdc29e2 | 378 | static struct twl4030_platform_data sdp3430_twldata = { |
6fdc29e2 | 379 | /* platform_data for children goes here */ |
6fdc29e2 | 380 | .gpio = &sdp3430_gpio_data, |
6fdc29e2 | 381 | .keypad = &sdp3430_kp_data, |
6fdc29e2 SMK |
382 | |
383 | .vaux1 = &sdp3430_vaux1, | |
384 | .vaux2 = &sdp3430_vaux2, | |
385 | .vaux3 = &sdp3430_vaux3, | |
386 | .vaux4 = &sdp3430_vaux4, | |
387 | .vmmc1 = &sdp3430_vmmc1, | |
388 | .vmmc2 = &sdp3430_vmmc2, | |
389 | .vsim = &sdp3430_vsim, | |
6fdc29e2 SMK |
390 | }; |
391 | ||
6fdc29e2 SMK |
392 | static int __init omap3430_i2c_init(void) |
393 | { | |
394 | /* i2c1 for PMIC only */ | |
827ed9ae | 395 | omap3_pmic_get_config(&sdp3430_twldata, |
b252b0ef PU |
396 | TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI | |
397 | TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO, | |
398 | TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); | |
399 | sdp3430_twldata.vdac->constraints.apply_uV = true; | |
400 | sdp3430_twldata.vpll2->constraints.apply_uV = true; | |
401 | sdp3430_twldata.vpll2->constraints.name = "VDVI"; | |
402 | ||
7b00077a PU |
403 | sdp3430_twldata.audio->codec->hs_extmute = 1; |
404 | sdp3430_twldata.audio->codec->hs_extmute_gpio = -EINVAL; | |
405 | ||
fbd8071c | 406 | omap3_pmic_init("twl4030", &sdp3430_twldata); |
827ed9ae | 407 | |
6fdc29e2 SMK |
408 | /* i2c2 on camera connector (for sensor control) and optional isp1301 */ |
409 | omap_register_i2c_bus(2, 400, NULL, 0); | |
410 | /* i2c3 on display connector (for DVI, tfp410) */ | |
411 | omap_register_i2c_bus(3, 400, NULL, 0); | |
412 | return 0; | |
413 | } | |
414 | ||
1a48e157 TL |
415 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
416 | ||
417 | static struct omap_smc91x_platform_data board_smc91x_data = { | |
418 | .cs = 3, | |
419 | .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 | | |
420 | IORESOURCE_IRQ_LOWLEVEL, | |
421 | }; | |
422 | ||
423 | static void __init board_smc91x_init(void) | |
424 | { | |
425 | if (omap_rev() > OMAP3430_REV_ES1_0) | |
426 | board_smc91x_data.gpio_irq = 6; | |
427 | else | |
428 | board_smc91x_data.gpio_irq = 29; | |
429 | ||
430 | gpmc_smc91x_init(&board_smc91x_data); | |
431 | } | |
432 | ||
433 | #else | |
434 | ||
435 | static inline void board_smc91x_init(void) | |
436 | { | |
437 | } | |
438 | ||
439 | #endif | |
440 | ||
5110b298 RT |
441 | static void enable_board_wakeup_source(void) |
442 | { | |
4896e394 TL |
443 | /* T2 interrupt line (keypad) */ |
444 | omap_mux_init_signal("sys_nirq", | |
445 | OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); | |
5110b298 RT |
446 | } |
447 | ||
42973159 | 448 | static struct usbhs_omap_platform_data usbhs_bdata __initdata = { |
58a5491c | 449 | |
181b250c KM |
450 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, |
451 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | |
452 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | |
58a5491c FB |
453 | |
454 | .phy_reset = true, | |
455 | .reset_gpio_port[0] = 57, | |
456 | .reset_gpio_port[1] = 61, | |
457 | .reset_gpio_port[2] = -EINVAL | |
458 | }; | |
459 | ||
ca5742bd TL |
460 | #ifdef CONFIG_OMAP_MUX |
461 | static struct omap_board_mux board_mux[] __initdata = { | |
462 | { .reg_offset = OMAP_MUX_TERMINATOR }, | |
463 | }; | |
626dda8a S |
464 | #else |
465 | #define board_mux NULL | |
ca5742bd TL |
466 | #endif |
467 | ||
13d6b73c SG |
468 | /* |
469 | * SDP3430 V2 Board CS organization | |
470 | * Different from SDP3430 V1. Now 4 switches used to specify CS | |
471 | * | |
472 | * See also the Switch S8 settings in the comments. | |
473 | */ | |
474 | static char chip_sel_3430[][GPMC_CS_NUM] = { | |
475 | {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ | |
476 | {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ | |
477 | {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ | |
478 | }; | |
479 | ||
88c8460a VS |
480 | static struct mtd_partition sdp_nor_partitions[] = { |
481 | /* bootloader (U-Boot, etc) in first sector */ | |
482 | { | |
483 | .name = "Bootloader-NOR", | |
484 | .offset = 0, | |
485 | .size = SZ_256K, | |
486 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
487 | }, | |
488 | /* bootloader params in the next sector */ | |
489 | { | |
490 | .name = "Params-NOR", | |
491 | .offset = MTDPART_OFS_APPEND, | |
492 | .size = SZ_256K, | |
493 | .mask_flags = 0, | |
494 | }, | |
495 | /* kernel */ | |
496 | { | |
497 | .name = "Kernel-NOR", | |
498 | .offset = MTDPART_OFS_APPEND, | |
499 | .size = SZ_2M, | |
500 | .mask_flags = 0 | |
501 | }, | |
502 | /* file system */ | |
503 | { | |
504 | .name = "Filesystem-NOR", | |
505 | .offset = MTDPART_OFS_APPEND, | |
506 | .size = MTDPART_SIZ_FULL, | |
507 | .mask_flags = 0 | |
508 | } | |
509 | }; | |
510 | ||
511 | static struct mtd_partition sdp_onenand_partitions[] = { | |
512 | { | |
513 | .name = "X-Loader-OneNAND", | |
514 | .offset = 0, | |
515 | .size = 4 * (64 * 2048), | |
516 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
517 | }, | |
518 | { | |
519 | .name = "U-Boot-OneNAND", | |
520 | .offset = MTDPART_OFS_APPEND, | |
521 | .size = 2 * (64 * 2048), | |
522 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
523 | }, | |
524 | { | |
525 | .name = "U-Boot Environment-OneNAND", | |
526 | .offset = MTDPART_OFS_APPEND, | |
527 | .size = 1 * (64 * 2048), | |
528 | }, | |
529 | { | |
530 | .name = "Kernel-OneNAND", | |
531 | .offset = MTDPART_OFS_APPEND, | |
532 | .size = 16 * (64 * 2048), | |
533 | }, | |
534 | { | |
535 | .name = "File System-OneNAND", | |
536 | .offset = MTDPART_OFS_APPEND, | |
537 | .size = MTDPART_SIZ_FULL, | |
538 | }, | |
539 | }; | |
540 | ||
541 | static struct mtd_partition sdp_nand_partitions[] = { | |
542 | /* All the partition sizes are listed in terms of NAND block size */ | |
543 | { | |
544 | .name = "X-Loader-NAND", | |
545 | .offset = 0, | |
546 | .size = 4 * (64 * 2048), | |
547 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
548 | }, | |
549 | { | |
550 | .name = "U-Boot-NAND", | |
551 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | |
552 | .size = 10 * (64 * 2048), | |
553 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
554 | }, | |
555 | { | |
556 | .name = "Boot Env-NAND", | |
557 | ||
558 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | |
559 | .size = 6 * (64 * 2048), | |
560 | }, | |
561 | { | |
562 | .name = "Kernel-NAND", | |
563 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | |
564 | .size = 40 * (64 * 2048), | |
565 | }, | |
566 | { | |
567 | .name = "File System - NAND", | |
568 | .size = MTDPART_SIZ_FULL, | |
569 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ | |
570 | }, | |
571 | }; | |
572 | ||
573 | static struct flash_partitions sdp_flash_partitions[] = { | |
574 | { | |
575 | .parts = sdp_nor_partitions, | |
576 | .nr_parts = ARRAY_SIZE(sdp_nor_partitions), | |
577 | }, | |
578 | { | |
579 | .parts = sdp_onenand_partitions, | |
580 | .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), | |
581 | }, | |
582 | { | |
583 | .parts = sdp_nand_partitions, | |
584 | .nr_parts = ARRAY_SIZE(sdp_nand_partitions), | |
585 | }, | |
586 | }; | |
587 | ||
6fdc29e2 SMK |
588 | static void __init omap_3430sdp_init(void) |
589 | { | |
96974a24 MR |
590 | int gpio_pendown; |
591 | ||
ca5742bd | 592 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
3b972bf0 | 593 | omap_hsmmc_init(mmc); |
6fdc29e2 | 594 | omap3430_i2c_init(); |
d5e13227 | 595 | omap_display_init(&sdp3430_dss_data); |
6fdc29e2 | 596 | if (omap_rev() > OMAP3430_REV_ES1_0) |
96974a24 | 597 | gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2; |
6fdc29e2 | 598 | else |
96974a24 MR |
599 | gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1; |
600 | omap_ads7846_init(1, gpio_pendown, 310, NULL); | |
7496ba30 | 601 | omap_serial_init(); |
a4ca9dbe | 602 | omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); |
51482be9 | 603 | usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); |
9e18630b | 604 | usb_musb_init(NULL); |
1a48e157 | 605 | board_smc91x_init(); |
d5ce2b65 | 606 | board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); |
d9056ce2 | 607 | sdp3430_display_init(); |
5110b298 | 608 | enable_board_wakeup_source(); |
9e64bb1e | 609 | usbhs_init(&usbhs_bdata); |
6fdc29e2 SMK |
610 | } |
611 | ||
6fdc29e2 SMK |
612 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") |
613 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | |
5e52b435 | 614 | .atag_offset = 0x100, |
71ee7dad | 615 | .reserve = omap_reserve, |
3dc3bad6 | 616 | .map_io = omap3_map_io, |
8f5b5a41 | 617 | .init_early = omap3430_init_early, |
741e3a89 | 618 | .init_irq = omap3_init_irq, |
6b2f55d7 | 619 | .handle_irq = omap3_intc_handle_irq, |
6fdc29e2 | 620 | .init_machine = omap_3430sdp_init, |
bbd707ac | 621 | .init_late = omap3430_init_late, |
6bb27d73 | 622 | .init_time = omap3_sync32k_timer_init, |
187e3e06 | 623 | .restart = omap3xxx_restart, |
6fdc29e2 | 624 | MACHINE_END |