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6fdc29e2 SMK |
1 | /* |
2 | * linux/arch/arm/mach-omap2/board-3430sdp.c | |
3 | * | |
4 | * Copyright (C) 2007 Texas Instruments | |
5 | * | |
6 | * Modified from mach-omap2/board-generic.c | |
7 | * | |
8 | * Initial code: Syed Mohammed Khasim | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/input.h> | |
6135434a | 20 | #include <linux/input/matrix_keypad.h> |
6fdc29e2 | 21 | #include <linux/spi/spi.h> |
b07682b6 | 22 | #include <linux/i2c/twl.h> |
6fdc29e2 SMK |
23 | #include <linux/regulator/machine.h> |
24 | #include <linux/io.h> | |
25 | #include <linux/gpio.h> | |
3a63833e | 26 | #include <linux/mmc/host.h> |
6fdc29e2 SMK |
27 | |
28 | #include <mach/hardware.h> | |
29 | #include <asm/mach-types.h> | |
30 | #include <asm/mach/arch.h> | |
31 | #include <asm/mach/map.h> | |
32 | ||
ce491cf8 | 33 | #include <plat/mcspi.h> |
ce491cf8 TL |
34 | #include <plat/board.h> |
35 | #include <plat/usb.h> | |
36 | #include <plat/common.h> | |
37 | #include <plat/dma.h> | |
38 | #include <plat/gpmc.h> | |
d9056ce2 | 39 | #include <plat/display.h> |
89747c91 | 40 | #include <plat/panel-generic-dpi.h> |
6fdc29e2 | 41 | |
ce491cf8 | 42 | #include <plat/gpmc-smc91x.h> |
6fdc29e2 | 43 | |
04aeae77 | 44 | #include "board-flash.h" |
ca5742bd | 45 | #include "mux.h" |
17a722ca | 46 | #include "sdram-qimonda-hyb18m512160af-6.h" |
d02a900b | 47 | #include "hsmmc.h" |
bb4de3df | 48 | #include "pm.h" |
4814ced5 | 49 | #include "control.h" |
96974a24 | 50 | #include "common-board-devices.h" |
6fdc29e2 SMK |
51 | |
52 | #define CONFIG_DISABLE_HFCLK 1 | |
53 | ||
6fdc29e2 SMK |
54 | #define SDP3430_TS_GPIO_IRQ_SDPV1 3 |
55 | #define SDP3430_TS_GPIO_IRQ_SDPV2 2 | |
56 | ||
57 | #define ENABLE_VAUX3_DEDICATED 0x03 | |
58 | #define ENABLE_VAUX3_DEV_GRP 0x20 | |
59 | ||
60 | #define TWL4030_MSECURE_GPIO 22 | |
61 | ||
bb4de3df KH |
62 | /* FIXME: These values need to be updated based on more profiling on 3430sdp*/ |
63 | static struct cpuidle_params omap3_cpuidle_params_table[] = { | |
64 | /* C1 */ | |
709731bb | 65 | {1, 2, 2, 5}, |
bb4de3df | 66 | /* C2 */ |
709731bb | 67 | {1, 10, 10, 30}, |
bb4de3df | 68 | /* C3 */ |
709731bb | 69 | {1, 50, 50, 300}, |
bb4de3df | 70 | /* C4 */ |
709731bb | 71 | {1, 1500, 1800, 4000}, |
bb4de3df | 72 | /* C5 */ |
709731bb | 73 | {1, 2500, 7500, 12000}, |
bb4de3df | 74 | /* C6 */ |
709731bb | 75 | {1, 3000, 8500, 15000}, |
bb4de3df | 76 | /* C7 */ |
709731bb | 77 | {1, 10000, 30000, 300000}, |
bb4de3df KH |
78 | }; |
79 | ||
bead4375 | 80 | static uint32_t board_keymap[] = { |
6fdc29e2 SMK |
81 | KEY(0, 0, KEY_LEFT), |
82 | KEY(0, 1, KEY_RIGHT), | |
83 | KEY(0, 2, KEY_A), | |
84 | KEY(0, 3, KEY_B), | |
85 | KEY(0, 4, KEY_C), | |
86 | KEY(1, 0, KEY_DOWN), | |
87 | KEY(1, 1, KEY_UP), | |
88 | KEY(1, 2, KEY_E), | |
89 | KEY(1, 3, KEY_F), | |
90 | KEY(1, 4, KEY_G), | |
91 | KEY(2, 0, KEY_ENTER), | |
92 | KEY(2, 1, KEY_I), | |
93 | KEY(2, 2, KEY_J), | |
94 | KEY(2, 3, KEY_K), | |
95 | KEY(2, 4, KEY_3), | |
96 | KEY(3, 0, KEY_M), | |
97 | KEY(3, 1, KEY_N), | |
98 | KEY(3, 2, KEY_O), | |
99 | KEY(3, 3, KEY_P), | |
100 | KEY(3, 4, KEY_Q), | |
101 | KEY(4, 0, KEY_R), | |
102 | KEY(4, 1, KEY_4), | |
103 | KEY(4, 2, KEY_T), | |
104 | KEY(4, 3, KEY_U), | |
105 | KEY(4, 4, KEY_D), | |
106 | KEY(5, 0, KEY_V), | |
107 | KEY(5, 1, KEY_W), | |
108 | KEY(5, 2, KEY_L), | |
109 | KEY(5, 3, KEY_S), | |
110 | KEY(5, 4, KEY_H), | |
111 | 0 | |
112 | }; | |
113 | ||
4f543332 TL |
114 | static struct matrix_keymap_data board_map_data = { |
115 | .keymap = board_keymap, | |
116 | .keymap_size = ARRAY_SIZE(board_keymap), | |
117 | }; | |
118 | ||
6fdc29e2 | 119 | static struct twl4030_keypad_data sdp3430_kp_data = { |
4f543332 | 120 | .keymap_data = &board_map_data, |
6fdc29e2 SMK |
121 | .rows = 5, |
122 | .cols = 6, | |
6fdc29e2 SMK |
123 | .rep = 1, |
124 | }; | |
125 | ||
d9056ce2 TV |
126 | #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8 |
127 | #define SDP3430_LCD_PANEL_ENABLE_GPIO 5 | |
128 | ||
129 | static unsigned backlight_gpio; | |
130 | static unsigned enable_gpio; | |
131 | static int lcd_enabled; | |
132 | static int dvi_enabled; | |
133 | ||
134 | static void __init sdp3430_display_init(void) | |
135 | { | |
136 | int r; | |
137 | ||
138 | enable_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO; | |
139 | backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO; | |
140 | ||
141 | r = gpio_request(enable_gpio, "LCD reset"); | |
142 | if (r) { | |
143 | printk(KERN_ERR "failed to get LCD reset GPIO\n"); | |
144 | goto err0; | |
145 | } | |
146 | ||
147 | r = gpio_request(backlight_gpio, "LCD Backlight"); | |
148 | if (r) { | |
149 | printk(KERN_ERR "failed to get LCD backlight GPIO\n"); | |
150 | goto err1; | |
151 | } | |
152 | ||
153 | gpio_direction_output(enable_gpio, 0); | |
154 | gpio_direction_output(backlight_gpio, 0); | |
155 | ||
156 | return; | |
157 | err1: | |
158 | gpio_free(enable_gpio); | |
159 | err0: | |
160 | return; | |
161 | } | |
162 | ||
163 | static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev) | |
164 | { | |
165 | if (dvi_enabled) { | |
166 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | |
167 | return -EINVAL; | |
168 | } | |
169 | ||
170 | gpio_direction_output(enable_gpio, 1); | |
171 | gpio_direction_output(backlight_gpio, 1); | |
172 | ||
173 | lcd_enabled = 1; | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
178 | static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev) | |
179 | { | |
180 | lcd_enabled = 0; | |
181 | ||
182 | gpio_direction_output(enable_gpio, 0); | |
183 | gpio_direction_output(backlight_gpio, 0); | |
184 | } | |
185 | ||
186 | static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev) | |
187 | { | |
188 | if (lcd_enabled) { | |
189 | printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); | |
190 | return -EINVAL; | |
191 | } | |
192 | ||
193 | dvi_enabled = 1; | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
198 | static void sdp3430_panel_disable_dvi(struct omap_dss_device *dssdev) | |
199 | { | |
200 | dvi_enabled = 0; | |
201 | } | |
202 | ||
203 | static int sdp3430_panel_enable_tv(struct omap_dss_device *dssdev) | |
204 | { | |
205 | return 0; | |
206 | } | |
207 | ||
208 | static void sdp3430_panel_disable_tv(struct omap_dss_device *dssdev) | |
209 | { | |
210 | } | |
211 | ||
212 | ||
213 | static struct omap_dss_device sdp3430_lcd_device = { | |
214 | .name = "lcd", | |
215 | .driver_name = "sharp_ls_panel", | |
216 | .type = OMAP_DISPLAY_TYPE_DPI, | |
217 | .phy.dpi.data_lines = 16, | |
218 | .platform_enable = sdp3430_panel_enable_lcd, | |
219 | .platform_disable = sdp3430_panel_disable_lcd, | |
6fdc29e2 SMK |
220 | }; |
221 | ||
89747c91 BW |
222 | static struct panel_generic_dpi_data dvi_panel = { |
223 | .name = "generic", | |
224 | .platform_enable = sdp3430_panel_enable_dvi, | |
225 | .platform_disable = sdp3430_panel_disable_dvi, | |
226 | }; | |
227 | ||
d9056ce2 TV |
228 | static struct omap_dss_device sdp3430_dvi_device = { |
229 | .name = "dvi", | |
d9056ce2 | 230 | .type = OMAP_DISPLAY_TYPE_DPI, |
89747c91 BW |
231 | .driver_name = "generic_dpi_panel", |
232 | .data = &dvi_panel, | |
d9056ce2 | 233 | .phy.dpi.data_lines = 24, |
6fdc29e2 SMK |
234 | }; |
235 | ||
d9056ce2 TV |
236 | static struct omap_dss_device sdp3430_tv_device = { |
237 | .name = "tv", | |
238 | .driver_name = "venc", | |
239 | .type = OMAP_DISPLAY_TYPE_VENC, | |
240 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | |
241 | .platform_enable = sdp3430_panel_enable_tv, | |
242 | .platform_disable = sdp3430_panel_disable_tv, | |
6fdc29e2 SMK |
243 | }; |
244 | ||
d9056ce2 TV |
245 | |
246 | static struct omap_dss_device *sdp3430_dss_devices[] = { | |
6fdc29e2 | 247 | &sdp3430_lcd_device, |
d9056ce2 TV |
248 | &sdp3430_dvi_device, |
249 | &sdp3430_tv_device, | |
6fdc29e2 SMK |
250 | }; |
251 | ||
d9056ce2 TV |
252 | static struct omap_dss_board_info sdp3430_dss_data = { |
253 | .num_devices = ARRAY_SIZE(sdp3430_dss_devices), | |
254 | .devices = sdp3430_dss_devices, | |
255 | .default_device = &sdp3430_lcd_device, | |
256 | }; | |
257 | ||
6fdc29e2 | 258 | static struct omap_board_config_kernel sdp3430_config[] __initdata = { |
6fdc29e2 SMK |
259 | }; |
260 | ||
3dc3bad6 | 261 | static void __init omap_3430sdp_init_early(void) |
b3c6df3a | 262 | { |
4805734b PW |
263 | omap2_init_common_infrastructure(); |
264 | omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); | |
b3c6df3a PW |
265 | } |
266 | ||
6fdc29e2 SMK |
267 | static int sdp3430_batt_table[] = { |
268 | /* 0 C*/ | |
269 | 30800, 29500, 28300, 27100, | |
270 | 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900, | |
271 | 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100, | |
272 | 11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310, | |
273 | 8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830, | |
274 | 5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170, | |
275 | 4040, 3910, 3790, 3670, 3550 | |
276 | }; | |
277 | ||
278 | static struct twl4030_bci_platform_data sdp3430_bci_data = { | |
279 | .battery_tmp_tbl = sdp3430_batt_table, | |
280 | .tblsize = ARRAY_SIZE(sdp3430_batt_table), | |
281 | }; | |
282 | ||
68ff0423 | 283 | static struct omap2_hsmmc_info mmc[] = { |
6fdc29e2 SMK |
284 | { |
285 | .mmc = 1, | |
286 | /* 8 bits (default) requires S6.3 == ON, | |
287 | * so the SIM card isn't used; else 4 bits. | |
288 | */ | |
3a63833e | 289 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
6fdc29e2 SMK |
290 | .gpio_wp = 4, |
291 | }, | |
292 | { | |
293 | .mmc = 2, | |
3a63833e | 294 | .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, |
6fdc29e2 SMK |
295 | .gpio_wp = 7, |
296 | }, | |
297 | {} /* Terminator */ | |
298 | }; | |
299 | ||
6fdc29e2 SMK |
300 | static int sdp3430_twl_gpio_setup(struct device *dev, |
301 | unsigned gpio, unsigned ngpio) | |
302 | { | |
303 | /* gpio + 0 is "mmc0_cd" (input/IRQ), | |
304 | * gpio + 1 is "mmc1_cd" (input/IRQ) | |
305 | */ | |
306 | mmc[0].gpio_cd = gpio + 0; | |
307 | mmc[1].gpio_cd = gpio + 1; | |
68ff0423 | 308 | omap2_hsmmc_init(mmc); |
6fdc29e2 | 309 | |
6fdc29e2 SMK |
310 | /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ |
311 | gpio_request(gpio + 7, "sub_lcd_en_bkl"); | |
312 | gpio_direction_output(gpio + 7, 0); | |
313 | ||
314 | /* gpio + 15 is "sub_lcd_nRST" (output) */ | |
315 | gpio_request(gpio + 15, "sub_lcd_nRST"); | |
316 | gpio_direction_output(gpio + 15, 0); | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | static struct twl4030_gpio_platform_data sdp3430_gpio_data = { | |
322 | .gpio_base = OMAP_MAX_GPIO_LINES, | |
323 | .irq_base = TWL4030_GPIO_IRQ_BASE, | |
324 | .irq_end = TWL4030_GPIO_IRQ_END, | |
325 | .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) | |
326 | | BIT(16) | BIT(17), | |
327 | .setup = sdp3430_twl_gpio_setup, | |
328 | }; | |
329 | ||
330 | static struct twl4030_usb_data sdp3430_usb_data = { | |
331 | .usb_mode = T2_USB_MODE_ULPI, | |
332 | }; | |
333 | ||
334 | static struct twl4030_madc_platform_data sdp3430_madc_data = { | |
335 | .irq_line = 1, | |
336 | }; | |
337 | ||
73a92aa4 RN |
338 | /* regulator consumer mappings */ |
339 | ||
4b087ff8 RN |
340 | /* ads7846 on SPI */ |
341 | static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = { | |
342 | REGULATOR_SUPPLY("vcc", "spi1.0"), | |
343 | }; | |
344 | ||
73a92aa4 | 345 | static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = { |
30ea50c9 | 346 | REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"), |
73a92aa4 RN |
347 | }; |
348 | ||
349 | /* VPLL2 for digital video outputs */ | |
350 | static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = { | |
351 | REGULATOR_SUPPLY("vdds_dsi", "omapdss"), | |
c8aac01b | 352 | REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), |
73a92aa4 RN |
353 | }; |
354 | ||
355 | static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { | |
0005ae73 | 356 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), |
73a92aa4 RN |
357 | }; |
358 | ||
359 | static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { | |
0005ae73 | 360 | REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), |
73a92aa4 RN |
361 | }; |
362 | ||
363 | static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { | |
0005ae73 | 364 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"), |
73a92aa4 RN |
365 | }; |
366 | ||
6fdc29e2 SMK |
367 | /* |
368 | * Apply all the fixed voltages since most versions of U-Boot | |
369 | * don't bother with that initialization. | |
370 | */ | |
371 | ||
372 | /* VAUX1 for mainboard (irda and sub-lcd) */ | |
373 | static struct regulator_init_data sdp3430_vaux1 = { | |
374 | .constraints = { | |
375 | .min_uV = 2800000, | |
376 | .max_uV = 2800000, | |
377 | .apply_uV = true, | |
378 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
379 | | REGULATOR_MODE_STANDBY, | |
380 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
381 | | REGULATOR_CHANGE_STATUS, | |
382 | }, | |
383 | }; | |
384 | ||
385 | /* VAUX2 for camera module */ | |
386 | static struct regulator_init_data sdp3430_vaux2 = { | |
387 | .constraints = { | |
388 | .min_uV = 2800000, | |
389 | .max_uV = 2800000, | |
390 | .apply_uV = true, | |
391 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
392 | | REGULATOR_MODE_STANDBY, | |
393 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
394 | | REGULATOR_CHANGE_STATUS, | |
395 | }, | |
396 | }; | |
397 | ||
398 | /* VAUX3 for LCD board */ | |
399 | static struct regulator_init_data sdp3430_vaux3 = { | |
400 | .constraints = { | |
401 | .min_uV = 2800000, | |
402 | .max_uV = 2800000, | |
403 | .apply_uV = true, | |
404 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
405 | | REGULATOR_MODE_STANDBY, | |
406 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
407 | | REGULATOR_CHANGE_STATUS, | |
408 | }, | |
4b087ff8 RN |
409 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies), |
410 | .consumer_supplies = sdp3430_vaux3_supplies, | |
6fdc29e2 SMK |
411 | }; |
412 | ||
413 | /* VAUX4 for OMAP VDD_CSI2 (camera) */ | |
414 | static struct regulator_init_data sdp3430_vaux4 = { | |
415 | .constraints = { | |
416 | .min_uV = 1800000, | |
417 | .max_uV = 1800000, | |
418 | .apply_uV = true, | |
419 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
420 | | REGULATOR_MODE_STANDBY, | |
421 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
422 | | REGULATOR_CHANGE_STATUS, | |
423 | }, | |
424 | }; | |
425 | ||
426 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ | |
427 | static struct regulator_init_data sdp3430_vmmc1 = { | |
428 | .constraints = { | |
429 | .min_uV = 1850000, | |
430 | .max_uV = 3150000, | |
431 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
432 | | REGULATOR_MODE_STANDBY, | |
433 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
434 | | REGULATOR_CHANGE_MODE | |
435 | | REGULATOR_CHANGE_STATUS, | |
436 | }, | |
73a92aa4 RN |
437 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies), |
438 | .consumer_supplies = sdp3430_vmmc1_supplies, | |
6fdc29e2 SMK |
439 | }; |
440 | ||
441 | /* VMMC2 for MMC2 card */ | |
442 | static struct regulator_init_data sdp3430_vmmc2 = { | |
443 | .constraints = { | |
444 | .min_uV = 1850000, | |
445 | .max_uV = 1850000, | |
446 | .apply_uV = true, | |
447 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
448 | | REGULATOR_MODE_STANDBY, | |
449 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
450 | | REGULATOR_CHANGE_STATUS, | |
451 | }, | |
73a92aa4 RN |
452 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies), |
453 | .consumer_supplies = sdp3430_vmmc2_supplies, | |
6fdc29e2 SMK |
454 | }; |
455 | ||
456 | /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ | |
457 | static struct regulator_init_data sdp3430_vsim = { | |
458 | .constraints = { | |
459 | .min_uV = 1800000, | |
460 | .max_uV = 3000000, | |
461 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
462 | | REGULATOR_MODE_STANDBY, | |
463 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
464 | | REGULATOR_CHANGE_MODE | |
465 | | REGULATOR_CHANGE_STATUS, | |
466 | }, | |
73a92aa4 RN |
467 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies), |
468 | .consumer_supplies = sdp3430_vsim_supplies, | |
6fdc29e2 SMK |
469 | }; |
470 | ||
471 | /* VDAC for DSS driving S-Video */ | |
472 | static struct regulator_init_data sdp3430_vdac = { | |
473 | .constraints = { | |
474 | .min_uV = 1800000, | |
475 | .max_uV = 1800000, | |
476 | .apply_uV = true, | |
477 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
478 | | REGULATOR_MODE_STANDBY, | |
479 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
480 | | REGULATOR_CHANGE_STATUS, | |
481 | }, | |
73a92aa4 RN |
482 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies), |
483 | .consumer_supplies = sdp3430_vdda_dac_supplies, | |
d9056ce2 TV |
484 | }; |
485 | ||
6fdc29e2 SMK |
486 | static struct regulator_init_data sdp3430_vpll2 = { |
487 | .constraints = { | |
488 | .name = "VDVI", | |
489 | .min_uV = 1800000, | |
490 | .max_uV = 1800000, | |
d9056ce2 | 491 | .apply_uV = true, |
6fdc29e2 SMK |
492 | .valid_modes_mask = REGULATOR_MODE_NORMAL |
493 | | REGULATOR_MODE_STANDBY, | |
494 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
495 | | REGULATOR_CHANGE_STATUS, | |
496 | }, | |
d9056ce2 TV |
497 | .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies), |
498 | .consumer_supplies = sdp3430_vpll2_supplies, | |
6fdc29e2 SMK |
499 | }; |
500 | ||
6a58baf8 | 501 | static struct twl4030_codec_audio_data sdp3430_audio; |
e86fa0b4 PU |
502 | |
503 | static struct twl4030_codec_data sdp3430_codec = { | |
6df74efb | 504 | .audio_mclk = 26000000, |
e86fa0b4 PU |
505 | .audio = &sdp3430_audio, |
506 | }; | |
507 | ||
6fdc29e2 SMK |
508 | static struct twl4030_platform_data sdp3430_twldata = { |
509 | .irq_base = TWL4030_IRQ_BASE, | |
510 | .irq_end = TWL4030_IRQ_END, | |
511 | ||
512 | /* platform_data for children goes here */ | |
513 | .bci = &sdp3430_bci_data, | |
514 | .gpio = &sdp3430_gpio_data, | |
515 | .madc = &sdp3430_madc_data, | |
516 | .keypad = &sdp3430_kp_data, | |
517 | .usb = &sdp3430_usb_data, | |
e86fa0b4 | 518 | .codec = &sdp3430_codec, |
6fdc29e2 SMK |
519 | |
520 | .vaux1 = &sdp3430_vaux1, | |
521 | .vaux2 = &sdp3430_vaux2, | |
522 | .vaux3 = &sdp3430_vaux3, | |
523 | .vaux4 = &sdp3430_vaux4, | |
524 | .vmmc1 = &sdp3430_vmmc1, | |
525 | .vmmc2 = &sdp3430_vmmc2, | |
526 | .vsim = &sdp3430_vsim, | |
527 | .vdac = &sdp3430_vdac, | |
528 | .vpll2 = &sdp3430_vpll2, | |
529 | }; | |
530 | ||
6fdc29e2 SMK |
531 | static int __init omap3430_i2c_init(void) |
532 | { | |
533 | /* i2c1 for PMIC only */ | |
fbd8071c | 534 | omap3_pmic_init("twl4030", &sdp3430_twldata); |
6fdc29e2 SMK |
535 | /* i2c2 on camera connector (for sensor control) and optional isp1301 */ |
536 | omap_register_i2c_bus(2, 400, NULL, 0); | |
537 | /* i2c3 on display connector (for DVI, tfp410) */ | |
538 | omap_register_i2c_bus(3, 400, NULL, 0); | |
539 | return 0; | |
540 | } | |
541 | ||
1a48e157 TL |
542 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) |
543 | ||
544 | static struct omap_smc91x_platform_data board_smc91x_data = { | |
545 | .cs = 3, | |
546 | .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 | | |
547 | IORESOURCE_IRQ_LOWLEVEL, | |
548 | }; | |
549 | ||
550 | static void __init board_smc91x_init(void) | |
551 | { | |
552 | if (omap_rev() > OMAP3430_REV_ES1_0) | |
553 | board_smc91x_data.gpio_irq = 6; | |
554 | else | |
555 | board_smc91x_data.gpio_irq = 29; | |
556 | ||
557 | gpmc_smc91x_init(&board_smc91x_data); | |
558 | } | |
559 | ||
560 | #else | |
561 | ||
562 | static inline void board_smc91x_init(void) | |
563 | { | |
564 | } | |
565 | ||
566 | #endif | |
567 | ||
5110b298 RT |
568 | static void enable_board_wakeup_source(void) |
569 | { | |
4896e394 TL |
570 | /* T2 interrupt line (keypad) */ |
571 | omap_mux_init_signal("sys_nirq", | |
572 | OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP); | |
5110b298 RT |
573 | } |
574 | ||
181b250c | 575 | static const struct usbhs_omap_board_data usbhs_bdata __initconst = { |
58a5491c | 576 | |
181b250c KM |
577 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, |
578 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | |
579 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | |
58a5491c FB |
580 | |
581 | .phy_reset = true, | |
582 | .reset_gpio_port[0] = 57, | |
583 | .reset_gpio_port[1] = 61, | |
584 | .reset_gpio_port[2] = -EINVAL | |
585 | }; | |
586 | ||
ca5742bd TL |
587 | #ifdef CONFIG_OMAP_MUX |
588 | static struct omap_board_mux board_mux[] __initdata = { | |
589 | { .reg_offset = OMAP_MUX_TERMINATOR }, | |
590 | }; | |
626dda8a S |
591 | |
592 | static struct omap_device_pad serial1_pads[] __initdata = { | |
593 | /* | |
594 | * Note that off output enable is an active low | |
595 | * signal. So setting this means pin is a | |
596 | * input enabled in off mode | |
597 | */ | |
598 | OMAP_MUX_STATIC("uart1_cts.uart1_cts", | |
599 | OMAP_PIN_INPUT | | |
600 | OMAP_PIN_OFF_INPUT_PULLDOWN | | |
601 | OMAP_OFFOUT_EN | | |
602 | OMAP_MUX_MODE0), | |
603 | OMAP_MUX_STATIC("uart1_rts.uart1_rts", | |
604 | OMAP_PIN_OUTPUT | | |
605 | OMAP_OFF_EN | | |
606 | OMAP_MUX_MODE0), | |
607 | OMAP_MUX_STATIC("uart1_rx.uart1_rx", | |
608 | OMAP_PIN_INPUT | | |
609 | OMAP_PIN_OFF_INPUT_PULLDOWN | | |
610 | OMAP_OFFOUT_EN | | |
611 | OMAP_MUX_MODE0), | |
612 | OMAP_MUX_STATIC("uart1_tx.uart1_tx", | |
613 | OMAP_PIN_OUTPUT | | |
614 | OMAP_OFF_EN | | |
615 | OMAP_MUX_MODE0), | |
616 | }; | |
617 | ||
618 | static struct omap_device_pad serial2_pads[] __initdata = { | |
619 | OMAP_MUX_STATIC("uart2_cts.uart2_cts", | |
620 | OMAP_PIN_INPUT_PULLUP | | |
621 | OMAP_PIN_OFF_INPUT_PULLDOWN | | |
622 | OMAP_OFFOUT_EN | | |
623 | OMAP_MUX_MODE0), | |
624 | OMAP_MUX_STATIC("uart2_rts.uart2_rts", | |
625 | OMAP_PIN_OUTPUT | | |
626 | OMAP_OFF_EN | | |
627 | OMAP_MUX_MODE0), | |
628 | OMAP_MUX_STATIC("uart2_rx.uart2_rx", | |
629 | OMAP_PIN_INPUT | | |
630 | OMAP_PIN_OFF_INPUT_PULLDOWN | | |
631 | OMAP_OFFOUT_EN | | |
632 | OMAP_MUX_MODE0), | |
633 | OMAP_MUX_STATIC("uart2_tx.uart2_tx", | |
634 | OMAP_PIN_OUTPUT | | |
635 | OMAP_OFF_EN | | |
636 | OMAP_MUX_MODE0), | |
637 | }; | |
638 | ||
639 | static struct omap_device_pad serial3_pads[] __initdata = { | |
640 | OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx", | |
641 | OMAP_PIN_INPUT_PULLDOWN | | |
642 | OMAP_PIN_OFF_INPUT_PULLDOWN | | |
643 | OMAP_OFFOUT_EN | | |
644 | OMAP_MUX_MODE0), | |
645 | OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd", | |
646 | OMAP_PIN_OUTPUT | | |
647 | OMAP_OFF_EN | | |
648 | OMAP_MUX_MODE0), | |
649 | OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx", | |
650 | OMAP_PIN_INPUT | | |
651 | OMAP_PIN_OFF_INPUT_PULLDOWN | | |
652 | OMAP_OFFOUT_EN | | |
653 | OMAP_MUX_MODE0), | |
654 | OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx", | |
655 | OMAP_PIN_OUTPUT | | |
656 | OMAP_OFF_EN | | |
657 | OMAP_MUX_MODE0), | |
658 | }; | |
659 | ||
660 | static struct omap_board_data serial1_data = { | |
661 | .id = 0, | |
662 | .pads = serial1_pads, | |
663 | .pads_cnt = ARRAY_SIZE(serial1_pads), | |
664 | }; | |
665 | ||
666 | static struct omap_board_data serial2_data = { | |
667 | .id = 1, | |
668 | .pads = serial2_pads, | |
669 | .pads_cnt = ARRAY_SIZE(serial2_pads), | |
670 | }; | |
671 | ||
672 | static struct omap_board_data serial3_data = { | |
673 | .id = 2, | |
674 | .pads = serial3_pads, | |
675 | .pads_cnt = ARRAY_SIZE(serial3_pads), | |
676 | }; | |
677 | ||
678 | static inline void board_serial_init(void) | |
679 | { | |
680 | omap_serial_init_port(&serial1_data); | |
681 | omap_serial_init_port(&serial2_data); | |
682 | omap_serial_init_port(&serial3_data); | |
683 | } | |
684 | #else | |
685 | #define board_mux NULL | |
686 | ||
687 | static inline void board_serial_init(void) | |
688 | { | |
689 | omap_serial_init(); | |
690 | } | |
ca5742bd TL |
691 | #endif |
692 | ||
13d6b73c SG |
693 | /* |
694 | * SDP3430 V2 Board CS organization | |
695 | * Different from SDP3430 V1. Now 4 switches used to specify CS | |
696 | * | |
697 | * See also the Switch S8 settings in the comments. | |
698 | */ | |
699 | static char chip_sel_3430[][GPMC_CS_NUM] = { | |
700 | {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */ | |
701 | {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */ | |
702 | {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */ | |
703 | }; | |
704 | ||
88c8460a VS |
705 | static struct mtd_partition sdp_nor_partitions[] = { |
706 | /* bootloader (U-Boot, etc) in first sector */ | |
707 | { | |
708 | .name = "Bootloader-NOR", | |
709 | .offset = 0, | |
710 | .size = SZ_256K, | |
711 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
712 | }, | |
713 | /* bootloader params in the next sector */ | |
714 | { | |
715 | .name = "Params-NOR", | |
716 | .offset = MTDPART_OFS_APPEND, | |
717 | .size = SZ_256K, | |
718 | .mask_flags = 0, | |
719 | }, | |
720 | /* kernel */ | |
721 | { | |
722 | .name = "Kernel-NOR", | |
723 | .offset = MTDPART_OFS_APPEND, | |
724 | .size = SZ_2M, | |
725 | .mask_flags = 0 | |
726 | }, | |
727 | /* file system */ | |
728 | { | |
729 | .name = "Filesystem-NOR", | |
730 | .offset = MTDPART_OFS_APPEND, | |
731 | .size = MTDPART_SIZ_FULL, | |
732 | .mask_flags = 0 | |
733 | } | |
734 | }; | |
735 | ||
736 | static struct mtd_partition sdp_onenand_partitions[] = { | |
737 | { | |
738 | .name = "X-Loader-OneNAND", | |
739 | .offset = 0, | |
740 | .size = 4 * (64 * 2048), | |
741 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
742 | }, | |
743 | { | |
744 | .name = "U-Boot-OneNAND", | |
745 | .offset = MTDPART_OFS_APPEND, | |
746 | .size = 2 * (64 * 2048), | |
747 | .mask_flags = MTD_WRITEABLE /* force read-only */ | |
748 | }, | |
749 | { | |
750 | .name = "U-Boot Environment-OneNAND", | |
751 | .offset = MTDPART_OFS_APPEND, | |
752 | .size = 1 * (64 * 2048), | |
753 | }, | |
754 | { | |
755 | .name = "Kernel-OneNAND", | |
756 | .offset = MTDPART_OFS_APPEND, | |
757 | .size = 16 * (64 * 2048), | |
758 | }, | |
759 | { | |
760 | .name = "File System-OneNAND", | |
761 | .offset = MTDPART_OFS_APPEND, | |
762 | .size = MTDPART_SIZ_FULL, | |
763 | }, | |
764 | }; | |
765 | ||
766 | static struct mtd_partition sdp_nand_partitions[] = { | |
767 | /* All the partition sizes are listed in terms of NAND block size */ | |
768 | { | |
769 | .name = "X-Loader-NAND", | |
770 | .offset = 0, | |
771 | .size = 4 * (64 * 2048), | |
772 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
773 | }, | |
774 | { | |
775 | .name = "U-Boot-NAND", | |
776 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | |
777 | .size = 10 * (64 * 2048), | |
778 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
779 | }, | |
780 | { | |
781 | .name = "Boot Env-NAND", | |
782 | ||
783 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ | |
784 | .size = 6 * (64 * 2048), | |
785 | }, | |
786 | { | |
787 | .name = "Kernel-NAND", | |
788 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | |
789 | .size = 40 * (64 * 2048), | |
790 | }, | |
791 | { | |
792 | .name = "File System - NAND", | |
793 | .size = MTDPART_SIZ_FULL, | |
794 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */ | |
795 | }, | |
796 | }; | |
797 | ||
798 | static struct flash_partitions sdp_flash_partitions[] = { | |
799 | { | |
800 | .parts = sdp_nor_partitions, | |
801 | .nr_parts = ARRAY_SIZE(sdp_nor_partitions), | |
802 | }, | |
803 | { | |
804 | .parts = sdp_onenand_partitions, | |
805 | .nr_parts = ARRAY_SIZE(sdp_onenand_partitions), | |
806 | }, | |
807 | { | |
808 | .parts = sdp_nand_partitions, | |
809 | .nr_parts = ARRAY_SIZE(sdp_nand_partitions), | |
810 | }, | |
811 | }; | |
812 | ||
6fdc29e2 SMK |
813 | static void __init omap_3430sdp_init(void) |
814 | { | |
96974a24 MR |
815 | int gpio_pendown; |
816 | ||
ca5742bd | 817 | omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); |
e41cccfe TL |
818 | omap_board_config = sdp3430_config; |
819 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); | |
820 | omap3_pm_init_cpuidle(omap3_cpuidle_params_table); | |
6fdc29e2 | 821 | omap3430_i2c_init(); |
d5e13227 | 822 | omap_display_init(&sdp3430_dss_data); |
6fdc29e2 | 823 | if (omap_rev() > OMAP3430_REV_ES1_0) |
96974a24 | 824 | gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2; |
6fdc29e2 | 825 | else |
96974a24 MR |
826 | gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1; |
827 | omap_ads7846_init(1, gpio_pendown, 310, NULL); | |
626dda8a | 828 | board_serial_init(); |
9e18630b | 829 | usb_musb_init(NULL); |
1a48e157 | 830 | board_smc91x_init(); |
d5ce2b65 | 831 | board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); |
d9056ce2 | 832 | sdp3430_display_init(); |
5110b298 | 833 | enable_board_wakeup_source(); |
9e64bb1e | 834 | usbhs_init(&usbhs_bdata); |
6fdc29e2 SMK |
835 | } |
836 | ||
6fdc29e2 SMK |
837 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") |
838 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | |
6fdc29e2 | 839 | .boot_params = 0x80000100, |
71ee7dad | 840 | .reserve = omap_reserve, |
3dc3bad6 RKAL |
841 | .map_io = omap3_map_io, |
842 | .init_early = omap_3430sdp_init_early, | |
843 | .init_irq = omap_init_irq, | |
6fdc29e2 SMK |
844 | .init_machine = omap_3430sdp_init, |
845 | .timer = &omap_timer, | |
846 | MACHINE_END |