projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: OMAP: remove plat/clock.h
[deliverable/linux.git] / arch / arm / mach-omap2 / board-cm-t35.c
CommitLineData
2886d128 1/*
c3146974 2 * CompuLab CM-T35/CM-T3730 modules support
2886d128 3 *
d12c2e28
IG		 4 * Copyright (C) 2009-2011 CompuLab, Ltd.
5 * Authors: Mike Rapoport <mike@compulab.co.il>
6 * Igor Grinberg <grinberg@compulab.co.il>
2886d128
MR		 7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
2886d128
MR		 17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/input.h>
23#include <linux/input/matrix_keypad.h>
24#include <linux/delay.h>
25#include <linux/gpio.h>
4b25408f 26#include <linux/platform_data/gpio-omap.h>
2886d128
MR		 27
28#include <linux/i2c/at24.h>
ebeb53e1 29#include <linux/i2c/twl.h>
5b3689f4 30#include <linux/regulator/fixed.h>
2886d128 31#include <linux/regulator/machine.h>
3a63833e 32#include <linux/mmc/host.h>
2886d128 33
7f049ad1
MR		 34#include <linux/spi/spi.h>
35#include <linux/spi/tdo24m.h>
36
2886d128
MR		 37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40
4e65331c 41#include "common.h"
2203747c 42#include <linux/platform_data/mtd-nand-omap2.h>
3ef5d007 43#include "gpmc.h"
2886d128 44#include <plat/usb.h>
a0b38cc4 45#include <video/omapdss.h>
f8ae2f08 46#include <video/omap-panel-generic-dpi.h>
dac8eb5f 47#include <video/omap-panel-tfp410.h>
2203747c 48#include <linux/platform_data/spi-omap2-mcspi.h>
2886d128
MR		 49
50#include <mach/hardware.h>
51
ca5742bd 52#include "mux.h"
2886d128 53#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 54#include "hsmmc.h"
96974a24 55#include "common-board-devices.h"
bc3668ea 56#include "gpmc-nand.h"
2886d128 57
039401f3
IG		 58#define CM_T35_GPIO_PENDOWN 57
59#define SB_T35_USB_HUB_RESET_GPIO 167
2886d128
MR		 60
61#define CM_T35_SMSC911X_CS 5
62#define CM_T35_SMSC911X_GPIO 163
63#define SB_T35_SMSC911X_CS 4
64#define SB_T35_SMSC911X_GPIO 65
65
2886d128
MR		 66#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
67#include <linux/smsc911x.h>
ac839b3c 68#include "gpmc-smsc911x.h"
2886d128 69
21b42731 70static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
2886d128 71 .id = 0,
21b42731
MR		 72 .cs = CM_T35_SMSC911X_CS,
73 .gpio_irq = CM_T35_SMSC911X_GPIO,
74 .gpio_reset = -EINVAL,
75 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
2886d128
MR		 76};
77
21b42731 78static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
2886d128 79 .id = 1,
21b42731
MR		 80 .cs = SB_T35_SMSC911X_CS,
81 .gpio_irq = SB_T35_SMSC911X_GPIO,
82 .gpio_reset = -EINVAL,
83 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
2886d128
MR		 84};
85
5b3689f4
RD		 86static struct regulator_consumer_supply cm_t35_smsc911x_supplies[] = {
87 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
88 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
89};
90
91static struct regulator_consumer_supply sb_t35_smsc911x_supplies[] = {
92 REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
93 REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
94};
95
2886d128
MR		 96static void __init cm_t35_init_ethernet(void)
97{
5b3689f4
RD		 98 regulator_register_fixed(0, cm_t35_smsc911x_supplies,
99 ARRAY_SIZE(cm_t35_smsc911x_supplies));
100 regulator_register_fixed(1, sb_t35_smsc911x_supplies,
101 ARRAY_SIZE(sb_t35_smsc911x_supplies));
102
21b42731
MR		 103 gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
104 gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
2886d128
MR		 105}
106#else
107static inline void __init cm_t35_init_ethernet(void) { return; }
108#endif
109
110#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
111#include <linux/leds.h>
112
113static struct gpio_led cm_t35_leds[] = {
114 [0] = {
115 .gpio = 186,
116 .name = "cm-t35:green",
117 .default_trigger = "heartbeat",
118 .active_low = 0,
119 },
120};
121
122static struct gpio_led_platform_data cm_t35_led_pdata = {
123 .num_leds = ARRAY_SIZE(cm_t35_leds),
124 .leds = cm_t35_leds,
125};
126
127static struct platform_device cm_t35_led_device = {
128 .name = "leds-gpio",
129 .id = -1,
130 .dev = {
131 .platform_data = &cm_t35_led_pdata,
132 },
133};
134
135static void __init cm_t35_init_led(void)
136{
137 platform_device_register(&cm_t35_led_device);
138}
139#else
140static inline void cm_t35_init_led(void) {}
141#endif
142
143#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
144#include <linux/mtd/mtd.h>
145#include <linux/mtd/nand.h>
146#include <linux/mtd/partitions.h>
147
148static struct mtd_partition cm_t35_nand_partitions[] = {
149 {
150 .name = "xloader",
151 .offset = 0, /* Offset = 0x00000 */
152 .size = 4 * NAND_BLOCK_SIZE,
153 .mask_flags = MTD_WRITEABLE
154 },
155 {
156 .name = "uboot",
157 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
158 .size = 15 * NAND_BLOCK_SIZE,
159 },
160 {
161 .name = "uboot environment",
162 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
163 .size = 2 * NAND_BLOCK_SIZE,
164 },
165 {
166 .name = "linux",
d12c2e28 167 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
2886d128
MR		 168 .size = 32 * NAND_BLOCK_SIZE,
169 },
170 {
171 .name = "rootfs",
d12c2e28 172 .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
2886d128
MR		 173 .size = MTDPART_SIZ_FULL,
174 },
175};
176
177static struct omap_nand_platform_data cm_t35_nand_data = {
178 .parts = cm_t35_nand_partitions,
179 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
2886d128 180 .cs = 0,
2886d128
MR		 181};
182
2886d128
MR		 183static void __init cm_t35_init_nand(void)
184{
bc3668ea 185 if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
2886d128
MR		 186 pr_err("CM-T35: Unable to register NAND device\n");
187}
188#else
189static inline void cm_t35_init_nand(void) {}
190#endif
191
7f049ad1
MR		 192#define CM_T35_LCD_EN_GPIO 157
193#define CM_T35_LCD_BL_GPIO 58
194#define CM_T35_DVI_EN_GPIO 54
195
7f049ad1
MR		 196static int lcd_enabled;
197static int dvi_enabled;
198
199static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
200{
201 if (dvi_enabled) {
202 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
203 return -EINVAL;
204 }
205
bc593f5d
IG		 206 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
207 gpio_set_value(CM_T35_LCD_BL_GPIO, 1);
7f049ad1
MR		 208
209 lcd_enabled = 1;
210
211 return 0;
212}
213
214static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
215{
216 lcd_enabled = 0;
217
bc593f5d
IG		 218 gpio_set_value(CM_T35_LCD_BL_GPIO, 0);
219 gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
7f049ad1
MR		 220}
221
7f049ad1
MR		 222static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
223{
224 return 0;
225}
226
227static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev)
228{
229}
230
89747c91
BW		 231static struct panel_generic_dpi_data lcd_panel = {
232 .name = "toppoly_tdo35s",
233 .platform_enable = cm_t35_panel_enable_lcd,
234 .platform_disable = cm_t35_panel_disable_lcd,
235};
236
7f049ad1
MR		 237static struct omap_dss_device cm_t35_lcd_device = {
238 .name = "lcd",
7f049ad1 239 .type = OMAP_DISPLAY_TYPE_DPI,
89747c91
BW		 240 .driver_name = "generic_dpi_panel",
241 .data = &lcd_panel,
7f049ad1 242 .phy.dpi.data_lines = 18,
89747c91
BW		 243};
244
2e6f2ee7 245static struct tfp410_platform_data dvi_panel = {
e813a55e 246 .power_down_gpio = CM_T35_DVI_EN_GPIO,
7f049ad1
MR		 247};
248
249static struct omap_dss_device cm_t35_dvi_device = {
250 .name = "dvi",
7f049ad1 251 .type = OMAP_DISPLAY_TYPE_DPI,
2e6f2ee7 252 .driver_name = "tfp410",
89747c91 253 .data = &dvi_panel,
7f049ad1 254 .phy.dpi.data_lines = 24,
7f049ad1
MR		 255};
256
257static struct omap_dss_device cm_t35_tv_device = {
258 .name = "tv",
259 .driver_name = "venc",
260 .type = OMAP_DISPLAY_TYPE_VENC,
261 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
262 .platform_enable = cm_t35_panel_enable_tv,
263 .platform_disable = cm_t35_panel_disable_tv,
264};
265
266static struct omap_dss_device *cm_t35_dss_devices[] = {
267 &cm_t35_lcd_device,
268 &cm_t35_dvi_device,
269 &cm_t35_tv_device,
270};
271
272static struct omap_dss_board_info cm_t35_dss_data = {
273 .num_devices = ARRAY_SIZE(cm_t35_dss_devices),
274 .devices = cm_t35_dss_devices,
275 .default_device = &cm_t35_dvi_device,
276};
277
7f049ad1
MR		 278static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
279 .turbo_mode = 0,
7f049ad1
MR		 280};
281
282static struct tdo24m_platform_data tdo24m_config = {
283 .model = TDO35S,
284};
285
286static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
287 {
288 .modalias = "tdo24m",
289 .bus_num = 4,
290 .chip_select = 0,
291 .max_speed_hz = 1000000,
292 .controller_data = &tdo24m_mcspi_config,
293 .platform_data = &tdo24m_config,
294 },
295};
296
bc593f5d
IG		 297static struct gpio cm_t35_dss_gpios[] __initdata = {
298 { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" },
299 { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" },
bc593f5d
IG		 300};
301
7f049ad1
MR		 302static void __init cm_t35_init_display(void)
303{
304 int err;
305
7f049ad1
MR		 306 spi_register_board_info(cm_t35_lcd_spi_board_info,
307 ARRAY_SIZE(cm_t35_lcd_spi_board_info));
308
bc593f5d
IG		 309 err = gpio_request_array(cm_t35_dss_gpios,
310 ARRAY_SIZE(cm_t35_dss_gpios));
7f049ad1 311 if (err) {
bc593f5d
IG		 312 pr_err("CM-T35: failed to request DSS control GPIOs\n");
313 return;
7f049ad1
MR		 314 }
315
bc593f5d
IG		 316 gpio_export(CM_T35_LCD_EN_GPIO, 0);
317 gpio_export(CM_T35_LCD_BL_GPIO, 0);
7f049ad1
MR		 318
319 msleep(50);
bc593f5d 320 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
7f049ad1 321
d5e13227 322 err = omap_display_init(&cm_t35_dss_data);
7f049ad1
MR		 323 if (err) {
324 pr_err("CM-T35: failed to register DSS device\n");
bc593f5d 325 gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios));
7f049ad1 326 }
7f049ad1
MR		 327}
328
786b01a8
OD		 329static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
330 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
2886d128
MR		 331};
332
786b01a8
OD		 333static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
334 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
2886d128
MR		 335};
336
b74f149c
IG		 337static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
338 REGULATOR_SUPPLY("vcc", "spi1.0"),
cd1c683c
IG		 339 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
340 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
b74f149c
IG		 341};
342
2886d128
MR		 343/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
344static struct regulator_init_data cm_t35_vmmc1 = {
345 .constraints = {
346 .min_uV = 1850000,
347 .max_uV = 3150000,
348 .valid_modes_mask = REGULATOR_MODE_NORMAL
349 | REGULATOR_MODE_STANDBY,
350 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
351 | REGULATOR_CHANGE_MODE
352 | REGULATOR_CHANGE_STATUS,
353 },
786b01a8
OD		 354 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
355 .consumer_supplies = cm_t35_vmmc1_supply,
2886d128
MR		 356};
357
358/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
359static struct regulator_init_data cm_t35_vsim = {
360 .constraints = {
361 .min_uV = 1800000,
362 .max_uV = 3000000,
363 .valid_modes_mask = REGULATOR_MODE_NORMAL
364 | REGULATOR_MODE_STANDBY,
365 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
366 | REGULATOR_CHANGE_MODE
367 | REGULATOR_CHANGE_STATUS,
368 },
786b01a8
OD		 369 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
370 .consumer_supplies = cm_t35_vsim_supply,
2886d128
MR		 371};
372
b74f149c
IG		 373static struct regulator_init_data cm_t35_vio = {
374 .constraints = {
375 .min_uV = 1800000,
376 .max_uV = 1800000,
377 .apply_uV = true,
378 .valid_modes_mask = REGULATOR_MODE_NORMAL
379 | REGULATOR_MODE_STANDBY,
380 .valid_ops_mask = REGULATOR_CHANGE_MODE,
381 },
382 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies),
383 .consumer_supplies = cm_t35_vio_supplies,
384};
385
bead4375 386static uint32_t cm_t35_keymap[] = {
2886d128
MR		 387 KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
388 KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
389 KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D),
390};
391
392static struct matrix_keymap_data cm_t35_keymap_data = {
393 .keymap = cm_t35_keymap,
394 .keymap_size = ARRAY_SIZE(cm_t35_keymap),
395};
396
397static struct twl4030_keypad_data cm_t35_kp_data = {
398 .keymap_data = &cm_t35_keymap_data,
399 .rows = 3,
400 .cols = 3,
401 .rep = 1,
402};
403
68ff0423 404static struct omap2_hsmmc_info mmc[] = {
2886d128
MR		 405 {
406 .mmc = 1,
3a63833e 407 .caps = MMC_CAP_4_BIT_DATA,
2886d128
MR		 408 .gpio_cd = -EINVAL,
409 .gpio_wp = -EINVAL,
3b972bf0 410 .deferred = true,
2886d128
MR		 411 },
412 {
413 .mmc = 2,
3a63833e 414 .caps = MMC_CAP_4_BIT_DATA,
2886d128
MR		 415 .transceiver = 1,
416 .gpio_cd = -EINVAL,
417 .gpio_wp = -EINVAL,
418 .ocr_mask = 0x00100000, /* 3.3V */
419 },
420 {} /* Terminator */
421};
422
181b250c
KM		 423static struct usbhs_omap_board_data usbhs_bdata __initdata = {
424 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
425 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
426 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
2886d128
MR		 427
428 .phy_reset = true,
1a6b5923
BW		 429 .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6,
430 .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7,
2886d128
MR		 431 .reset_gpio_port[2] = -EINVAL
432};
433
36863964 434static void __init cm_t35_init_usbh(void)
039401f3
IG		 435{
436 int err;
437
438 err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
439 GPIOF_OUT_INIT_LOW, "usb hub rst");
440 if (err) {
441 pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
442 } else {
443 udelay(10);
444 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
445 msleep(1);
446 }
447
448 usbhs_init(&usbhs_bdata);
449}
450
2886d128
MR		 451static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
452 unsigned ngpio)
453{
454 int wlan_rst = gpio + 2;
455
bc593f5d 456 if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
2886d128 457 gpio_export(wlan_rst, 0);
2886d128 458 udelay(10);
be741de1 459 gpio_set_value_cansleep(wlan_rst, 0);
2886d128 460 udelay(10);
be741de1 461 gpio_set_value_cansleep(wlan_rst, 1);
2886d128
MR		 462 } else {
463 pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
464 }
465
466 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
467 mmc[0].gpio_cd = gpio + 0;
3b972bf0 468 omap_hsmmc_late_init(mmc);
2886d128 469
2886d128
MR		 470 return 0;
471}
472
473static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
2886d128
MR		 474 .setup = cm_t35_twl_gpio_setup,
475};
476
d61676b8
IG		 477static struct twl4030_power_data cm_t35_power_data = {
478 .use_poweroff = true,
479};
480
2886d128 481static struct twl4030_platform_data cm_t35_twldata = {
2886d128
MR		 482 /* platform_data for children goes here */
483 .keypad = &cm_t35_kp_data,
2886d128
MR		 484 .gpio = &cm_t35_gpio_data,
485 .vmmc1 = &cm_t35_vmmc1,
486 .vsim = &cm_t35_vsim,
b74f149c 487 .vio = &cm_t35_vio,
d61676b8 488 .power = &cm_t35_power_data,
2886d128
MR		 489};
490
d396be47
DL		 491#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
492#include <media/omap3isp.h>
493#include "devices.h"
494
495static struct i2c_board_info cm_t35_isp_i2c_boardinfo[] = {
496 {
497 I2C_BOARD_INFO("mt9t001", 0x5d),
498 },
3d6bbca9
DL		 499 {
500 I2C_BOARD_INFO("tvp5150", 0x5c),
501 },
d396be47
DL		 502};
503
504static struct isp_subdev_i2c_board_info cm_t35_isp_primary_subdevs[] = {
505 {
506 .board_info = &cm_t35_isp_i2c_boardinfo[0],
507 .i2c_adapter_id = 3,
508 },
509 { NULL, 0, },
510};
511
3d6bbca9
DL		 512static struct isp_subdev_i2c_board_info cm_t35_isp_secondary_subdevs[] = {
513 {
514 .board_info = &cm_t35_isp_i2c_boardinfo[1],
515 .i2c_adapter_id = 3,
516 },
517 { NULL, 0, },
518};
519
d396be47
DL		 520static struct isp_v4l2_subdevs_group cm_t35_isp_subdevs[] = {
521 {
522 .subdevs = cm_t35_isp_primary_subdevs,
523 .interface = ISP_INTERFACE_PARALLEL,
524 .bus = {
525 .parallel = {
526 .clk_pol = 1,
527 },
528 },
529 },
3d6bbca9
DL		 530 {
531 .subdevs = cm_t35_isp_secondary_subdevs,
532 .interface = ISP_INTERFACE_PARALLEL,
533 .bus = {
534 .parallel = {
535 .clk_pol = 0,
536 },
537 },
538 },
d396be47
DL		 539 { NULL, 0, },
540};
541
542static struct isp_platform_data cm_t35_isp_pdata = {
543 .subdevs = cm_t35_isp_subdevs,
544};
545
546static void __init cm_t35_init_camera(void)
547{
548 if (omap3_init_camera(&cm_t35_isp_pdata) < 0)
549 pr_warn("CM-T3x: Failed registering camera device!\n");
550}
551
552#else
553static inline void cm_t35_init_camera(void) {}
554#endif /* CONFIG_VIDEO_OMAP3 */
555
2886d128
MR		 556static void __init cm_t35_init_i2c(void)
557{
b252b0ef 558 omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
19ce6439
IG		 559 TWL_COMMON_REGULATOR_VDAC |
560 TWL_COMMON_PDATA_AUDIO);
b252b0ef 561
fbd8071c 562 omap3_pmic_init("tps65930", &cm_t35_twldata);
d396be47
DL		 563
564 omap_register_i2c_bus(3, 400, NULL, 0);
2886d128
MR		 565}
566
c7ecea24 567#ifdef CONFIG_OMAP_MUX
ca5742bd 568static struct omap_board_mux board_mux[] __initdata = {
edc961a2
MR		 569 /* nCS and IRQ for CM-T35 ethernet */
570 OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
571 OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
572
573 /* nCS and IRQ for SB-T35 ethernet */
574 OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
575 OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
576
577 /* PENDOWN GPIO */
578 OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
579
580 /* mUSB */
581 OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
582 OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
583 OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
584 OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
585 OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
586 OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
587 OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
588 OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
589 OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
590 OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
591 OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
592 OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
593
594 /* MMC 2 */
595 OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
596 OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
597 OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
598 OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
599
600 /* McSPI 1 */
601 OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
602 OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
603 OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
604 OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
605
606 /* McSPI 4 */
607 OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
608 OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
609 OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
610 OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
611
612 /* McBSP 2 */
613 OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
614 OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
615 OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
616 OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
617
618 /* serial ports */
619 OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
620 OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
621 OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
622 OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
623
c3146974 624 /* common DSS */
edc961a2
MR		 625 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
626 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
627 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
628 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
edc961a2
MR		 629 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
630 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
631 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
632 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
633 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
634 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
635 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
636 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
637 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
638 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
639 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
640 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
edc961a2 641
d396be47
DL		 642 /* Camera */
643 OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
644 OMAP3_MUX(CAM_VS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
645 OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
646 OMAP3_MUX(CAM_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
647 OMAP3_MUX(CAM_FLD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
648 OMAP3_MUX(CAM_D0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
649 OMAP3_MUX(CAM_D1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
650 OMAP3_MUX(CAM_D2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
651 OMAP3_MUX(CAM_D3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
652 OMAP3_MUX(CAM_D4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
653 OMAP3_MUX(CAM_D5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
654 OMAP3_MUX(CAM_D6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
655 OMAP3_MUX(CAM_D7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
656 OMAP3_MUX(CAM_D8, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
657 OMAP3_MUX(CAM_D9, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
658 OMAP3_MUX(CAM_STROBE, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
659
660 OMAP3_MUX(CAM_D10, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
661 OMAP3_MUX(CAM_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
662
7f049ad1
MR		 663 /* display controls */
664 OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
665 OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
666 OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
667
edc961a2
MR		 668 /* TPS IRQ */
669 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
670 OMAP_PIN_INPUT_PULLUP),
671
ca5742bd
TL		 672 { .reg_offset = OMAP_MUX_TERMINATOR },
673};
c3146974
IG		 674
675static void __init cm_t3x_common_dss_mux_init(int mux_mode)
676{
677 omap_mux_init_signal("dss_data18", mux_mode);
678 omap_mux_init_signal("dss_data19", mux_mode);
679 omap_mux_init_signal("dss_data20", mux_mode);
680 omap_mux_init_signal("dss_data21", mux_mode);
681 omap_mux_init_signal("dss_data22", mux_mode);
682 omap_mux_init_signal("dss_data23", mux_mode);
683}
684
685static void __init cm_t35_init_mux(void)
686{
b2404f42
IG		 687 int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
688
689 omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
690 omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
691 omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
692 omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
693 omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
694 omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
695 cm_t3x_common_dss_mux_init(mux_mode);
c3146974
IG		 696}
697
698static void __init cm_t3730_init_mux(void)
699{
b2404f42
IG		 700 int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
701
702 omap_mux_init_signal("sys_boot0", mux_mode);
703 omap_mux_init_signal("sys_boot1", mux_mode);
704 omap_mux_init_signal("sys_boot3", mux_mode);
705 omap_mux_init_signal("sys_boot4", mux_mode);
706 omap_mux_init_signal("sys_boot5", mux_mode);
707 omap_mux_init_signal("sys_boot6", mux_mode);
708 cm_t3x_common_dss_mux_init(mux_mode);
c3146974
IG		 709}
710#else
711static inline void cm_t35_init_mux(void) {}
712static inline void cm_t3730_init_mux(void) {}
c7ecea24 713#endif
ca5742bd 714
c3146974 715static void __init cm_t3x_common_init(void)
2886d128 716{
ca5742bd 717 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
2886d128 718 omap_serial_init();
a4ca9dbe
TL		 719 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
720 mt46h32m32lf6_sdrc_params);
3b972bf0 721 omap_hsmmc_init(mmc);
2886d128 722 cm_t35_init_i2c();
96974a24 723 omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
2886d128
MR		 724 cm_t35_init_ethernet();
725 cm_t35_init_led();
7f049ad1 726 cm_t35_init_display();
ac51c90f 727 omap_twl4030_audio_init("cm-t3x");
2886d128 728
9e18630b 729 usb_musb_init(NULL);
039401f3 730 cm_t35_init_usbh();
d396be47 731 cm_t35_init_camera();
2886d128
MR		 732}
733
c3146974
IG		 734static void __init cm_t35_init(void)
735{
736 cm_t3x_common_init();
737 cm_t35_init_mux();
738 cm_t35_init_nand();
739}
740
741static void __init cm_t3730_init(void)
742{
743 cm_t3x_common_init();
744 cm_t3730_init_mux();
745}
746
2886d128 747MACHINE_START(CM_T35, "Compulab CM-T35")
5e52b435 748 .atag_offset = 0x100,
71ee7dad 749 .reserve = omap_reserve,
3dc3bad6 750 .map_io = omap3_map_io,
8f5b5a41 751 .init_early = omap35xx_init_early,
741e3a89 752 .init_irq = omap3_init_irq,
6b2f55d7 753 .handle_irq = omap3_intc_handle_irq,
2886d128 754 .init_machine = cm_t35_init,
bbd707ac 755 .init_late = omap35xx_init_late,
e74984e4 756 .timer = &omap3_timer,
baa95883 757 .restart = omap_prcm_restart,
2886d128 758MACHINE_END
c3146974
IG		 759
760MACHINE_START(CM_T3730, "Compulab CM-T3730")
5e52b435 761 .atag_offset = 0x100,
c3146974
IG		 762 .reserve = omap_reserve,
763 .map_io = omap3_map_io,
8f5b5a41 764 .init_early = omap3630_init_early,
c3146974 765 .init_irq = omap3_init_irq,
6b2f55d7 766 .handle_irq = omap3_intc_handle_irq,
c3146974 767 .init_machine = cm_t3730_init,
bbd707ac 768 .init_late = omap3630_init_late,
c3146974 769 .timer = &omap3_timer,
baa95883 770 .restart = omap_prcm_restart,
c3146974 771MACHINE_END
Linux kernel - Deliverables
This page took 0.231645 seconds and 5 git commands to generate.