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Merge tag 'ipvs2-for-v3.19' of https://git.kernel.org/pub/scm/linux/kernel/git/horms...
[deliverable/linux.git] / arch / arm / mach-omap2 / board-cm-t35.c
CommitLineData
2886d128 1/*
c3146974 2 * CompuLab CM-T35/CM-T3730 modules support
2886d128 3 *
d12c2e28
IG		 4 * Copyright (C) 2009-2011 CompuLab, Ltd.
5 * Authors: Mike Rapoport <mike@compulab.co.il>
6 * Igor Grinberg <grinberg@compulab.co.il>
2886d128
MR		 7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
2886d128
MR		 17 */
18
e68084c6
LP		 19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
2886d128
MR		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24#include <linux/input.h>
25#include <linux/input/matrix_keypad.h>
26#include <linux/delay.h>
27#include <linux/gpio.h>
e639cd5b 28#include <linux/omap-gpmc.h>
4b25408f 29#include <linux/platform_data/gpio-omap.h>
2886d128 30
25f73ed5 31#include <linux/platform_data/at24.h>
ebeb53e1 32#include <linux/i2c/twl.h>
5b3689f4 33#include <linux/regulator/fixed.h>
2886d128 34#include <linux/regulator/machine.h>
3a63833e 35#include <linux/mmc/host.h>
51482be9 36#include <linux/usb/phy.h>
2886d128 37
7f049ad1
MR		 38#include <linux/spi/spi.h>
39#include <linux/spi/tdo24m.h>
40
2886d128
MR		 41#include <asm/mach-types.h>
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44
2203747c 45#include <linux/platform_data/mtd-nand-omap2.h>
a0b38cc4 46#include <video/omapdss.h>
a0d8dde9 47#include <video/omap-panel-data.h>
2203747c 48#include <linux/platform_data/spi-omap2-mcspi.h>
2886d128 49
6d02643d 50#include "common.h"
ca5742bd 51#include "mux.h"
2886d128 52#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 53#include "hsmmc.h"
96974a24 54#include "common-board-devices.h"
2886d128 55
039401f3
IG		 56#define CM_T35_GPIO_PENDOWN 57
57#define SB_T35_USB_HUB_RESET_GPIO 167
2886d128
MR		 58
59#define CM_T35_SMSC911X_CS 5
60#define CM_T35_SMSC911X_GPIO 163
61#define SB_T35_SMSC911X_CS 4
62#define SB_T35_SMSC911X_GPIO 65
63
2886d128
MR		 64#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
65#include <linux/smsc911x.h>
ac839b3c 66#include "gpmc-smsc911x.h"
2886d128 67
21b42731 68static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
2886d128 69 .id = 0,
21b42731
MR		 70 .cs = CM_T35_SMSC911X_CS,
71 .gpio_irq = CM_T35_SMSC911X_GPIO,
72 .gpio_reset = -EINVAL,
73 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
2886d128
MR		 74};
75
21b42731 76static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
2886d128 77 .id = 1,
21b42731
MR		 78 .cs = SB_T35_SMSC911X_CS,
79 .gpio_irq = SB_T35_SMSC911X_GPIO,
80 .gpio_reset = -EINVAL,
81 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
2886d128
MR		 82};
83
5b3689f4
RD		 84static struct regulator_consumer_supply cm_t35_smsc911x_supplies[] = {
85 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
86 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
87};
88
89static struct regulator_consumer_supply sb_t35_smsc911x_supplies[] = {
90 REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
91 REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
92};
93
2886d128
MR		 94static void __init cm_t35_init_ethernet(void)
95{
5b3689f4
RD		 96 regulator_register_fixed(0, cm_t35_smsc911x_supplies,
97 ARRAY_SIZE(cm_t35_smsc911x_supplies));
98 regulator_register_fixed(1, sb_t35_smsc911x_supplies,
99 ARRAY_SIZE(sb_t35_smsc911x_supplies));
100
21b42731
MR		 101 gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
102 gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
2886d128
MR		 103}
104#else
105static inline void __init cm_t35_init_ethernet(void) { return; }
106#endif
107
108#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
109#include <linux/leds.h>
110
111static struct gpio_led cm_t35_leds[] = {
112 [0] = {
113 .gpio = 186,
114 .name = "cm-t35:green",
115 .default_trigger = "heartbeat",
116 .active_low = 0,
117 },
118};
119
120static struct gpio_led_platform_data cm_t35_led_pdata = {
121 .num_leds = ARRAY_SIZE(cm_t35_leds),
122 .leds = cm_t35_leds,
123};
124
125static struct platform_device cm_t35_led_device = {
126 .name = "leds-gpio",
127 .id = -1,
128 .dev = {
129 .platform_data = &cm_t35_led_pdata,
130 },
131};
132
133static void __init cm_t35_init_led(void)
134{
135 platform_device_register(&cm_t35_led_device);
136}
137#else
138static inline void cm_t35_init_led(void) {}
139#endif
140
141#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
142#include <linux/mtd/mtd.h>
143#include <linux/mtd/nand.h>
144#include <linux/mtd/partitions.h>
145
146static struct mtd_partition cm_t35_nand_partitions[] = {
147 {
148 .name = "xloader",
149 .offset = 0, /* Offset = 0x00000 */
150 .size = 4 * NAND_BLOCK_SIZE,
151 .mask_flags = MTD_WRITEABLE
152 },
153 {
154 .name = "uboot",
155 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
156 .size = 15 * NAND_BLOCK_SIZE,
157 },
158 {
159 .name = "uboot environment",
160 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
161 .size = 2 * NAND_BLOCK_SIZE,
162 },
163 {
164 .name = "linux",
d12c2e28 165 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
2886d128
MR		 166 .size = 32 * NAND_BLOCK_SIZE,
167 },
168 {
169 .name = "rootfs",
d12c2e28 170 .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
2886d128
MR		 171 .size = MTDPART_SIZ_FULL,
172 },
173};
174
175static struct omap_nand_platform_data cm_t35_nand_data = {
176 .parts = cm_t35_nand_partitions,
177 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
2886d128 178 .cs = 0,
2886d128
MR		 179};
180
2886d128
MR		 181static void __init cm_t35_init_nand(void)
182{
bc3668ea 183 if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
2886d128
MR		 184 pr_err("CM-T35: Unable to register NAND device\n");
185}
186#else
187static inline void cm_t35_init_nand(void) {}
188#endif
189
7f049ad1
MR		 190#define CM_T35_LCD_EN_GPIO 157
191#define CM_T35_LCD_BL_GPIO 58
192#define CM_T35_DVI_EN_GPIO 54
193
fe0cf7d9
TV		 194static const struct display_timing cm_t35_lcd_videomode = {
195 .pixelclock = { 0, 26000000, 0 },
196
197 .hactive = { 0, 480, 0 },
198 .hfront_porch = { 0, 104, 0 },
199 .hback_porch = { 0, 8, 0 },
200 .hsync_len = { 0, 8, 0 },
201
202 .vactive = { 0, 640, 0 },
203 .vfront_porch = { 0, 4, 0 },
204 .vback_porch = { 0, 2, 0 },
205 .vsync_len = { 0, 2, 0 },
206
207 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
208 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE,
209};
210
211static struct panel_dpi_platform_data cm_t35_lcd_pdata = {
212 .name = "lcd",
213 .source = "dpi.0",
214
215 .data_lines = 18,
216
217 .display_timing = &cm_t35_lcd_videomode,
218
219 .enable_gpio = -1,
220 .backlight_gpio = CM_T35_LCD_BL_GPIO,
221};
222
223static struct platform_device cm_t35_lcd_device = {
224 .name = "panel-dpi",
225 .id = 0,
226 .dev.platform_data = &cm_t35_lcd_pdata,
89747c91
BW		 227};
228
fe0cf7d9
TV		 229static struct connector_dvi_platform_data cm_t35_dvi_connector_pdata = {
230 .name = "dvi",
231 .source = "tfp410.0",
232 .i2c_bus_num = -1,
89747c91
BW		 233};
234
fe0cf7d9
TV		 235static struct platform_device cm_t35_dvi_connector_device = {
236 .name = "connector-dvi",
237 .id = 0,
238 .dev.platform_data = &cm_t35_dvi_connector_pdata,
7f049ad1
MR		 239};
240
fe0cf7d9
TV		 241static struct encoder_tfp410_platform_data cm_t35_tfp410_pdata = {
242 .name = "tfp410.0",
243 .source = "dpi.0",
244 .data_lines = 24,
245 .power_down_gpio = CM_T35_DVI_EN_GPIO,
7f049ad1
MR		 246};
247
fe0cf7d9
TV		 248static struct platform_device cm_t35_tfp410_device = {
249 .name = "tfp410",
250 .id = 0,
251 .dev.platform_data = &cm_t35_tfp410_pdata,
7f049ad1
MR		 252};
253
fe0cf7d9
TV		 254static struct connector_atv_platform_data cm_t35_tv_pdata = {
255 .name = "tv",
256 .source = "venc.0",
257 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
258 .invert_polarity = false,
259};
260
261static struct platform_device cm_t35_tv_connector_device = {
262 .name = "connector-analog-tv",
263 .id = 0,
264 .dev.platform_data = &cm_t35_tv_pdata,
7f049ad1
MR		 265};
266
267static struct omap_dss_board_info cm_t35_dss_data = {
fe0cf7d9 268 .default_display_name = "dvi",
7f049ad1
MR		 269};
270
7f049ad1
MR		 271static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
272 .turbo_mode = 0,
7f049ad1
MR		 273};
274
275static struct tdo24m_platform_data tdo24m_config = {
276 .model = TDO35S,
277};
278
279static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
280 {
281 .modalias = "tdo24m",
282 .bus_num = 4,
283 .chip_select = 0,
284 .max_speed_hz = 1000000,
285 .controller_data = &tdo24m_mcspi_config,
286 .platform_data = &tdo24m_config,
287 },
288};
289
290static void __init cm_t35_init_display(void)
291{
292 int err;
293
7f049ad1
MR		 294 spi_register_board_info(cm_t35_lcd_spi_board_info,
295 ARRAY_SIZE(cm_t35_lcd_spi_board_info));
296
e471e9ad
TV		 297
298 err = gpio_request_one(CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,
299 "lcd bl enable");
7f049ad1 300 if (err) {
e471e9ad 301 pr_err("CM-T35: failed to request LCD EN GPIO\n");
bc593f5d 302 return;
7f049ad1
MR		 303 }
304
7f049ad1 305 msleep(50);
bc593f5d 306 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
7f049ad1 307
d5e13227 308 err = omap_display_init(&cm_t35_dss_data);
7f049ad1
MR		 309 if (err) {
310 pr_err("CM-T35: failed to register DSS device\n");
e471e9ad 311 gpio_free(CM_T35_LCD_EN_GPIO);
7f049ad1 312 }
fe0cf7d9
TV		 313
314 platform_device_register(&cm_t35_tfp410_device);
315 platform_device_register(&cm_t35_dvi_connector_device);
316 platform_device_register(&cm_t35_lcd_device);
317 platform_device_register(&cm_t35_tv_connector_device);
7f049ad1
MR		 318}
319
786b01a8
OD		 320static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
321 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
2886d128
MR		 322};
323
786b01a8
OD		 324static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
325 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
2886d128
MR		 326};
327
b74f149c
IG		 328static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
329 REGULATOR_SUPPLY("vcc", "spi1.0"),
cd1c683c 330 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
1f92a1a4 331 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
1738ddbe 332 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
b74f149c
IG		 333};
334
2886d128
MR		 335/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
336static struct regulator_init_data cm_t35_vmmc1 = {
337 .constraints = {
338 .min_uV = 1850000,
339 .max_uV = 3150000,
340 .valid_modes_mask = REGULATOR_MODE_NORMAL
341 | REGULATOR_MODE_STANDBY,
342 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
343 | REGULATOR_CHANGE_MODE
344 | REGULATOR_CHANGE_STATUS,
345 },
786b01a8
OD		 346 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
347 .consumer_supplies = cm_t35_vmmc1_supply,
2886d128
MR		 348};
349
350/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
351static struct regulator_init_data cm_t35_vsim = {
352 .constraints = {
353 .min_uV = 1800000,
354 .max_uV = 3000000,
355 .valid_modes_mask = REGULATOR_MODE_NORMAL
356 | REGULATOR_MODE_STANDBY,
357 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
358 | REGULATOR_CHANGE_MODE
359 | REGULATOR_CHANGE_STATUS,
360 },
786b01a8
OD		 361 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
362 .consumer_supplies = cm_t35_vsim_supply,
2886d128
MR		 363};
364
b74f149c
IG		 365static struct regulator_init_data cm_t35_vio = {
366 .constraints = {
367 .min_uV = 1800000,
368 .max_uV = 1800000,
369 .apply_uV = true,
370 .valid_modes_mask = REGULATOR_MODE_NORMAL
371 | REGULATOR_MODE_STANDBY,
372 .valid_ops_mask = REGULATOR_CHANGE_MODE,
373 },
374 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies),
375 .consumer_supplies = cm_t35_vio_supplies,
376};
377
bead4375 378static uint32_t cm_t35_keymap[] = {
2886d128
MR		 379 KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
380 KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
381 KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D),
382};
383
384static struct matrix_keymap_data cm_t35_keymap_data = {
385 .keymap = cm_t35_keymap,
386 .keymap_size = ARRAY_SIZE(cm_t35_keymap),
387};
388
389static struct twl4030_keypad_data cm_t35_kp_data = {
390 .keymap_data = &cm_t35_keymap_data,
391 .rows = 3,
392 .cols = 3,
393 .rep = 1,
394};
395
68ff0423 396static struct omap2_hsmmc_info mmc[] = {
2886d128
MR		 397 {
398 .mmc = 1,
3a63833e 399 .caps = MMC_CAP_4_BIT_DATA,
2886d128
MR		 400 .gpio_cd = -EINVAL,
401 .gpio_wp = -EINVAL,
3b972bf0 402 .deferred = true,
2886d128
MR		 403 },
404 {
405 .mmc = 2,
3a63833e 406 .caps = MMC_CAP_4_BIT_DATA,
2886d128
MR		 407 .transceiver = 1,
408 .gpio_cd = -EINVAL,
409 .gpio_wp = -EINVAL,
410 .ocr_mask = 0x00100000, /* 3.3V */
411 },
412 {} /* Terminator */
413};
414
59b1499a
RQ		 415static struct usbhs_phy_data phy_data[] __initdata = {
416 {
417 .port = 1,
418 .reset_gpio = OMAP_MAX_GPIO_LINES + 6,
419 .vcc_gpio = -EINVAL,
420 },
421 {
422 .port = 2,
423 .reset_gpio = OMAP_MAX_GPIO_LINES + 7,
424 .vcc_gpio = -EINVAL,
425 },
426};
427
42973159 428static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
181b250c
KM		 429 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
430 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
2886d128
MR		 431};
432
36863964 433static void __init cm_t35_init_usbh(void)
039401f3
IG		 434{
435 int err;
436
437 err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
438 GPIOF_OUT_INIT_LOW, "usb hub rst");
439 if (err) {
440 pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
441 } else {
442 udelay(10);
443 gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
444 msleep(1);
445 }
446
59b1499a 447 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
039401f3
IG		 448 usbhs_init(&usbhs_bdata);
449}
450
2886d128
MR		 451static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
452 unsigned ngpio)
453{
454 int wlan_rst = gpio + 2;
455
bc593f5d 456 if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
2886d128 457 gpio_export(wlan_rst, 0);
2886d128 458 udelay(10);
be741de1 459 gpio_set_value_cansleep(wlan_rst, 0);
2886d128 460 udelay(10);
be741de1 461 gpio_set_value_cansleep(wlan_rst, 1);
2886d128
MR		 462 } else {
463 pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
464 }
465
466 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
467 mmc[0].gpio_cd = gpio + 0;
3b972bf0 468 omap_hsmmc_late_init(mmc);
2886d128 469
2886d128
MR		 470 return 0;
471}
472
473static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
2886d128
MR		 474 .setup = cm_t35_twl_gpio_setup,
475};
476
d61676b8
IG		 477static struct twl4030_power_data cm_t35_power_data = {
478 .use_poweroff = true,
479};
480
2886d128 481static struct twl4030_platform_data cm_t35_twldata = {
2886d128
MR		 482 /* platform_data for children goes here */
483 .keypad = &cm_t35_kp_data,
2886d128
MR		 484 .gpio = &cm_t35_gpio_data,
485 .vmmc1 = &cm_t35_vmmc1,
486 .vsim = &cm_t35_vsim,
b74f149c 487 .vio = &cm_t35_vio,
d61676b8 488 .power = &cm_t35_power_data,
2886d128
MR		 489};
490
d396be47
DL		 491#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
492#include <media/omap3isp.h>
493#include "devices.h"
494
495static struct i2c_board_info cm_t35_isp_i2c_boardinfo[] = {
496 {
497 I2C_BOARD_INFO("mt9t001", 0x5d),
498 },
3d6bbca9
DL		 499 {
500 I2C_BOARD_INFO("tvp5150", 0x5c),
501 },
d396be47
DL		 502};
503
504static struct isp_subdev_i2c_board_info cm_t35_isp_primary_subdevs[] = {
505 {
506 .board_info = &cm_t35_isp_i2c_boardinfo[0],
507 .i2c_adapter_id = 3,
508 },
509 { NULL, 0, },
510};
511
3d6bbca9
DL		 512static struct isp_subdev_i2c_board_info cm_t35_isp_secondary_subdevs[] = {
513 {
514 .board_info = &cm_t35_isp_i2c_boardinfo[1],
515 .i2c_adapter_id = 3,
516 },
517 { NULL, 0, },
518};
519
d396be47
DL		 520static struct isp_v4l2_subdevs_group cm_t35_isp_subdevs[] = {
521 {
522 .subdevs = cm_t35_isp_primary_subdevs,
523 .interface = ISP_INTERFACE_PARALLEL,
524 .bus = {
525 .parallel = {
526 .clk_pol = 1,
527 },
528 },
529 },
3d6bbca9
DL		 530 {
531 .subdevs = cm_t35_isp_secondary_subdevs,
532 .interface = ISP_INTERFACE_PARALLEL,
533 .bus = {
534 .parallel = {
535 .clk_pol = 0,
536 },
537 },
538 },
d396be47
DL		 539 { NULL, 0, },
540};
541
542static struct isp_platform_data cm_t35_isp_pdata = {
543 .subdevs = cm_t35_isp_subdevs,
544};
545
e68084c6
LP		 546static struct regulator_consumer_supply cm_t35_camera_supplies[] = {
547 REGULATOR_SUPPLY("vaa", "3-005d"),
548 REGULATOR_SUPPLY("vdd", "3-005d"),
549};
550
d396be47
DL		 551static void __init cm_t35_init_camera(void)
552{
e68084c6
LP		 553 struct clk *clk;
554
555 clk = clk_register_fixed_rate(NULL, "mt9t001-clkin", NULL, CLK_IS_ROOT,
556 48000000);
557 clk_register_clkdev(clk, NULL, "3-005d");
558
559 regulator_register_fixed(2, cm_t35_camera_supplies,
560 ARRAY_SIZE(cm_t35_camera_supplies));
561
d396be47
DL		 562 if (omap3_init_camera(&cm_t35_isp_pdata) < 0)
563 pr_warn("CM-T3x: Failed registering camera device!\n");
564}
565
566#else
567static inline void cm_t35_init_camera(void) {}
568#endif /* CONFIG_VIDEO_OMAP3 */
569
2886d128
MR		 570static void __init cm_t35_init_i2c(void)
571{
b252b0ef 572 omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
19ce6439
IG		 573 TWL_COMMON_REGULATOR_VDAC |
574 TWL_COMMON_PDATA_AUDIO);
b252b0ef 575
fbd8071c 576 omap3_pmic_init("tps65930", &cm_t35_twldata);
d396be47
DL		 577
578 omap_register_i2c_bus(3, 400, NULL, 0);
2886d128
MR		 579}
580
c7ecea24 581#ifdef CONFIG_OMAP_MUX
ca5742bd 582static struct omap_board_mux board_mux[] __initdata = {
edc961a2
MR		 583 /* nCS and IRQ for CM-T35 ethernet */
584 OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
585 OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
586
587 /* nCS and IRQ for SB-T35 ethernet */
588 OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
589 OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
590
591 /* PENDOWN GPIO */
592 OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
593
594 /* mUSB */
595 OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
596 OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
597 OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
598 OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
599 OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
600 OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
601 OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
602 OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
603 OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
604 OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
605 OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
606 OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
607
608 /* MMC 2 */
609 OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
610 OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
611 OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
612 OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
613
614 /* McSPI 1 */
615 OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
616 OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
617 OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
618 OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
619
620 /* McSPI 4 */
621 OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
622 OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
623 OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
624 OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
625
626 /* McBSP 2 */
627 OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
628 OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
629 OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
630 OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
631
632 /* serial ports */
633 OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
634 OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
635 OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
636 OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
637
c3146974 638 /* common DSS */
edc961a2
MR		 639 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
640 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
641 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
642 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
edc961a2
MR		 643 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
644 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
645 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
646 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
647 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
648 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
649 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
650 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
651 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
652 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
653 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
654 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
edc961a2 655
d396be47
DL		 656 /* Camera */
657 OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
658 OMAP3_MUX(CAM_VS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
659 OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
660 OMAP3_MUX(CAM_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
661 OMAP3_MUX(CAM_FLD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
662 OMAP3_MUX(CAM_D0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
663 OMAP3_MUX(CAM_D1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
664 OMAP3_MUX(CAM_D2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
665 OMAP3_MUX(CAM_D3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
666 OMAP3_MUX(CAM_D4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
667 OMAP3_MUX(CAM_D5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
668 OMAP3_MUX(CAM_D6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
669 OMAP3_MUX(CAM_D7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
670 OMAP3_MUX(CAM_D8, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
671 OMAP3_MUX(CAM_D9, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
672 OMAP3_MUX(CAM_STROBE, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
673
674 OMAP3_MUX(CAM_D10, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
675 OMAP3_MUX(CAM_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
676
7f049ad1
MR		 677 /* display controls */
678 OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
679 OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
680 OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
681
edc961a2
MR		 682 /* TPS IRQ */
683 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
684 OMAP_PIN_INPUT_PULLUP),
685
ca5742bd
TL		 686 { .reg_offset = OMAP_MUX_TERMINATOR },
687};
c3146974
IG		 688
689static void __init cm_t3x_common_dss_mux_init(int mux_mode)
690{
691 omap_mux_init_signal("dss_data18", mux_mode);
692 omap_mux_init_signal("dss_data19", mux_mode);
693 omap_mux_init_signal("dss_data20", mux_mode);
694 omap_mux_init_signal("dss_data21", mux_mode);
695 omap_mux_init_signal("dss_data22", mux_mode);
696 omap_mux_init_signal("dss_data23", mux_mode);
697}
698
699static void __init cm_t35_init_mux(void)
700{
b2404f42
IG		 701 int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
702
703 omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
704 omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
705 omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
706 omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
707 omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
708 omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
709 cm_t3x_common_dss_mux_init(mux_mode);
c3146974
IG		 710}
711
712static void __init cm_t3730_init_mux(void)
713{
b2404f42
IG		 714 int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
715
716 omap_mux_init_signal("sys_boot0", mux_mode);
717 omap_mux_init_signal("sys_boot1", mux_mode);
718 omap_mux_init_signal("sys_boot3", mux_mode);
719 omap_mux_init_signal("sys_boot4", mux_mode);
720 omap_mux_init_signal("sys_boot5", mux_mode);
721 omap_mux_init_signal("sys_boot6", mux_mode);
722 cm_t3x_common_dss_mux_init(mux_mode);
c3146974
IG		 723}
724#else
725static inline void cm_t35_init_mux(void) {}
726static inline void cm_t3730_init_mux(void) {}
c7ecea24 727#endif
ca5742bd 728
c3146974 729static void __init cm_t3x_common_init(void)
2886d128 730{
ca5742bd 731 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
2886d128 732 omap_serial_init();
a4ca9dbe
TL		 733 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
734 mt46h32m32lf6_sdrc_params);
3b972bf0 735 omap_hsmmc_init(mmc);
2886d128 736 cm_t35_init_i2c();
96974a24 737 omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
2886d128
MR		 738 cm_t35_init_ethernet();
739 cm_t35_init_led();
7f049ad1 740 cm_t35_init_display();
40234bf7 741 omap_twl4030_audio_init("cm-t3x", NULL);
2886d128 742
51482be9 743 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
9e18630b 744 usb_musb_init(NULL);
039401f3 745 cm_t35_init_usbh();
d396be47 746 cm_t35_init_camera();
2886d128
MR		 747}
748
c3146974
IG		 749static void __init cm_t35_init(void)
750{
751 cm_t3x_common_init();
752 cm_t35_init_mux();
753 cm_t35_init_nand();
754}
755
756static void __init cm_t3730_init(void)
757{
758 cm_t3x_common_init();
759 cm_t3730_init_mux();
760}
761
2886d128 762MACHINE_START(CM_T35, "Compulab CM-T35")
5e52b435 763 .atag_offset = 0x100,
71ee7dad 764 .reserve = omap_reserve,
3dc3bad6 765 .map_io = omap3_map_io,
8f5b5a41 766 .init_early = omap35xx_init_early,
741e3a89 767 .init_irq = omap3_init_irq,
2886d128 768 .init_machine = cm_t35_init,
bbd707ac 769 .init_late = omap35xx_init_late,
6bb27d73 770 .init_time = omap3_sync32k_timer_init,
187e3e06 771 .restart = omap3xxx_restart,
2886d128 772MACHINE_END
c3146974
IG		 773
774MACHINE_START(CM_T3730, "Compulab CM-T3730")
187e3e06
PW		 775 .atag_offset = 0x100,
776 .reserve = omap_reserve,
777 .map_io = omap3_map_io,
778 .init_early = omap3630_init_early,
779 .init_irq = omap3_init_irq,
187e3e06 780 .init_machine = cm_t3730_init,
bbd707ac 781 .init_late = omap3630_init_late,
6bb27d73 782 .init_time = omap3_sync32k_timer_init,
187e3e06 783 .restart = omap3xxx_restart,
c3146974 784MACHINE_END
Linux kernel - Deliverables
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