Commit | Line | Data |
---|---|---|
2886d128 | 1 | /* |
c3146974 | 2 | * CompuLab CM-T35/CM-T3730 modules support |
2886d128 | 3 | * |
d12c2e28 IG |
4 | * Copyright (C) 2009-2011 CompuLab, Ltd. |
5 | * Authors: Mike Rapoport <mike@compulab.co.il> | |
6 | * Igor Grinberg <grinberg@compulab.co.il> | |
2886d128 MR |
7 | * |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
2886d128 MR |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/input.h> | |
23 | #include <linux/input/matrix_keypad.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/gpio.h> | |
4b25408f | 26 | #include <linux/platform_data/gpio-omap.h> |
2886d128 MR |
27 | |
28 | #include <linux/i2c/at24.h> | |
ebeb53e1 | 29 | #include <linux/i2c/twl.h> |
5b3689f4 | 30 | #include <linux/regulator/fixed.h> |
2886d128 | 31 | #include <linux/regulator/machine.h> |
3a63833e | 32 | #include <linux/mmc/host.h> |
51482be9 | 33 | #include <linux/usb/phy.h> |
2886d128 | 34 | |
7f049ad1 MR |
35 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/tdo24m.h> | |
37 | ||
2886d128 MR |
38 | #include <asm/mach-types.h> |
39 | #include <asm/mach/arch.h> | |
40 | #include <asm/mach/map.h> | |
41 | ||
2203747c | 42 | #include <linux/platform_data/mtd-nand-omap2.h> |
a0b38cc4 | 43 | #include <video/omapdss.h> |
f8ae2f08 | 44 | #include <video/omap-panel-generic-dpi.h> |
dac8eb5f | 45 | #include <video/omap-panel-tfp410.h> |
2203747c | 46 | #include <linux/platform_data/spi-omap2-mcspi.h> |
2886d128 | 47 | |
6d02643d | 48 | #include "common.h" |
ca5742bd | 49 | #include "mux.h" |
2886d128 | 50 | #include "sdram-micron-mt46h32m32lf-6.h" |
d02a900b | 51 | #include "hsmmc.h" |
96974a24 | 52 | #include "common-board-devices.h" |
6d02643d | 53 | #include "gpmc.h" |
bc3668ea | 54 | #include "gpmc-nand.h" |
2886d128 | 55 | |
039401f3 IG |
56 | #define CM_T35_GPIO_PENDOWN 57 |
57 | #define SB_T35_USB_HUB_RESET_GPIO 167 | |
2886d128 MR |
58 | |
59 | #define CM_T35_SMSC911X_CS 5 | |
60 | #define CM_T35_SMSC911X_GPIO 163 | |
61 | #define SB_T35_SMSC911X_CS 4 | |
62 | #define SB_T35_SMSC911X_GPIO 65 | |
63 | ||
2886d128 MR |
64 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
65 | #include <linux/smsc911x.h> | |
ac839b3c | 66 | #include "gpmc-smsc911x.h" |
2886d128 | 67 | |
21b42731 | 68 | static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = { |
2886d128 | 69 | .id = 0, |
21b42731 MR |
70 | .cs = CM_T35_SMSC911X_CS, |
71 | .gpio_irq = CM_T35_SMSC911X_GPIO, | |
72 | .gpio_reset = -EINVAL, | |
73 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | |
2886d128 MR |
74 | }; |
75 | ||
21b42731 | 76 | static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = { |
2886d128 | 77 | .id = 1, |
21b42731 MR |
78 | .cs = SB_T35_SMSC911X_CS, |
79 | .gpio_irq = SB_T35_SMSC911X_GPIO, | |
80 | .gpio_reset = -EINVAL, | |
81 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | |
2886d128 MR |
82 | }; |
83 | ||
5b3689f4 RD |
84 | static struct regulator_consumer_supply cm_t35_smsc911x_supplies[] = { |
85 | REGULATOR_SUPPLY("vddvario", "smsc911x.0"), | |
86 | REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), | |
87 | }; | |
88 | ||
89 | static struct regulator_consumer_supply sb_t35_smsc911x_supplies[] = { | |
90 | REGULATOR_SUPPLY("vddvario", "smsc911x.1"), | |
91 | REGULATOR_SUPPLY("vdd33a", "smsc911x.1"), | |
92 | }; | |
93 | ||
2886d128 MR |
94 | static void __init cm_t35_init_ethernet(void) |
95 | { | |
5b3689f4 RD |
96 | regulator_register_fixed(0, cm_t35_smsc911x_supplies, |
97 | ARRAY_SIZE(cm_t35_smsc911x_supplies)); | |
98 | regulator_register_fixed(1, sb_t35_smsc911x_supplies, | |
99 | ARRAY_SIZE(sb_t35_smsc911x_supplies)); | |
100 | ||
21b42731 MR |
101 | gpmc_smsc911x_init(&cm_t35_smsc911x_cfg); |
102 | gpmc_smsc911x_init(&sb_t35_smsc911x_cfg); | |
2886d128 MR |
103 | } |
104 | #else | |
105 | static inline void __init cm_t35_init_ethernet(void) { return; } | |
106 | #endif | |
107 | ||
108 | #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) | |
109 | #include <linux/leds.h> | |
110 | ||
111 | static struct gpio_led cm_t35_leds[] = { | |
112 | [0] = { | |
113 | .gpio = 186, | |
114 | .name = "cm-t35:green", | |
115 | .default_trigger = "heartbeat", | |
116 | .active_low = 0, | |
117 | }, | |
118 | }; | |
119 | ||
120 | static struct gpio_led_platform_data cm_t35_led_pdata = { | |
121 | .num_leds = ARRAY_SIZE(cm_t35_leds), | |
122 | .leds = cm_t35_leds, | |
123 | }; | |
124 | ||
125 | static struct platform_device cm_t35_led_device = { | |
126 | .name = "leds-gpio", | |
127 | .id = -1, | |
128 | .dev = { | |
129 | .platform_data = &cm_t35_led_pdata, | |
130 | }, | |
131 | }; | |
132 | ||
133 | static void __init cm_t35_init_led(void) | |
134 | { | |
135 | platform_device_register(&cm_t35_led_device); | |
136 | } | |
137 | #else | |
138 | static inline void cm_t35_init_led(void) {} | |
139 | #endif | |
140 | ||
141 | #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) | |
142 | #include <linux/mtd/mtd.h> | |
143 | #include <linux/mtd/nand.h> | |
144 | #include <linux/mtd/partitions.h> | |
145 | ||
146 | static struct mtd_partition cm_t35_nand_partitions[] = { | |
147 | { | |
148 | .name = "xloader", | |
149 | .offset = 0, /* Offset = 0x00000 */ | |
150 | .size = 4 * NAND_BLOCK_SIZE, | |
151 | .mask_flags = MTD_WRITEABLE | |
152 | }, | |
153 | { | |
154 | .name = "uboot", | |
155 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | |
156 | .size = 15 * NAND_BLOCK_SIZE, | |
157 | }, | |
158 | { | |
159 | .name = "uboot environment", | |
160 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ | |
161 | .size = 2 * NAND_BLOCK_SIZE, | |
162 | }, | |
163 | { | |
164 | .name = "linux", | |
d12c2e28 | 165 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */ |
2886d128 MR |
166 | .size = 32 * NAND_BLOCK_SIZE, |
167 | }, | |
168 | { | |
169 | .name = "rootfs", | |
d12c2e28 | 170 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */ |
2886d128 MR |
171 | .size = MTDPART_SIZ_FULL, |
172 | }, | |
173 | }; | |
174 | ||
175 | static struct omap_nand_platform_data cm_t35_nand_data = { | |
176 | .parts = cm_t35_nand_partitions, | |
177 | .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), | |
2886d128 | 178 | .cs = 0, |
2886d128 MR |
179 | }; |
180 | ||
2886d128 MR |
181 | static void __init cm_t35_init_nand(void) |
182 | { | |
bc3668ea | 183 | if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0) |
2886d128 MR |
184 | pr_err("CM-T35: Unable to register NAND device\n"); |
185 | } | |
186 | #else | |
187 | static inline void cm_t35_init_nand(void) {} | |
188 | #endif | |
189 | ||
7f049ad1 MR |
190 | #define CM_T35_LCD_EN_GPIO 157 |
191 | #define CM_T35_LCD_BL_GPIO 58 | |
192 | #define CM_T35_DVI_EN_GPIO 54 | |
193 | ||
7f049ad1 MR |
194 | static int lcd_enabled; |
195 | static int dvi_enabled; | |
196 | ||
197 | static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev) | |
198 | { | |
199 | if (dvi_enabled) { | |
200 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | |
201 | return -EINVAL; | |
202 | } | |
203 | ||
bc593f5d IG |
204 | gpio_set_value(CM_T35_LCD_EN_GPIO, 1); |
205 | gpio_set_value(CM_T35_LCD_BL_GPIO, 1); | |
7f049ad1 MR |
206 | |
207 | lcd_enabled = 1; | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) | |
213 | { | |
214 | lcd_enabled = 0; | |
215 | ||
bc593f5d IG |
216 | gpio_set_value(CM_T35_LCD_BL_GPIO, 0); |
217 | gpio_set_value(CM_T35_LCD_EN_GPIO, 0); | |
7f049ad1 MR |
218 | } |
219 | ||
7f049ad1 MR |
220 | static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) |
221 | { | |
222 | return 0; | |
223 | } | |
224 | ||
225 | static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev) | |
226 | { | |
227 | } | |
228 | ||
89747c91 BW |
229 | static struct panel_generic_dpi_data lcd_panel = { |
230 | .name = "toppoly_tdo35s", | |
231 | .platform_enable = cm_t35_panel_enable_lcd, | |
232 | .platform_disable = cm_t35_panel_disable_lcd, | |
233 | }; | |
234 | ||
7f049ad1 MR |
235 | static struct omap_dss_device cm_t35_lcd_device = { |
236 | .name = "lcd", | |
7f049ad1 | 237 | .type = OMAP_DISPLAY_TYPE_DPI, |
89747c91 BW |
238 | .driver_name = "generic_dpi_panel", |
239 | .data = &lcd_panel, | |
7f049ad1 | 240 | .phy.dpi.data_lines = 18, |
89747c91 BW |
241 | }; |
242 | ||
2e6f2ee7 | 243 | static struct tfp410_platform_data dvi_panel = { |
e813a55e | 244 | .power_down_gpio = CM_T35_DVI_EN_GPIO, |
ca2e16fa | 245 | .i2c_bus_num = -1, |
7f049ad1 MR |
246 | }; |
247 | ||
248 | static struct omap_dss_device cm_t35_dvi_device = { | |
249 | .name = "dvi", | |
7f049ad1 | 250 | .type = OMAP_DISPLAY_TYPE_DPI, |
2e6f2ee7 | 251 | .driver_name = "tfp410", |
89747c91 | 252 | .data = &dvi_panel, |
7f049ad1 | 253 | .phy.dpi.data_lines = 24, |
7f049ad1 MR |
254 | }; |
255 | ||
256 | static struct omap_dss_device cm_t35_tv_device = { | |
257 | .name = "tv", | |
258 | .driver_name = "venc", | |
259 | .type = OMAP_DISPLAY_TYPE_VENC, | |
260 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | |
261 | .platform_enable = cm_t35_panel_enable_tv, | |
262 | .platform_disable = cm_t35_panel_disable_tv, | |
263 | }; | |
264 | ||
265 | static struct omap_dss_device *cm_t35_dss_devices[] = { | |
266 | &cm_t35_lcd_device, | |
267 | &cm_t35_dvi_device, | |
268 | &cm_t35_tv_device, | |
269 | }; | |
270 | ||
271 | static struct omap_dss_board_info cm_t35_dss_data = { | |
272 | .num_devices = ARRAY_SIZE(cm_t35_dss_devices), | |
273 | .devices = cm_t35_dss_devices, | |
274 | .default_device = &cm_t35_dvi_device, | |
275 | }; | |
276 | ||
7f049ad1 MR |
277 | static struct omap2_mcspi_device_config tdo24m_mcspi_config = { |
278 | .turbo_mode = 0, | |
7f049ad1 MR |
279 | }; |
280 | ||
281 | static struct tdo24m_platform_data tdo24m_config = { | |
282 | .model = TDO35S, | |
283 | }; | |
284 | ||
285 | static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { | |
286 | { | |
287 | .modalias = "tdo24m", | |
288 | .bus_num = 4, | |
289 | .chip_select = 0, | |
290 | .max_speed_hz = 1000000, | |
291 | .controller_data = &tdo24m_mcspi_config, | |
292 | .platform_data = &tdo24m_config, | |
293 | }, | |
294 | }; | |
295 | ||
bc593f5d IG |
296 | static struct gpio cm_t35_dss_gpios[] __initdata = { |
297 | { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" }, | |
298 | { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" }, | |
bc593f5d IG |
299 | }; |
300 | ||
7f049ad1 MR |
301 | static void __init cm_t35_init_display(void) |
302 | { | |
303 | int err; | |
304 | ||
7f049ad1 MR |
305 | spi_register_board_info(cm_t35_lcd_spi_board_info, |
306 | ARRAY_SIZE(cm_t35_lcd_spi_board_info)); | |
307 | ||
bc593f5d IG |
308 | err = gpio_request_array(cm_t35_dss_gpios, |
309 | ARRAY_SIZE(cm_t35_dss_gpios)); | |
7f049ad1 | 310 | if (err) { |
bc593f5d IG |
311 | pr_err("CM-T35: failed to request DSS control GPIOs\n"); |
312 | return; | |
7f049ad1 MR |
313 | } |
314 | ||
bc593f5d IG |
315 | gpio_export(CM_T35_LCD_EN_GPIO, 0); |
316 | gpio_export(CM_T35_LCD_BL_GPIO, 0); | |
7f049ad1 MR |
317 | |
318 | msleep(50); | |
bc593f5d | 319 | gpio_set_value(CM_T35_LCD_EN_GPIO, 1); |
7f049ad1 | 320 | |
d5e13227 | 321 | err = omap_display_init(&cm_t35_dss_data); |
7f049ad1 MR |
322 | if (err) { |
323 | pr_err("CM-T35: failed to register DSS device\n"); | |
bc593f5d | 324 | gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios)); |
7f049ad1 | 325 | } |
7f049ad1 MR |
326 | } |
327 | ||
786b01a8 OD |
328 | static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = { |
329 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), | |
2886d128 MR |
330 | }; |
331 | ||
786b01a8 OD |
332 | static struct regulator_consumer_supply cm_t35_vsim_supply[] = { |
333 | REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), | |
2886d128 MR |
334 | }; |
335 | ||
b74f149c IG |
336 | static struct regulator_consumer_supply cm_t35_vio_supplies[] = { |
337 | REGULATOR_SUPPLY("vcc", "spi1.0"), | |
cd1c683c IG |
338 | REGULATOR_SUPPLY("vdds_dsi", "omapdss"), |
339 | REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"), | |
b74f149c IG |
340 | }; |
341 | ||
2886d128 MR |
342 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ |
343 | static struct regulator_init_data cm_t35_vmmc1 = { | |
344 | .constraints = { | |
345 | .min_uV = 1850000, | |
346 | .max_uV = 3150000, | |
347 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
348 | | REGULATOR_MODE_STANDBY, | |
349 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
350 | | REGULATOR_CHANGE_MODE | |
351 | | REGULATOR_CHANGE_STATUS, | |
352 | }, | |
786b01a8 OD |
353 | .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply), |
354 | .consumer_supplies = cm_t35_vmmc1_supply, | |
2886d128 MR |
355 | }; |
356 | ||
357 | /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ | |
358 | static struct regulator_init_data cm_t35_vsim = { | |
359 | .constraints = { | |
360 | .min_uV = 1800000, | |
361 | .max_uV = 3000000, | |
362 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
363 | | REGULATOR_MODE_STANDBY, | |
364 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
365 | | REGULATOR_CHANGE_MODE | |
366 | | REGULATOR_CHANGE_STATUS, | |
367 | }, | |
786b01a8 OD |
368 | .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply), |
369 | .consumer_supplies = cm_t35_vsim_supply, | |
2886d128 MR |
370 | }; |
371 | ||
b74f149c IG |
372 | static struct regulator_init_data cm_t35_vio = { |
373 | .constraints = { | |
374 | .min_uV = 1800000, | |
375 | .max_uV = 1800000, | |
376 | .apply_uV = true, | |
377 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
378 | | REGULATOR_MODE_STANDBY, | |
379 | .valid_ops_mask = REGULATOR_CHANGE_MODE, | |
380 | }, | |
381 | .num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies), | |
382 | .consumer_supplies = cm_t35_vio_supplies, | |
383 | }; | |
384 | ||
bead4375 | 385 | static uint32_t cm_t35_keymap[] = { |
2886d128 MR |
386 | KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), |
387 | KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), | |
388 | KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), | |
389 | }; | |
390 | ||
391 | static struct matrix_keymap_data cm_t35_keymap_data = { | |
392 | .keymap = cm_t35_keymap, | |
393 | .keymap_size = ARRAY_SIZE(cm_t35_keymap), | |
394 | }; | |
395 | ||
396 | static struct twl4030_keypad_data cm_t35_kp_data = { | |
397 | .keymap_data = &cm_t35_keymap_data, | |
398 | .rows = 3, | |
399 | .cols = 3, | |
400 | .rep = 1, | |
401 | }; | |
402 | ||
68ff0423 | 403 | static struct omap2_hsmmc_info mmc[] = { |
2886d128 MR |
404 | { |
405 | .mmc = 1, | |
3a63833e | 406 | .caps = MMC_CAP_4_BIT_DATA, |
2886d128 MR |
407 | .gpio_cd = -EINVAL, |
408 | .gpio_wp = -EINVAL, | |
3b972bf0 | 409 | .deferred = true, |
2886d128 MR |
410 | }, |
411 | { | |
412 | .mmc = 2, | |
3a63833e | 413 | .caps = MMC_CAP_4_BIT_DATA, |
2886d128 MR |
414 | .transceiver = 1, |
415 | .gpio_cd = -EINVAL, | |
416 | .gpio_wp = -EINVAL, | |
417 | .ocr_mask = 0x00100000, /* 3.3V */ | |
418 | }, | |
419 | {} /* Terminator */ | |
420 | }; | |
421 | ||
42973159 | 422 | static struct usbhs_omap_platform_data usbhs_bdata __initdata = { |
181b250c KM |
423 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, |
424 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | |
425 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | |
2886d128 MR |
426 | |
427 | .phy_reset = true, | |
1a6b5923 BW |
428 | .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, |
429 | .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7, | |
2886d128 MR |
430 | .reset_gpio_port[2] = -EINVAL |
431 | }; | |
432 | ||
36863964 | 433 | static void __init cm_t35_init_usbh(void) |
039401f3 IG |
434 | { |
435 | int err; | |
436 | ||
437 | err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO, | |
438 | GPIOF_OUT_INIT_LOW, "usb hub rst"); | |
439 | if (err) { | |
440 | pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err); | |
441 | } else { | |
442 | udelay(10); | |
443 | gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1); | |
444 | msleep(1); | |
445 | } | |
446 | ||
447 | usbhs_init(&usbhs_bdata); | |
448 | } | |
449 | ||
2886d128 MR |
450 | static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, |
451 | unsigned ngpio) | |
452 | { | |
453 | int wlan_rst = gpio + 2; | |
454 | ||
bc593f5d | 455 | if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) { |
2886d128 | 456 | gpio_export(wlan_rst, 0); |
2886d128 | 457 | udelay(10); |
be741de1 | 458 | gpio_set_value_cansleep(wlan_rst, 0); |
2886d128 | 459 | udelay(10); |
be741de1 | 460 | gpio_set_value_cansleep(wlan_rst, 1); |
2886d128 MR |
461 | } else { |
462 | pr_err("CM-T35: could not obtain gpio for WiFi reset\n"); | |
463 | } | |
464 | ||
465 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | |
466 | mmc[0].gpio_cd = gpio + 0; | |
3b972bf0 | 467 | omap_hsmmc_late_init(mmc); |
2886d128 | 468 | |
2886d128 MR |
469 | return 0; |
470 | } | |
471 | ||
472 | static struct twl4030_gpio_platform_data cm_t35_gpio_data = { | |
2886d128 MR |
473 | .setup = cm_t35_twl_gpio_setup, |
474 | }; | |
475 | ||
d61676b8 IG |
476 | static struct twl4030_power_data cm_t35_power_data = { |
477 | .use_poweroff = true, | |
478 | }; | |
479 | ||
2886d128 | 480 | static struct twl4030_platform_data cm_t35_twldata = { |
2886d128 MR |
481 | /* platform_data for children goes here */ |
482 | .keypad = &cm_t35_kp_data, | |
2886d128 MR |
483 | .gpio = &cm_t35_gpio_data, |
484 | .vmmc1 = &cm_t35_vmmc1, | |
485 | .vsim = &cm_t35_vsim, | |
b74f149c | 486 | .vio = &cm_t35_vio, |
d61676b8 | 487 | .power = &cm_t35_power_data, |
2886d128 MR |
488 | }; |
489 | ||
d396be47 DL |
490 | #if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) |
491 | #include <media/omap3isp.h> | |
492 | #include "devices.h" | |
493 | ||
494 | static struct i2c_board_info cm_t35_isp_i2c_boardinfo[] = { | |
495 | { | |
496 | I2C_BOARD_INFO("mt9t001", 0x5d), | |
497 | }, | |
3d6bbca9 DL |
498 | { |
499 | I2C_BOARD_INFO("tvp5150", 0x5c), | |
500 | }, | |
d396be47 DL |
501 | }; |
502 | ||
503 | static struct isp_subdev_i2c_board_info cm_t35_isp_primary_subdevs[] = { | |
504 | { | |
505 | .board_info = &cm_t35_isp_i2c_boardinfo[0], | |
506 | .i2c_adapter_id = 3, | |
507 | }, | |
508 | { NULL, 0, }, | |
509 | }; | |
510 | ||
3d6bbca9 DL |
511 | static struct isp_subdev_i2c_board_info cm_t35_isp_secondary_subdevs[] = { |
512 | { | |
513 | .board_info = &cm_t35_isp_i2c_boardinfo[1], | |
514 | .i2c_adapter_id = 3, | |
515 | }, | |
516 | { NULL, 0, }, | |
517 | }; | |
518 | ||
d396be47 DL |
519 | static struct isp_v4l2_subdevs_group cm_t35_isp_subdevs[] = { |
520 | { | |
521 | .subdevs = cm_t35_isp_primary_subdevs, | |
522 | .interface = ISP_INTERFACE_PARALLEL, | |
523 | .bus = { | |
524 | .parallel = { | |
525 | .clk_pol = 1, | |
526 | }, | |
527 | }, | |
528 | }, | |
3d6bbca9 DL |
529 | { |
530 | .subdevs = cm_t35_isp_secondary_subdevs, | |
531 | .interface = ISP_INTERFACE_PARALLEL, | |
532 | .bus = { | |
533 | .parallel = { | |
534 | .clk_pol = 0, | |
535 | }, | |
536 | }, | |
537 | }, | |
d396be47 DL |
538 | { NULL, 0, }, |
539 | }; | |
540 | ||
541 | static struct isp_platform_data cm_t35_isp_pdata = { | |
542 | .subdevs = cm_t35_isp_subdevs, | |
543 | }; | |
544 | ||
545 | static void __init cm_t35_init_camera(void) | |
546 | { | |
547 | if (omap3_init_camera(&cm_t35_isp_pdata) < 0) | |
548 | pr_warn("CM-T3x: Failed registering camera device!\n"); | |
549 | } | |
550 | ||
551 | #else | |
552 | static inline void cm_t35_init_camera(void) {} | |
553 | #endif /* CONFIG_VIDEO_OMAP3 */ | |
554 | ||
2886d128 MR |
555 | static void __init cm_t35_init_i2c(void) |
556 | { | |
b252b0ef | 557 | omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB, |
19ce6439 IG |
558 | TWL_COMMON_REGULATOR_VDAC | |
559 | TWL_COMMON_PDATA_AUDIO); | |
b252b0ef | 560 | |
fbd8071c | 561 | omap3_pmic_init("tps65930", &cm_t35_twldata); |
d396be47 DL |
562 | |
563 | omap_register_i2c_bus(3, 400, NULL, 0); | |
2886d128 MR |
564 | } |
565 | ||
c7ecea24 | 566 | #ifdef CONFIG_OMAP_MUX |
ca5742bd | 567 | static struct omap_board_mux board_mux[] __initdata = { |
edc961a2 MR |
568 | /* nCS and IRQ for CM-T35 ethernet */ |
569 | OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), | |
570 | OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
571 | ||
572 | /* nCS and IRQ for SB-T35 ethernet */ | |
573 | OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0), | |
574 | OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
575 | ||
576 | /* PENDOWN GPIO */ | |
577 | OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), | |
578 | ||
579 | /* mUSB */ | |
580 | OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
581 | OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
582 | OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
583 | OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
584 | OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
585 | OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
586 | OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
587 | OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
588 | OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
589 | OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
590 | OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
591 | OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
592 | ||
593 | /* MMC 2 */ | |
594 | OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
595 | OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
596 | OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
597 | OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
598 | ||
599 | /* McSPI 1 */ | |
600 | OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
601 | OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
602 | OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
603 | OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | |
604 | ||
605 | /* McSPI 4 */ | |
606 | OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
607 | OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
608 | OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
609 | OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP), | |
610 | ||
611 | /* McBSP 2 */ | |
612 | OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
613 | OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
614 | OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
615 | OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
616 | ||
617 | /* serial ports */ | |
618 | OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
619 | OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
620 | OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
621 | OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
622 | ||
c3146974 | 623 | /* common DSS */ |
edc961a2 MR |
624 | OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), |
625 | OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
626 | OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
627 | OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
edc961a2 MR |
628 | OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), |
629 | OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
630 | OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
631 | OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
632 | OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
633 | OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
634 | OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
635 | OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
636 | OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
637 | OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
638 | OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
639 | OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
edc961a2 | 640 | |
d396be47 DL |
641 | /* Camera */ |
642 | OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
643 | OMAP3_MUX(CAM_VS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
644 | OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
645 | OMAP3_MUX(CAM_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
646 | OMAP3_MUX(CAM_FLD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
647 | OMAP3_MUX(CAM_D0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
648 | OMAP3_MUX(CAM_D1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
649 | OMAP3_MUX(CAM_D2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
650 | OMAP3_MUX(CAM_D3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
651 | OMAP3_MUX(CAM_D4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
652 | OMAP3_MUX(CAM_D5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
653 | OMAP3_MUX(CAM_D6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
654 | OMAP3_MUX(CAM_D7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
655 | OMAP3_MUX(CAM_D8, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | |
656 | OMAP3_MUX(CAM_D9, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | |
657 | OMAP3_MUX(CAM_STROBE, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
658 | ||
659 | OMAP3_MUX(CAM_D10, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN), | |
660 | OMAP3_MUX(CAM_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN), | |
661 | ||
7f049ad1 MR |
662 | /* display controls */ |
663 | OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
664 | OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
665 | OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
666 | ||
edc961a2 MR |
667 | /* TPS IRQ */ |
668 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ | |
669 | OMAP_PIN_INPUT_PULLUP), | |
670 | ||
ca5742bd TL |
671 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
672 | }; | |
c3146974 IG |
673 | |
674 | static void __init cm_t3x_common_dss_mux_init(int mux_mode) | |
675 | { | |
676 | omap_mux_init_signal("dss_data18", mux_mode); | |
677 | omap_mux_init_signal("dss_data19", mux_mode); | |
678 | omap_mux_init_signal("dss_data20", mux_mode); | |
679 | omap_mux_init_signal("dss_data21", mux_mode); | |
680 | omap_mux_init_signal("dss_data22", mux_mode); | |
681 | omap_mux_init_signal("dss_data23", mux_mode); | |
682 | } | |
683 | ||
684 | static void __init cm_t35_init_mux(void) | |
685 | { | |
b2404f42 IG |
686 | int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT; |
687 | ||
688 | omap_mux_init_signal("dss_data0.dss_data0", mux_mode); | |
689 | omap_mux_init_signal("dss_data1.dss_data1", mux_mode); | |
690 | omap_mux_init_signal("dss_data2.dss_data2", mux_mode); | |
691 | omap_mux_init_signal("dss_data3.dss_data3", mux_mode); | |
692 | omap_mux_init_signal("dss_data4.dss_data4", mux_mode); | |
693 | omap_mux_init_signal("dss_data5.dss_data5", mux_mode); | |
694 | cm_t3x_common_dss_mux_init(mux_mode); | |
c3146974 IG |
695 | } |
696 | ||
697 | static void __init cm_t3730_init_mux(void) | |
698 | { | |
b2404f42 IG |
699 | int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT; |
700 | ||
701 | omap_mux_init_signal("sys_boot0", mux_mode); | |
702 | omap_mux_init_signal("sys_boot1", mux_mode); | |
703 | omap_mux_init_signal("sys_boot3", mux_mode); | |
704 | omap_mux_init_signal("sys_boot4", mux_mode); | |
705 | omap_mux_init_signal("sys_boot5", mux_mode); | |
706 | omap_mux_init_signal("sys_boot6", mux_mode); | |
707 | cm_t3x_common_dss_mux_init(mux_mode); | |
c3146974 IG |
708 | } |
709 | #else | |
710 | static inline void cm_t35_init_mux(void) {} | |
711 | static inline void cm_t3730_init_mux(void) {} | |
c7ecea24 | 712 | #endif |
ca5742bd | 713 | |
c3146974 | 714 | static void __init cm_t3x_common_init(void) |
2886d128 | 715 | { |
ca5742bd | 716 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); |
2886d128 | 717 | omap_serial_init(); |
a4ca9dbe TL |
718 | omap_sdrc_init(mt46h32m32lf6_sdrc_params, |
719 | mt46h32m32lf6_sdrc_params); | |
3b972bf0 | 720 | omap_hsmmc_init(mmc); |
2886d128 | 721 | cm_t35_init_i2c(); |
96974a24 | 722 | omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL); |
2886d128 MR |
723 | cm_t35_init_ethernet(); |
724 | cm_t35_init_led(); | |
7f049ad1 | 725 | cm_t35_init_display(); |
40234bf7 | 726 | omap_twl4030_audio_init("cm-t3x", NULL); |
2886d128 | 727 | |
51482be9 | 728 | usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb"); |
9e18630b | 729 | usb_musb_init(NULL); |
039401f3 | 730 | cm_t35_init_usbh(); |
d396be47 | 731 | cm_t35_init_camera(); |
2886d128 MR |
732 | } |
733 | ||
c3146974 IG |
734 | static void __init cm_t35_init(void) |
735 | { | |
736 | cm_t3x_common_init(); | |
737 | cm_t35_init_mux(); | |
738 | cm_t35_init_nand(); | |
739 | } | |
740 | ||
741 | static void __init cm_t3730_init(void) | |
742 | { | |
743 | cm_t3x_common_init(); | |
744 | cm_t3730_init_mux(); | |
745 | } | |
746 | ||
2886d128 | 747 | MACHINE_START(CM_T35, "Compulab CM-T35") |
5e52b435 | 748 | .atag_offset = 0x100, |
71ee7dad | 749 | .reserve = omap_reserve, |
3dc3bad6 | 750 | .map_io = omap3_map_io, |
8f5b5a41 | 751 | .init_early = omap35xx_init_early, |
741e3a89 | 752 | .init_irq = omap3_init_irq, |
6b2f55d7 | 753 | .handle_irq = omap3_intc_handle_irq, |
2886d128 | 754 | .init_machine = cm_t35_init, |
bbd707ac | 755 | .init_late = omap35xx_init_late, |
6bb27d73 | 756 | .init_time = omap3_sync32k_timer_init, |
187e3e06 | 757 | .restart = omap3xxx_restart, |
2886d128 | 758 | MACHINE_END |
c3146974 IG |
759 | |
760 | MACHINE_START(CM_T3730, "Compulab CM-T3730") | |
187e3e06 PW |
761 | .atag_offset = 0x100, |
762 | .reserve = omap_reserve, | |
763 | .map_io = omap3_map_io, | |
764 | .init_early = omap3630_init_early, | |
765 | .init_irq = omap3_init_irq, | |
6b2f55d7 | 766 | .handle_irq = omap3_intc_handle_irq, |
187e3e06 | 767 | .init_machine = cm_t3730_init, |
bbd707ac | 768 | .init_late = omap3630_init_late, |
6bb27d73 | 769 | .init_time = omap3_sync32k_timer_init, |
187e3e06 | 770 | .restart = omap3xxx_restart, |
c3146974 | 771 | MACHINE_END |