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2886d128 MR |
1 | /* |
2 | * board-cm-t35.c (CompuLab CM-T35 module) | |
3 | * | |
4 | * Copyright (C) 2009 CompuLab, Ltd. | |
5 | * Author: Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/input.h> | |
27 | #include <linux/input/matrix_keypad.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/gpio.h> | |
30 | ||
31 | #include <linux/i2c/at24.h> | |
ebeb53e1 | 32 | #include <linux/i2c/twl.h> |
2886d128 | 33 | #include <linux/regulator/machine.h> |
3a63833e | 34 | #include <linux/mmc/host.h> |
2886d128 | 35 | |
7f049ad1 MR |
36 | #include <linux/spi/spi.h> |
37 | #include <linux/spi/tdo24m.h> | |
38 | ||
2886d128 MR |
39 | #include <asm/mach-types.h> |
40 | #include <asm/mach/arch.h> | |
41 | #include <asm/mach/map.h> | |
42 | ||
43 | #include <plat/board.h> | |
44 | #include <plat/common.h> | |
2886d128 MR |
45 | #include <plat/nand.h> |
46 | #include <plat/gpmc.h> | |
47 | #include <plat/usb.h> | |
7f049ad1 | 48 | #include <plat/display.h> |
89747c91 | 49 | #include <plat/panel-generic-dpi.h> |
609c9ba2 | 50 | #include <plat/mcspi.h> |
2886d128 MR |
51 | |
52 | #include <mach/hardware.h> | |
53 | ||
ca5742bd | 54 | #include "mux.h" |
2886d128 | 55 | #include "sdram-micron-mt46h32m32lf-6.h" |
d02a900b | 56 | #include "hsmmc.h" |
96974a24 | 57 | #include "common-board-devices.h" |
2886d128 MR |
58 | |
59 | #define CM_T35_GPIO_PENDOWN 57 | |
60 | ||
61 | #define CM_T35_SMSC911X_CS 5 | |
62 | #define CM_T35_SMSC911X_GPIO 163 | |
63 | #define SB_T35_SMSC911X_CS 4 | |
64 | #define SB_T35_SMSC911X_GPIO 65 | |
65 | ||
66 | #define NAND_BLOCK_SIZE SZ_128K | |
2886d128 MR |
67 | |
68 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | |
69 | #include <linux/smsc911x.h> | |
21b42731 | 70 | #include <plat/gpmc-smsc911x.h> |
2886d128 | 71 | |
21b42731 | 72 | static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = { |
2886d128 | 73 | .id = 0, |
21b42731 MR |
74 | .cs = CM_T35_SMSC911X_CS, |
75 | .gpio_irq = CM_T35_SMSC911X_GPIO, | |
76 | .gpio_reset = -EINVAL, | |
77 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | |
2886d128 MR |
78 | }; |
79 | ||
21b42731 | 80 | static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = { |
2886d128 | 81 | .id = 1, |
21b42731 MR |
82 | .cs = SB_T35_SMSC911X_CS, |
83 | .gpio_irq = SB_T35_SMSC911X_GPIO, | |
84 | .gpio_reset = -EINVAL, | |
85 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | |
2886d128 MR |
86 | }; |
87 | ||
2886d128 MR |
88 | static void __init cm_t35_init_ethernet(void) |
89 | { | |
21b42731 MR |
90 | gpmc_smsc911x_init(&cm_t35_smsc911x_cfg); |
91 | gpmc_smsc911x_init(&sb_t35_smsc911x_cfg); | |
2886d128 MR |
92 | } |
93 | #else | |
94 | static inline void __init cm_t35_init_ethernet(void) { return; } | |
95 | #endif | |
96 | ||
97 | #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) | |
98 | #include <linux/leds.h> | |
99 | ||
100 | static struct gpio_led cm_t35_leds[] = { | |
101 | [0] = { | |
102 | .gpio = 186, | |
103 | .name = "cm-t35:green", | |
104 | .default_trigger = "heartbeat", | |
105 | .active_low = 0, | |
106 | }, | |
107 | }; | |
108 | ||
109 | static struct gpio_led_platform_data cm_t35_led_pdata = { | |
110 | .num_leds = ARRAY_SIZE(cm_t35_leds), | |
111 | .leds = cm_t35_leds, | |
112 | }; | |
113 | ||
114 | static struct platform_device cm_t35_led_device = { | |
115 | .name = "leds-gpio", | |
116 | .id = -1, | |
117 | .dev = { | |
118 | .platform_data = &cm_t35_led_pdata, | |
119 | }, | |
120 | }; | |
121 | ||
122 | static void __init cm_t35_init_led(void) | |
123 | { | |
124 | platform_device_register(&cm_t35_led_device); | |
125 | } | |
126 | #else | |
127 | static inline void cm_t35_init_led(void) {} | |
128 | #endif | |
129 | ||
130 | #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) | |
131 | #include <linux/mtd/mtd.h> | |
132 | #include <linux/mtd/nand.h> | |
133 | #include <linux/mtd/partitions.h> | |
134 | ||
135 | static struct mtd_partition cm_t35_nand_partitions[] = { | |
136 | { | |
137 | .name = "xloader", | |
138 | .offset = 0, /* Offset = 0x00000 */ | |
139 | .size = 4 * NAND_BLOCK_SIZE, | |
140 | .mask_flags = MTD_WRITEABLE | |
141 | }, | |
142 | { | |
143 | .name = "uboot", | |
144 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | |
145 | .size = 15 * NAND_BLOCK_SIZE, | |
146 | }, | |
147 | { | |
148 | .name = "uboot environment", | |
149 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ | |
150 | .size = 2 * NAND_BLOCK_SIZE, | |
151 | }, | |
152 | { | |
153 | .name = "linux", | |
154 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | |
155 | .size = 32 * NAND_BLOCK_SIZE, | |
156 | }, | |
157 | { | |
158 | .name = "rootfs", | |
159 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ | |
160 | .size = MTDPART_SIZ_FULL, | |
161 | }, | |
162 | }; | |
163 | ||
164 | static struct omap_nand_platform_data cm_t35_nand_data = { | |
165 | .parts = cm_t35_nand_partitions, | |
166 | .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), | |
167 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | |
168 | .cs = 0, | |
2886d128 MR |
169 | |
170 | }; | |
171 | ||
2886d128 MR |
172 | static void __init cm_t35_init_nand(void) |
173 | { | |
f450d867 | 174 | if (gpmc_nand_init(&cm_t35_nand_data) < 0) |
2886d128 MR |
175 | pr_err("CM-T35: Unable to register NAND device\n"); |
176 | } | |
177 | #else | |
178 | static inline void cm_t35_init_nand(void) {} | |
179 | #endif | |
180 | ||
7f049ad1 MR |
181 | #define CM_T35_LCD_EN_GPIO 157 |
182 | #define CM_T35_LCD_BL_GPIO 58 | |
183 | #define CM_T35_DVI_EN_GPIO 54 | |
184 | ||
185 | static int lcd_bl_gpio; | |
186 | static int lcd_en_gpio; | |
187 | static int dvi_en_gpio; | |
188 | ||
189 | static int lcd_enabled; | |
190 | static int dvi_enabled; | |
191 | ||
192 | static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev) | |
193 | { | |
194 | if (dvi_enabled) { | |
195 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | |
196 | return -EINVAL; | |
197 | } | |
198 | ||
199 | gpio_set_value(lcd_en_gpio, 1); | |
200 | gpio_set_value(lcd_bl_gpio, 1); | |
201 | ||
202 | lcd_enabled = 1; | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) | |
208 | { | |
209 | lcd_enabled = 0; | |
210 | ||
211 | gpio_set_value(lcd_bl_gpio, 0); | |
212 | gpio_set_value(lcd_en_gpio, 0); | |
213 | } | |
214 | ||
215 | static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) | |
216 | { | |
217 | if (lcd_enabled) { | |
218 | printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); | |
219 | return -EINVAL; | |
220 | } | |
221 | ||
222 | gpio_set_value(dvi_en_gpio, 0); | |
223 | dvi_enabled = 1; | |
224 | ||
225 | return 0; | |
226 | } | |
227 | ||
228 | static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev) | |
229 | { | |
230 | gpio_set_value(dvi_en_gpio, 1); | |
231 | dvi_enabled = 0; | |
232 | } | |
233 | ||
234 | static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) | |
235 | { | |
236 | return 0; | |
237 | } | |
238 | ||
239 | static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev) | |
240 | { | |
241 | } | |
242 | ||
89747c91 BW |
243 | static struct panel_generic_dpi_data lcd_panel = { |
244 | .name = "toppoly_tdo35s", | |
245 | .platform_enable = cm_t35_panel_enable_lcd, | |
246 | .platform_disable = cm_t35_panel_disable_lcd, | |
247 | }; | |
248 | ||
7f049ad1 MR |
249 | static struct omap_dss_device cm_t35_lcd_device = { |
250 | .name = "lcd", | |
7f049ad1 | 251 | .type = OMAP_DISPLAY_TYPE_DPI, |
89747c91 BW |
252 | .driver_name = "generic_dpi_panel", |
253 | .data = &lcd_panel, | |
7f049ad1 | 254 | .phy.dpi.data_lines = 18, |
89747c91 BW |
255 | }; |
256 | ||
257 | static struct panel_generic_dpi_data dvi_panel = { | |
258 | .name = "generic", | |
259 | .platform_enable = cm_t35_panel_enable_dvi, | |
260 | .platform_disable = cm_t35_panel_disable_dvi, | |
7f049ad1 MR |
261 | }; |
262 | ||
263 | static struct omap_dss_device cm_t35_dvi_device = { | |
264 | .name = "dvi", | |
7f049ad1 | 265 | .type = OMAP_DISPLAY_TYPE_DPI, |
89747c91 BW |
266 | .driver_name = "generic_dpi_panel", |
267 | .data = &dvi_panel, | |
7f049ad1 | 268 | .phy.dpi.data_lines = 24, |
7f049ad1 MR |
269 | }; |
270 | ||
271 | static struct omap_dss_device cm_t35_tv_device = { | |
272 | .name = "tv", | |
273 | .driver_name = "venc", | |
274 | .type = OMAP_DISPLAY_TYPE_VENC, | |
275 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | |
276 | .platform_enable = cm_t35_panel_enable_tv, | |
277 | .platform_disable = cm_t35_panel_disable_tv, | |
278 | }; | |
279 | ||
280 | static struct omap_dss_device *cm_t35_dss_devices[] = { | |
281 | &cm_t35_lcd_device, | |
282 | &cm_t35_dvi_device, | |
283 | &cm_t35_tv_device, | |
284 | }; | |
285 | ||
286 | static struct omap_dss_board_info cm_t35_dss_data = { | |
287 | .num_devices = ARRAY_SIZE(cm_t35_dss_devices), | |
288 | .devices = cm_t35_dss_devices, | |
289 | .default_device = &cm_t35_dvi_device, | |
290 | }; | |
291 | ||
7f049ad1 MR |
292 | static struct omap2_mcspi_device_config tdo24m_mcspi_config = { |
293 | .turbo_mode = 0, | |
294 | .single_channel = 1, /* 0: slave, 1: master */ | |
295 | }; | |
296 | ||
297 | static struct tdo24m_platform_data tdo24m_config = { | |
298 | .model = TDO35S, | |
299 | }; | |
300 | ||
301 | static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { | |
302 | { | |
303 | .modalias = "tdo24m", | |
304 | .bus_num = 4, | |
305 | .chip_select = 0, | |
306 | .max_speed_hz = 1000000, | |
307 | .controller_data = &tdo24m_mcspi_config, | |
308 | .platform_data = &tdo24m_config, | |
309 | }, | |
310 | }; | |
311 | ||
312 | static void __init cm_t35_init_display(void) | |
313 | { | |
314 | int err; | |
315 | ||
316 | lcd_en_gpio = CM_T35_LCD_EN_GPIO; | |
317 | lcd_bl_gpio = CM_T35_LCD_BL_GPIO; | |
318 | dvi_en_gpio = CM_T35_DVI_EN_GPIO; | |
319 | ||
320 | spi_register_board_info(cm_t35_lcd_spi_board_info, | |
321 | ARRAY_SIZE(cm_t35_lcd_spi_board_info)); | |
322 | ||
323 | err = gpio_request(lcd_en_gpio, "LCD RST"); | |
324 | if (err) { | |
325 | pr_err("CM-T35: failed to get LCD reset GPIO\n"); | |
326 | goto out; | |
327 | } | |
328 | ||
329 | err = gpio_request(lcd_bl_gpio, "LCD BL"); | |
330 | if (err) { | |
331 | pr_err("CM-T35: failed to get LCD backlight control GPIO\n"); | |
332 | goto err_lcd_bl; | |
333 | } | |
334 | ||
335 | err = gpio_request(dvi_en_gpio, "DVI EN"); | |
336 | if (err) { | |
337 | pr_err("CM-T35: failed to get DVI reset GPIO\n"); | |
338 | goto err_dvi_en; | |
339 | } | |
340 | ||
341 | gpio_export(lcd_en_gpio, 0); | |
342 | gpio_export(lcd_bl_gpio, 0); | |
343 | gpio_export(dvi_en_gpio, 0); | |
344 | gpio_direction_output(lcd_en_gpio, 0); | |
345 | gpio_direction_output(lcd_bl_gpio, 0); | |
346 | gpio_direction_output(dvi_en_gpio, 1); | |
347 | ||
348 | msleep(50); | |
349 | gpio_set_value(lcd_en_gpio, 1); | |
350 | ||
d5e13227 | 351 | err = omap_display_init(&cm_t35_dss_data); |
7f049ad1 MR |
352 | if (err) { |
353 | pr_err("CM-T35: failed to register DSS device\n"); | |
354 | goto err_dev_reg; | |
355 | } | |
356 | ||
357 | return; | |
358 | ||
359 | err_dev_reg: | |
360 | gpio_free(dvi_en_gpio); | |
361 | err_dvi_en: | |
362 | gpio_free(lcd_bl_gpio); | |
363 | err_lcd_bl: | |
364 | gpio_free(lcd_en_gpio); | |
365 | out: | |
366 | ||
367 | return; | |
368 | } | |
369 | ||
2886d128 MR |
370 | static struct regulator_consumer_supply cm_t35_vmmc1_supply = { |
371 | .supply = "vmmc", | |
372 | }; | |
373 | ||
374 | static struct regulator_consumer_supply cm_t35_vsim_supply = { | |
375 | .supply = "vmmc_aux", | |
376 | }; | |
377 | ||
1dde9732 | 378 | static struct regulator_consumer_supply cm_t35_vdac_supply = |
30ea50c9 | 379 | REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"); |
7f049ad1 | 380 | |
1dde9732 SG |
381 | static struct regulator_consumer_supply cm_t35_vdvi_supply = |
382 | REGULATOR_SUPPLY("vdvi", "omapdss"); | |
7f049ad1 | 383 | |
2886d128 MR |
384 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ |
385 | static struct regulator_init_data cm_t35_vmmc1 = { | |
386 | .constraints = { | |
387 | .min_uV = 1850000, | |
388 | .max_uV = 3150000, | |
389 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
390 | | REGULATOR_MODE_STANDBY, | |
391 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
392 | | REGULATOR_CHANGE_MODE | |
393 | | REGULATOR_CHANGE_STATUS, | |
394 | }, | |
395 | .num_consumer_supplies = 1, | |
396 | .consumer_supplies = &cm_t35_vmmc1_supply, | |
397 | }; | |
398 | ||
399 | /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ | |
400 | static struct regulator_init_data cm_t35_vsim = { | |
401 | .constraints = { | |
402 | .min_uV = 1800000, | |
403 | .max_uV = 3000000, | |
404 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
405 | | REGULATOR_MODE_STANDBY, | |
406 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
407 | | REGULATOR_CHANGE_MODE | |
408 | | REGULATOR_CHANGE_STATUS, | |
409 | }, | |
410 | .num_consumer_supplies = 1, | |
411 | .consumer_supplies = &cm_t35_vsim_supply, | |
412 | }; | |
413 | ||
7f049ad1 MR |
414 | /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ |
415 | static struct regulator_init_data cm_t35_vdac = { | |
416 | .constraints = { | |
417 | .min_uV = 1800000, | |
418 | .max_uV = 1800000, | |
419 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
420 | | REGULATOR_MODE_STANDBY, | |
421 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
422 | | REGULATOR_CHANGE_STATUS, | |
423 | }, | |
424 | .num_consumer_supplies = 1, | |
425 | .consumer_supplies = &cm_t35_vdac_supply, | |
426 | }; | |
427 | ||
428 | /* VPLL2 for digital video outputs */ | |
429 | static struct regulator_init_data cm_t35_vpll2 = { | |
430 | .constraints = { | |
431 | .name = "VDVI", | |
432 | .min_uV = 1800000, | |
433 | .max_uV = 1800000, | |
434 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
435 | | REGULATOR_MODE_STANDBY, | |
436 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
437 | | REGULATOR_CHANGE_STATUS, | |
438 | }, | |
439 | .num_consumer_supplies = 1, | |
440 | .consumer_supplies = &cm_t35_vdvi_supply, | |
441 | }; | |
442 | ||
2886d128 MR |
443 | static struct twl4030_usb_data cm_t35_usb_data = { |
444 | .usb_mode = T2_USB_MODE_ULPI, | |
445 | }; | |
446 | ||
bead4375 | 447 | static uint32_t cm_t35_keymap[] = { |
2886d128 MR |
448 | KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), |
449 | KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), | |
450 | KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), | |
451 | }; | |
452 | ||
453 | static struct matrix_keymap_data cm_t35_keymap_data = { | |
454 | .keymap = cm_t35_keymap, | |
455 | .keymap_size = ARRAY_SIZE(cm_t35_keymap), | |
456 | }; | |
457 | ||
458 | static struct twl4030_keypad_data cm_t35_kp_data = { | |
459 | .keymap_data = &cm_t35_keymap_data, | |
460 | .rows = 3, | |
461 | .cols = 3, | |
462 | .rep = 1, | |
463 | }; | |
464 | ||
68ff0423 | 465 | static struct omap2_hsmmc_info mmc[] = { |
2886d128 MR |
466 | { |
467 | .mmc = 1, | |
3a63833e | 468 | .caps = MMC_CAP_4_BIT_DATA, |
2886d128 MR |
469 | .gpio_cd = -EINVAL, |
470 | .gpio_wp = -EINVAL, | |
471 | ||
472 | }, | |
473 | { | |
474 | .mmc = 2, | |
3a63833e | 475 | .caps = MMC_CAP_4_BIT_DATA, |
2886d128 MR |
476 | .transceiver = 1, |
477 | .gpio_cd = -EINVAL, | |
478 | .gpio_wp = -EINVAL, | |
479 | .ocr_mask = 0x00100000, /* 3.3V */ | |
480 | }, | |
481 | {} /* Terminator */ | |
482 | }; | |
483 | ||
181b250c KM |
484 | static struct usbhs_omap_board_data usbhs_bdata __initdata = { |
485 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, | |
486 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | |
487 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | |
2886d128 MR |
488 | |
489 | .phy_reset = true, | |
1a6b5923 BW |
490 | .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, |
491 | .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7, | |
2886d128 MR |
492 | .reset_gpio_port[2] = -EINVAL |
493 | }; | |
494 | ||
495 | static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, | |
496 | unsigned ngpio) | |
497 | { | |
498 | int wlan_rst = gpio + 2; | |
499 | ||
500 | if ((gpio_request(wlan_rst, "WLAN RST") == 0) && | |
501 | (gpio_direction_output(wlan_rst, 1) == 0)) { | |
502 | gpio_export(wlan_rst, 0); | |
503 | ||
504 | udelay(10); | |
505 | gpio_set_value(wlan_rst, 0); | |
506 | udelay(10); | |
507 | gpio_set_value(wlan_rst, 1); | |
508 | } else { | |
509 | pr_err("CM-T35: could not obtain gpio for WiFi reset\n"); | |
510 | } | |
511 | ||
512 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | |
513 | mmc[0].gpio_cd = gpio + 0; | |
68ff0423 | 514 | omap2_hsmmc_init(mmc); |
2886d128 MR |
515 | |
516 | /* link regulators to MMC adapters */ | |
517 | cm_t35_vmmc1_supply.dev = mmc[0].dev; | |
518 | cm_t35_vsim_supply.dev = mmc[0].dev; | |
519 | ||
2886d128 MR |
520 | return 0; |
521 | } | |
522 | ||
523 | static struct twl4030_gpio_platform_data cm_t35_gpio_data = { | |
524 | .gpio_base = OMAP_MAX_GPIO_LINES, | |
525 | .irq_base = TWL4030_GPIO_IRQ_BASE, | |
526 | .irq_end = TWL4030_GPIO_IRQ_END, | |
527 | .setup = cm_t35_twl_gpio_setup, | |
528 | }; | |
529 | ||
530 | static struct twl4030_platform_data cm_t35_twldata = { | |
531 | .irq_base = TWL4030_IRQ_BASE, | |
532 | .irq_end = TWL4030_IRQ_END, | |
533 | ||
534 | /* platform_data for children goes here */ | |
535 | .keypad = &cm_t35_kp_data, | |
536 | .usb = &cm_t35_usb_data, | |
537 | .gpio = &cm_t35_gpio_data, | |
538 | .vmmc1 = &cm_t35_vmmc1, | |
539 | .vsim = &cm_t35_vsim, | |
7f049ad1 MR |
540 | .vdac = &cm_t35_vdac, |
541 | .vpll2 = &cm_t35_vpll2, | |
2886d128 MR |
542 | }; |
543 | ||
2886d128 MR |
544 | static void __init cm_t35_init_i2c(void) |
545 | { | |
fbd8071c | 546 | omap3_pmic_init("tps65930", &cm_t35_twldata); |
2886d128 MR |
547 | } |
548 | ||
3dc3bad6 | 549 | static void __init cm_t35_init_early(void) |
2886d128 | 550 | { |
4805734b PW |
551 | omap2_init_common_infrastructure(); |
552 | omap2_init_common_devices(mt46h32m32lf6_sdrc_params, | |
2886d128 | 553 | mt46h32m32lf6_sdrc_params); |
2886d128 MR |
554 | } |
555 | ||
c7ecea24 | 556 | #ifdef CONFIG_OMAP_MUX |
ca5742bd | 557 | static struct omap_board_mux board_mux[] __initdata = { |
edc961a2 MR |
558 | /* nCS and IRQ for CM-T35 ethernet */ |
559 | OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), | |
560 | OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
561 | ||
562 | /* nCS and IRQ for SB-T35 ethernet */ | |
563 | OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0), | |
564 | OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
565 | ||
566 | /* PENDOWN GPIO */ | |
567 | OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), | |
568 | ||
569 | /* mUSB */ | |
570 | OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
571 | OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
572 | OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
573 | OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
574 | OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
575 | OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
576 | OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
577 | OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
578 | OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
579 | OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
580 | OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
581 | OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
582 | ||
583 | /* MMC 2 */ | |
584 | OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
585 | OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
586 | OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
587 | OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
588 | ||
589 | /* McSPI 1 */ | |
590 | OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
591 | OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
592 | OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
593 | OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | |
594 | ||
595 | /* McSPI 4 */ | |
596 | OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
597 | OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
598 | OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
599 | OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP), | |
600 | ||
601 | /* McBSP 2 */ | |
602 | OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
603 | OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
604 | OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
605 | OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
606 | ||
607 | /* serial ports */ | |
608 | OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
609 | OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
610 | OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
611 | OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
612 | ||
613 | /* DSS */ | |
614 | OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
615 | OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
616 | OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
617 | OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
618 | OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
619 | OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
620 | OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
621 | OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
622 | OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
623 | OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
624 | OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
625 | OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
626 | OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
627 | OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
628 | OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
629 | OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
630 | OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
631 | OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
632 | OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
633 | OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
634 | OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
635 | OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
636 | OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
637 | OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
638 | OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
639 | OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
640 | OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
641 | OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
642 | ||
7f049ad1 MR |
643 | /* display controls */ |
644 | OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
645 | OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
646 | OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
647 | ||
edc961a2 MR |
648 | /* TPS IRQ */ |
649 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ | |
650 | OMAP_PIN_INPUT_PULLUP), | |
651 | ||
ca5742bd TL |
652 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
653 | }; | |
c7ecea24 | 654 | #endif |
ca5742bd | 655 | |
884b8369 MM |
656 | static struct omap_musb_board_data musb_board_data = { |
657 | .interface_type = MUSB_INTERFACE_ULPI, | |
658 | .mode = MUSB_OTG, | |
659 | .power = 100, | |
660 | }; | |
661 | ||
e41cccfe TL |
662 | static struct omap_board_config_kernel cm_t35_config[] __initdata = { |
663 | }; | |
664 | ||
2886d128 MR |
665 | static void __init cm_t35_init(void) |
666 | { | |
e41cccfe TL |
667 | omap_board_config = cm_t35_config; |
668 | omap_board_config_size = ARRAY_SIZE(cm_t35_config); | |
ca5742bd | 669 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); |
2886d128 MR |
670 | omap_serial_init(); |
671 | cm_t35_init_i2c(); | |
672 | cm_t35_init_nand(); | |
96974a24 | 673 | omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL); |
2886d128 MR |
674 | cm_t35_init_ethernet(); |
675 | cm_t35_init_led(); | |
7f049ad1 | 676 | cm_t35_init_display(); |
2886d128 | 677 | |
884b8369 | 678 | usb_musb_init(&musb_board_data); |
9e64bb1e | 679 | usbhs_init(&usbhs_bdata); |
2886d128 MR |
680 | } |
681 | ||
682 | MACHINE_START(CM_T35, "Compulab CM-T35") | |
2886d128 | 683 | .boot_params = 0x80000100, |
71ee7dad | 684 | .reserve = omap_reserve, |
3dc3bad6 RKAL |
685 | .map_io = omap3_map_io, |
686 | .init_early = cm_t35_init_early, | |
687 | .init_irq = omap_init_irq, | |
2886d128 MR |
688 | .init_machine = cm_t35_init, |
689 | .timer = &omap_timer, | |
690 | MACHINE_END |