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ARM: OMAP3: cm-t35: Use correct DSS regulator supply
[deliverable/linux.git] / arch / arm / mach-omap2 / board-cm-t35.c
CommitLineData
2886d128 1/*
c3146974 2 * CompuLab CM-T35/CM-T3730 modules support
2886d128 3 *
d12c2e28
IG		 4 * Copyright (C) 2009-2011 CompuLab, Ltd.
5 * Authors: Mike Rapoport <mike@compulab.co.il>
6 * Igor Grinberg <grinberg@compulab.co.il>
2886d128
MR		 7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
2886d128
MR		 17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/input.h>
23#include <linux/input/matrix_keypad.h>
24#include <linux/delay.h>
25#include <linux/gpio.h>
26
27#include <linux/i2c/at24.h>
ebeb53e1 28#include <linux/i2c/twl.h>
2886d128 29#include <linux/regulator/machine.h>
3a63833e 30#include <linux/mmc/host.h>
2886d128 31
7f049ad1
MR		 32#include <linux/spi/spi.h>
33#include <linux/spi/tdo24m.h>
34
2886d128
MR		 35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38
39#include <plat/board.h>
4e65331c 40#include "common.h"
2886d128
MR		 41#include <plat/nand.h>
42#include <plat/gpmc.h>
43#include <plat/usb.h>
a0b38cc4 44#include <video/omapdss.h>
f8ae2f08 45#include <video/omap-panel-generic-dpi.h>
1d7a8654 46#include <video/omap-panel-dvi.h>
609c9ba2 47#include <plat/mcspi.h>
2886d128
MR		 48
49#include <mach/hardware.h>
50
ca5742bd 51#include "mux.h"
2886d128 52#include "sdram-micron-mt46h32m32lf-6.h"
d02a900b 53#include "hsmmc.h"
96974a24 54#include "common-board-devices.h"
2886d128
MR		 55
56#define CM_T35_GPIO_PENDOWN 57
57
58#define CM_T35_SMSC911X_CS 5
59#define CM_T35_SMSC911X_GPIO 163
60#define SB_T35_SMSC911X_CS 4
61#define SB_T35_SMSC911X_GPIO 65
62
2886d128
MR		 63#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
64#include <linux/smsc911x.h>
21b42731 65#include <plat/gpmc-smsc911x.h>
2886d128 66
21b42731 67static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
2886d128 68 .id = 0,
21b42731
MR		 69 .cs = CM_T35_SMSC911X_CS,
70 .gpio_irq = CM_T35_SMSC911X_GPIO,
71 .gpio_reset = -EINVAL,
72 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
2886d128
MR		 73};
74
21b42731 75static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
2886d128 76 .id = 1,
21b42731
MR		 77 .cs = SB_T35_SMSC911X_CS,
78 .gpio_irq = SB_T35_SMSC911X_GPIO,
79 .gpio_reset = -EINVAL,
80 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
2886d128
MR		 81};
82
2886d128
MR		 83static void __init cm_t35_init_ethernet(void)
84{
21b42731
MR		 85 gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
86 gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
2886d128
MR		 87}
88#else
89static inline void __init cm_t35_init_ethernet(void) { return; }
90#endif
91
92#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
93#include <linux/leds.h>
94
95static struct gpio_led cm_t35_leds[] = {
96 [0] = {
97 .gpio = 186,
98 .name = "cm-t35:green",
99 .default_trigger = "heartbeat",
100 .active_low = 0,
101 },
102};
103
104static struct gpio_led_platform_data cm_t35_led_pdata = {
105 .num_leds = ARRAY_SIZE(cm_t35_leds),
106 .leds = cm_t35_leds,
107};
108
109static struct platform_device cm_t35_led_device = {
110 .name = "leds-gpio",
111 .id = -1,
112 .dev = {
113 .platform_data = &cm_t35_led_pdata,
114 },
115};
116
117static void __init cm_t35_init_led(void)
118{
119 platform_device_register(&cm_t35_led_device);
120}
121#else
122static inline void cm_t35_init_led(void) {}
123#endif
124
125#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
126#include <linux/mtd/mtd.h>
127#include <linux/mtd/nand.h>
128#include <linux/mtd/partitions.h>
129
130static struct mtd_partition cm_t35_nand_partitions[] = {
131 {
132 .name = "xloader",
133 .offset = 0, /* Offset = 0x00000 */
134 .size = 4 * NAND_BLOCK_SIZE,
135 .mask_flags = MTD_WRITEABLE
136 },
137 {
138 .name = "uboot",
139 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
140 .size = 15 * NAND_BLOCK_SIZE,
141 },
142 {
143 .name = "uboot environment",
144 .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
145 .size = 2 * NAND_BLOCK_SIZE,
146 },
147 {
148 .name = "linux",
d12c2e28 149 .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
2886d128
MR		 150 .size = 32 * NAND_BLOCK_SIZE,
151 },
152 {
153 .name = "rootfs",
d12c2e28 154 .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
2886d128
MR		 155 .size = MTDPART_SIZ_FULL,
156 },
157};
158
159static struct omap_nand_platform_data cm_t35_nand_data = {
160 .parts = cm_t35_nand_partitions,
161 .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
2886d128 162 .cs = 0,
2886d128
MR		 163};
164
2886d128
MR		 165static void __init cm_t35_init_nand(void)
166{
f450d867 167 if (gpmc_nand_init(&cm_t35_nand_data) < 0)
2886d128
MR		 168 pr_err("CM-T35: Unable to register NAND device\n");
169}
170#else
171static inline void cm_t35_init_nand(void) {}
172#endif
173
7f049ad1
MR		 174#define CM_T35_LCD_EN_GPIO 157
175#define CM_T35_LCD_BL_GPIO 58
176#define CM_T35_DVI_EN_GPIO 54
177
7f049ad1
MR		 178static int lcd_enabled;
179static int dvi_enabled;
180
181static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
182{
183 if (dvi_enabled) {
184 printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
185 return -EINVAL;
186 }
187
bc593f5d
IG		 188 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
189 gpio_set_value(CM_T35_LCD_BL_GPIO, 1);
7f049ad1
MR		 190
191 lcd_enabled = 1;
192
193 return 0;
194}
195
196static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
197{
198 lcd_enabled = 0;
199
bc593f5d
IG		 200 gpio_set_value(CM_T35_LCD_BL_GPIO, 0);
201 gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
7f049ad1
MR		 202}
203
204static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
205{
206 if (lcd_enabled) {
207 printk(KERN_ERR "cannot enable DVI, LCD is enabled\n");
208 return -EINVAL;
209 }
210
bc593f5d 211 gpio_set_value(CM_T35_DVI_EN_GPIO, 0);
7f049ad1
MR		 212 dvi_enabled = 1;
213
214 return 0;
215}
216
217static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
218{
bc593f5d 219 gpio_set_value(CM_T35_DVI_EN_GPIO, 1);
7f049ad1
MR		 220 dvi_enabled = 0;
221}
222
223static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
224{
225 return 0;
226}
227
228static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev)
229{
230}
231
89747c91
BW		 232static struct panel_generic_dpi_data lcd_panel = {
233 .name = "toppoly_tdo35s",
234 .platform_enable = cm_t35_panel_enable_lcd,
235 .platform_disable = cm_t35_panel_disable_lcd,
236};
237
7f049ad1
MR		 238static struct omap_dss_device cm_t35_lcd_device = {
239 .name = "lcd",
7f049ad1 240 .type = OMAP_DISPLAY_TYPE_DPI,
89747c91
BW		 241 .driver_name = "generic_dpi_panel",
242 .data = &lcd_panel,
7f049ad1 243 .phy.dpi.data_lines = 18,
89747c91
BW		 244};
245
1d7a8654 246static struct panel_dvi_platform_data dvi_panel = {
89747c91
BW		 247 .platform_enable = cm_t35_panel_enable_dvi,
248 .platform_disable = cm_t35_panel_disable_dvi,
7f049ad1
MR		 249};
250
251static struct omap_dss_device cm_t35_dvi_device = {
252 .name = "dvi",
7f049ad1 253 .type = OMAP_DISPLAY_TYPE_DPI,
1d7a8654 254 .driver_name = "dvi",
89747c91 255 .data = &dvi_panel,
7f049ad1 256 .phy.dpi.data_lines = 24,
7f049ad1
MR		 257};
258
259static struct omap_dss_device cm_t35_tv_device = {
260 .name = "tv",
261 .driver_name = "venc",
262 .type = OMAP_DISPLAY_TYPE_VENC,
263 .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO,
264 .platform_enable = cm_t35_panel_enable_tv,
265 .platform_disable = cm_t35_panel_disable_tv,
266};
267
268static struct omap_dss_device *cm_t35_dss_devices[] = {
269 &cm_t35_lcd_device,
270 &cm_t35_dvi_device,
271 &cm_t35_tv_device,
272};
273
274static struct omap_dss_board_info cm_t35_dss_data = {
275 .num_devices = ARRAY_SIZE(cm_t35_dss_devices),
276 .devices = cm_t35_dss_devices,
277 .default_device = &cm_t35_dvi_device,
278};
279
7f049ad1
MR		 280static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
281 .turbo_mode = 0,
282 .single_channel = 1, /* 0: slave, 1: master */
283};
284
285static struct tdo24m_platform_data tdo24m_config = {
286 .model = TDO35S,
287};
288
289static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
290 {
291 .modalias = "tdo24m",
292 .bus_num = 4,
293 .chip_select = 0,
294 .max_speed_hz = 1000000,
295 .controller_data = &tdo24m_mcspi_config,
296 .platform_data = &tdo24m_config,
297 },
298};
299
bc593f5d
IG		 300static struct gpio cm_t35_dss_gpios[] __initdata = {
301 { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" },
302 { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" },
303 { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable" },
304};
305
7f049ad1
MR		 306static void __init cm_t35_init_display(void)
307{
308 int err;
309
7f049ad1
MR		 310 spi_register_board_info(cm_t35_lcd_spi_board_info,
311 ARRAY_SIZE(cm_t35_lcd_spi_board_info));
312
bc593f5d
IG		 313 err = gpio_request_array(cm_t35_dss_gpios,
314 ARRAY_SIZE(cm_t35_dss_gpios));
7f049ad1 315 if (err) {
bc593f5d
IG		 316 pr_err("CM-T35: failed to request DSS control GPIOs\n");
317 return;
7f049ad1
MR		 318 }
319
bc593f5d
IG		 320 gpio_export(CM_T35_LCD_EN_GPIO, 0);
321 gpio_export(CM_T35_LCD_BL_GPIO, 0);
322 gpio_export(CM_T35_DVI_EN_GPIO, 0);
7f049ad1
MR		 323
324 msleep(50);
bc593f5d 325 gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
7f049ad1 326
d5e13227 327 err = omap_display_init(&cm_t35_dss_data);
7f049ad1
MR		 328 if (err) {
329 pr_err("CM-T35: failed to register DSS device\n");
bc593f5d 330 gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios));
7f049ad1 331 }
7f049ad1
MR		 332}
333
786b01a8
OD		 334static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
335 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
2886d128
MR		 336};
337
786b01a8
OD		 338static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
339 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
2886d128
MR		 340};
341
b74f149c
IG		 342static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
343 REGULATOR_SUPPLY("vcc", "spi1.0"),
cd1c683c
IG		 344 REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
345 REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
b74f149c
IG		 346};
347
2886d128
MR		 348/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
349static struct regulator_init_data cm_t35_vmmc1 = {
350 .constraints = {
351 .min_uV = 1850000,
352 .max_uV = 3150000,
353 .valid_modes_mask = REGULATOR_MODE_NORMAL
354 | REGULATOR_MODE_STANDBY,
355 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
356 | REGULATOR_CHANGE_MODE
357 | REGULATOR_CHANGE_STATUS,
358 },
786b01a8
OD		 359 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
360 .consumer_supplies = cm_t35_vmmc1_supply,
2886d128
MR		 361};
362
363/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
364static struct regulator_init_data cm_t35_vsim = {
365 .constraints = {
366 .min_uV = 1800000,
367 .max_uV = 3000000,
368 .valid_modes_mask = REGULATOR_MODE_NORMAL
369 | REGULATOR_MODE_STANDBY,
370 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
371 | REGULATOR_CHANGE_MODE
372 | REGULATOR_CHANGE_STATUS,
373 },
786b01a8
OD		 374 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
375 .consumer_supplies = cm_t35_vsim_supply,
2886d128
MR		 376};
377
b74f149c
IG		 378static struct regulator_init_data cm_t35_vio = {
379 .constraints = {
380 .min_uV = 1800000,
381 .max_uV = 1800000,
382 .apply_uV = true,
383 .valid_modes_mask = REGULATOR_MODE_NORMAL
384 | REGULATOR_MODE_STANDBY,
385 .valid_ops_mask = REGULATOR_CHANGE_MODE,
386 },
387 .num_consumer_supplies = ARRAY_SIZE(cm_t35_vio_supplies),
388 .consumer_supplies = cm_t35_vio_supplies,
389};
390
bead4375 391static uint32_t cm_t35_keymap[] = {
2886d128
MR		 392 KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT),
393 KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN),
394 KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D),
395};
396
397static struct matrix_keymap_data cm_t35_keymap_data = {
398 .keymap = cm_t35_keymap,
399 .keymap_size = ARRAY_SIZE(cm_t35_keymap),
400};
401
402static struct twl4030_keypad_data cm_t35_kp_data = {
403 .keymap_data = &cm_t35_keymap_data,
404 .rows = 3,
405 .cols = 3,
406 .rep = 1,
407};
408
68ff0423 409static struct omap2_hsmmc_info mmc[] = {
2886d128
MR		 410 {
411 .mmc = 1,
3a63833e 412 .caps = MMC_CAP_4_BIT_DATA,
2886d128
MR		 413 .gpio_cd = -EINVAL,
414 .gpio_wp = -EINVAL,
415
416 },
417 {
418 .mmc = 2,
3a63833e 419 .caps = MMC_CAP_4_BIT_DATA,
2886d128
MR		 420 .transceiver = 1,
421 .gpio_cd = -EINVAL,
422 .gpio_wp = -EINVAL,
423 .ocr_mask = 0x00100000, /* 3.3V */
424 },
425 {} /* Terminator */
426};
427
181b250c
KM		 428static struct usbhs_omap_board_data usbhs_bdata __initdata = {
429 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
430 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
431 .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
2886d128
MR		 432
433 .phy_reset = true,
1a6b5923
BW		 434 .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6,
435 .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7,
2886d128
MR		 436 .reset_gpio_port[2] = -EINVAL
437};
438
439static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
440 unsigned ngpio)
441{
442 int wlan_rst = gpio + 2;
443
bc593f5d 444 if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
2886d128 445 gpio_export(wlan_rst, 0);
2886d128 446 udelay(10);
be741de1 447 gpio_set_value_cansleep(wlan_rst, 0);
2886d128 448 udelay(10);
be741de1 449 gpio_set_value_cansleep(wlan_rst, 1);
2886d128
MR		 450 } else {
451 pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
452 }
453
454 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
455 mmc[0].gpio_cd = gpio + 0;
68ff0423 456 omap2_hsmmc_init(mmc);
2886d128 457
2886d128
MR		 458 return 0;
459}
460
461static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
462 .gpio_base = OMAP_MAX_GPIO_LINES,
463 .irq_base = TWL4030_GPIO_IRQ_BASE,
464 .irq_end = TWL4030_GPIO_IRQ_END,
465 .setup = cm_t35_twl_gpio_setup,
466};
467
468static struct twl4030_platform_data cm_t35_twldata = {
2886d128
MR		 469 /* platform_data for children goes here */
470 .keypad = &cm_t35_kp_data,
2886d128
MR		 471 .gpio = &cm_t35_gpio_data,
472 .vmmc1 = &cm_t35_vmmc1,
473 .vsim = &cm_t35_vsim,
b74f149c 474 .vio = &cm_t35_vio,
2886d128
MR		 475};
476
2886d128
MR		 477static void __init cm_t35_init_i2c(void)
478{
b252b0ef 479 omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
cd1c683c 480 TWL_COMMON_REGULATOR_VDAC);
b252b0ef 481
fbd8071c 482 omap3_pmic_init("tps65930", &cm_t35_twldata);
2886d128
MR		 483}
484
c7ecea24 485#ifdef CONFIG_OMAP_MUX
ca5742bd 486static struct omap_board_mux board_mux[] __initdata = {
edc961a2
MR		 487 /* nCS and IRQ for CM-T35 ethernet */
488 OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
489 OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
490
491 /* nCS and IRQ for SB-T35 ethernet */
492 OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
493 OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
494
495 /* PENDOWN GPIO */
496 OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
497
498 /* mUSB */
499 OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
500 OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
501 OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
502 OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
503 OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
504 OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
505 OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
506 OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
507 OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
508 OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
509 OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
510 OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
511
512 /* MMC 2 */
513 OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
514 OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
515 OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
516 OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
517
518 /* McSPI 1 */
519 OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
520 OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
521 OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
522 OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
523
524 /* McSPI 4 */
525 OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
526 OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
527 OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
528 OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
529
530 /* McBSP 2 */
531 OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
532 OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
533 OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
534 OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
535
536 /* serial ports */
537 OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
538 OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
539 OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
540 OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
541
c3146974 542 /* common DSS */
edc961a2
MR		 543 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
544 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
545 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
546 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
edc961a2
MR		 547 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
548 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
549 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
550 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
551 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
552 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
553 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
554 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
555 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
556 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
557 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
558 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
edc961a2 559
7f049ad1
MR		 560 /* display controls */
561 OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
562 OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
563 OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
564
edc961a2
MR		 565 /* TPS IRQ */
566 OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
567 OMAP_PIN_INPUT_PULLUP),
568
ca5742bd
TL		 569 { .reg_offset = OMAP_MUX_TERMINATOR },
570};
c3146974
IG		 571
572static void __init cm_t3x_common_dss_mux_init(int mux_mode)
573{
574 omap_mux_init_signal("dss_data18", mux_mode);
575 omap_mux_init_signal("dss_data19", mux_mode);
576 omap_mux_init_signal("dss_data20", mux_mode);
577 omap_mux_init_signal("dss_data21", mux_mode);
578 omap_mux_init_signal("dss_data22", mux_mode);
579 omap_mux_init_signal("dss_data23", mux_mode);
580}
581
582static void __init cm_t35_init_mux(void)
583{
584 omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
585 omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
586 omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
587 omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
588 omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
589 omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
590 cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
591}
592
593static void __init cm_t3730_init_mux(void)
594{
595 omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
596 omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
597 omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
598 omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
599 omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
600 omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
601 cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
602}
603#else
604static inline void cm_t35_init_mux(void) {}
605static inline void cm_t3730_init_mux(void) {}
c7ecea24 606#endif
ca5742bd 607
e41cccfe
TL		 608static struct omap_board_config_kernel cm_t35_config[] __initdata = {
609};
610
c3146974 611static void __init cm_t3x_common_init(void)
2886d128 612{
e41cccfe
TL		 613 omap_board_config = cm_t35_config;
614 omap_board_config_size = ARRAY_SIZE(cm_t35_config);
ca5742bd 615 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
2886d128 616 omap_serial_init();
a4ca9dbe
TL		 617 omap_sdrc_init(mt46h32m32lf6_sdrc_params,
618 mt46h32m32lf6_sdrc_params);
2886d128 619 cm_t35_init_i2c();
96974a24 620 omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
2886d128
MR		 621 cm_t35_init_ethernet();
622 cm_t35_init_led();
7f049ad1 623 cm_t35_init_display();
2886d128 624
9e18630b 625 usb_musb_init(NULL);
9e64bb1e 626 usbhs_init(&usbhs_bdata);
2886d128
MR		 627}
628
c3146974
IG		 629static void __init cm_t35_init(void)
630{
631 cm_t3x_common_init();
632 cm_t35_init_mux();
633 cm_t35_init_nand();
634}
635
636static void __init cm_t3730_init(void)
637{
638 cm_t3x_common_init();
639 cm_t3730_init_mux();
640}
641
2886d128 642MACHINE_START(CM_T35, "Compulab CM-T35")
5e52b435 643 .atag_offset = 0x100,
71ee7dad 644 .reserve = omap_reserve,
3dc3bad6 645 .map_io = omap3_map_io,
8f5b5a41 646 .init_early = omap35xx_init_early,
741e3a89 647 .init_irq = omap3_init_irq,
6b2f55d7 648 .handle_irq = omap3_intc_handle_irq,
2886d128 649 .init_machine = cm_t35_init,
e74984e4 650 .timer = &omap3_timer,
2886d128 651MACHINE_END
c3146974
IG		 652
653MACHINE_START(CM_T3730, "Compulab CM-T3730")
5e52b435 654 .atag_offset = 0x100,
c3146974
IG		 655 .reserve = omap_reserve,
656 .map_io = omap3_map_io,
8f5b5a41 657 .init_early = omap3630_init_early,
c3146974 658 .init_irq = omap3_init_irq,
6b2f55d7 659 .handle_irq = omap3_intc_handle_irq,
c3146974
IG		 660 .init_machine = cm_t3730_init,
661 .timer = &omap3_timer,
662MACHINE_END
Linux kernel - Deliverables
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