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ARM: OMAP2+: Fix imprecise external abort caused by bogus SRAM init
[deliverable/linux.git] / arch / arm / mach-omap2 / board-generic.c
CommitLineData
1dbae815 1/*
1dbae815
TL		 2 * Copyright (C) 2005 Nokia Corporation
3 * Author: Paul Mundt <paul.mundt@nokia.com>
4 *
8d61649d 5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
1dbae815 6 *
8d61649d
BC		 7 * Modified from the original mach-omap/omap2/board-generic.c did by Paul
8 * to support the OMAP2+ device tree boards with an unique board file.
1dbae815
TL		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
8d61649d 14#include <linux/io.h>
fbf75da7 15#include <linux/of_irq.h>
8d61649d
BC		 16#include <linux/of_platform.h>
17#include <linux/irqdomain.h>
1dbae815 18
1dbae815 19#include <asm/mach/arch.h>
1dbae815 20
4e65331c 21#include "common.h"
8d61649d 22
31957609 23static const struct of_device_id omap_dt_match_table[] __initconst = {
8d61649d
BC		 24 { .compatible = "simple-bus", },
25 { .compatible = "ti,omap-infra", },
26 { }
b3c6df3a
PW		 27};
28
1dbae815
TL		 29static void __init omap_generic_init(void)
30{
6a0e6b38
TV		 31 omapdss_early_init_of();
32
8651bd8c 33 pdata_quirks_init(omap_dt_match_table);
dcdf407b
TV		 34
35 omapdss_init_of();
1dbae815
TL		 36}
37
0e02a8c1 38#ifdef CONFIG_SOC_OMAP2420
58cda01e 39static const char *const omap242x_boards_compat[] __initconst = {
8d61649d
BC		 40 "ti,omap2420",
41 NULL,
42};
43
44DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
45 .reserve = omap_reserve,
46 .map_io = omap242x_map_io,
47 .init_early = omap2420_init_early,
8d61649d 48 .init_machine = omap_generic_init,
6bb27d73 49 .init_time = omap2_sync32k_timer_init,
8d61649d 50 .dt_compat = omap242x_boards_compat,
187e3e06 51 .restart = omap2xxx_restart,
8d61649d
BC		 52MACHINE_END
53#endif
54
0e02a8c1 55#ifdef CONFIG_SOC_OMAP2430
58cda01e 56static const char *const omap243x_boards_compat[] __initconst = {
8d61649d
BC		 57 "ti,omap2430",
58 NULL,
59};
60
61DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
71ee7dad 62 .reserve = omap_reserve,
8d61649d
BC		 63 .map_io = omap243x_map_io,
64 .init_early = omap2430_init_early,
1dbae815 65 .init_machine = omap_generic_init,
6bb27d73 66 .init_time = omap2_sync32k_timer_init,
8d61649d 67 .dt_compat = omap243x_boards_compat,
187e3e06 68 .restart = omap2xxx_restart,
8d61649d
BC		 69MACHINE_END
70#endif
71
0e02a8c1 72#ifdef CONFIG_ARCH_OMAP3
71c4f602
TL		 73/* Some boards need board name for legacy userspace in /proc/cpuinfo */
74static const char *const n900_boards_compat[] __initconst = {
75 "nokia,omap3-n900",
76 NULL,
77};
78
79DT_MACHINE_START(OMAP3_N900_DT, "Nokia RX-51 board")
80 .reserve = omap_reserve,
81 .map_io = omap3_map_io,
82 .init_early = omap3430_init_early,
83 .init_machine = omap_generic_init,
84 .init_late = omap3_init_late,
85 .init_time = omap3_sync32k_timer_init,
86 .dt_compat = n900_boards_compat,
87 .restart = omap3xxx_restart,
88MACHINE_END
89
90/* Generic omap3 boards, most boards can use these */
58cda01e 91static const char *const omap3_boards_compat[] __initconst = {
b83a08fe 92 "ti,omap3430",
8d61649d
BC		 93 "ti,omap3",
94 NULL,
95};
96
97DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
98 .reserve = omap_reserve,
99 .map_io = omap3_map_io,
100 .init_early = omap3430_init_early,
93651b85 101 .init_machine = omap_generic_init,
990fa4f5 102 .init_late = omap3_init_late,
6bb27d73 103 .init_time = omap3_sync32k_timer_init,
8d61649d 104 .dt_compat = omap3_boards_compat,
187e3e06 105 .restart = omap3xxx_restart,
8d61649d 106MACHINE_END
7dd9d502 107
58cda01e 108static const char *const omap36xx_boards_compat[] __initconst = {
57df5380 109 "ti,omap3630",
016c12d2
NM		 110 "ti,omap36xx",
111 NULL,
112};
113
114DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
115 .reserve = omap_reserve,
116 .map_io = omap3_map_io,
117 .init_early = omap3630_init_early,
016c12d2
NM		 118 .init_machine = omap_generic_init,
119 .init_late = omap3_init_late,
120 .init_time = omap3_sync32k_timer_init,
121 .dt_compat = omap36xx_boards_compat,
122 .restart = omap3xxx_restart,
123MACHINE_END
124
58cda01e 125static const char *const omap3_gp_boards_compat[] __initconst = {
7dd9d502 126 "ti,omap3-beagle",
4bfe6341 127 "timll,omap3-devkit8000",
7dd9d502
JH		 128 NULL,
129};
130
131DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
132 .reserve = omap_reserve,
133 .map_io = omap3_map_io,
134 .init_early = omap3430_init_early,
7dd9d502 135 .init_machine = omap_generic_init,
990fa4f5 136 .init_late = omap3_init_late,
6bb27d73 137 .init_time = omap3_secure_sync32k_timer_init,
7dd9d502 138 .dt_compat = omap3_gp_boards_compat,
d01e4afd 139 .restart = omap3xxx_restart,
8d61649d 140MACHINE_END
caef4ee8 141
58cda01e 142static const char *const am3517_boards_compat[] __initconst = {
caef4ee8
NM		 143 "ti,am3517",
144 NULL,
145};
146
147DT_MACHINE_START(AM3517_DT, "Generic AM3517 (Flattened Device Tree)")
148 .reserve = omap_reserve,
149 .map_io = omap3_map_io,
150 .init_early = am35xx_init_early,
caef4ee8
NM		 151 .init_machine = omap_generic_init,
152 .init_late = omap3_init_late,
153 .init_time = omap3_gptimer_timer_init,
154 .dt_compat = am3517_boards_compat,
155 .restart = omap3xxx_restart,
156MACHINE_END
8d61649d
BC		 157#endif
158
abf8cc1d
TL		 159#ifdef CONFIG_SOC_TI81XX
160static const char *const ti814x_boards_compat[] __initconst = {
161 "ti,dm8148",
162 "ti,dm814",
163 NULL,
164};
165
9fd274c0 166DT_MACHINE_START(TI814X_DT, "Generic ti814x (Flattened Device Tree)")
abf8cc1d
TL		 167 .reserve = omap_reserve,
168 .map_io = ti81xx_map_io,
169 .init_early = ti814x_init_early,
170 .init_machine = omap_generic_init,
171 .init_late = ti81xx_init_late,
172 .init_time = omap3_gptimer_timer_init,
173 .dt_compat = ti814x_boards_compat,
174 .restart = ti81xx_restart,
175MACHINE_END
176
177static const char *const ti816x_boards_compat[] __initconst = {
178 "ti,dm8168",
179 "ti,dm816",
180 NULL,
181};
182
183DT_MACHINE_START(TI816X_DT, "Generic ti816x (Flattened Device Tree)")
184 .reserve = omap_reserve,
185 .map_io = ti81xx_map_io,
186 .init_early = ti816x_init_early,
187 .init_machine = omap_generic_init,
188 .init_late = ti81xx_init_late,
189 .init_time = omap3_gptimer_timer_init,
190 .dt_compat = ti816x_boards_compat,
191 .restart = ti81xx_restart,
192MACHINE_END
193#endif
194
08f30989 195#ifdef CONFIG_SOC_AM33XX
58cda01e 196static const char *const am33xx_boards_compat[] __initconst = {
08f30989
AM		 197 "ti,am33xx",
198 NULL,
199};
200
201DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
202 .reserve = omap_reserve,
203 .map_io = am33xx_map_io,
204 .init_early = am33xx_init_early,
08f30989 205 .init_machine = omap_generic_init,
765e7a06 206 .init_late = am33xx_init_late,
00ea4d56 207 .init_time = omap3_gptimer_timer_init,
08f30989 208 .dt_compat = am33xx_boards_compat,
14e067c1 209 .restart = am33xx_restart,
08f30989
AM		 210MACHINE_END
211#endif
212
0e02a8c1 213#ifdef CONFIG_ARCH_OMAP4
58cda01e 214static const char *const omap4_boards_compat[] __initconst = {
b83a08fe
NM		 215 "ti,omap4460",
216 "ti,omap4430",
8d61649d
BC		 217 "ti,omap4",
218 NULL,
219};
220
221DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
944e9df1
MS		 222 .l2c_aux_val = OMAP_L2C_AUX_CTRL,
223 .l2c_aux_mask = 0xcf9fffff,
224 .l2c_write_sec = omap4_l2c310_write_sec,
8d61649d 225 .reserve = omap_reserve,
06915321 226 .smp = smp_ops(omap4_smp_ops),
8d61649d
BC		 227 .map_io = omap4_map_io,
228 .init_early = omap4430_init_early,
c4082d49 229 .init_irq = omap_gic_of_init,
93651b85 230 .init_machine = omap_generic_init,
bbd707ac 231 .init_late = omap4430_init_late,
6bb27d73 232 .init_time = omap4_local_timer_init,
8d61649d 233 .dt_compat = omap4_boards_compat,
187e3e06 234 .restart = omap44xx_restart,
1dbae815 235MACHINE_END
8d61649d 236#endif
0c1b6fac
S		 237
238#ifdef CONFIG_SOC_OMAP5
58cda01e 239static const char *const omap5_boards_compat[] __initconst = {
b83a08fe
NM		 240 "ti,omap5432",
241 "ti,omap5430",
0c1b6fac
S		 242 "ti,omap5",
243 NULL,
244};
245
246DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
6a3b764b
TL		 247#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
248 .dma_zone_size = SZ_2G,
249#endif
0c1b6fac 250 .reserve = omap_reserve,
06915321 251 .smp = smp_ops(omap4_smp_ops),
0c1b6fac
S		 252 .map_io = omap5_map_io,
253 .init_early = omap5_init_early,
254 .init_irq = omap_gic_of_init,
0c1b6fac 255 .init_machine = omap_generic_init,
765e7a06 256 .init_late = omap5_init_late,
6bb27d73 257 .init_time = omap5_realtime_timer_init,
0c1b6fac 258 .dt_compat = omap5_boards_compat,
187e3e06 259 .restart = omap44xx_restart,
0c1b6fac
S		 260MACHINE_END
261#endif
bb256f80
AM		 262
263#ifdef CONFIG_SOC_AM43XX
58cda01e 264static const char *const am43_boards_compat[] __initconst = {
b83a08fe 265 "ti,am4372",
bb256f80
AM		 266 "ti,am43",
267 NULL,
268};
269
270DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
944e9df1
MS		 271 .l2c_aux_val = OMAP_L2C_AUX_CTRL,
272 .l2c_aux_mask = 0xcf9fffff,
273 .l2c_write_sec = omap4_l2c310_write_sec,
bb256f80
AM		 274 .map_io = am33xx_map_io,
275 .init_early = am43xx_init_early,
765e7a06 276 .init_late = am43xx_init_late,
bb256f80
AM		 277 .init_irq = omap_gic_of_init,
278 .init_machine = omap_generic_init,
5b5c0135 279 .init_time = omap3_gptimer_timer_init,
bb256f80 280 .dt_compat = am43_boards_compat,
a7daf64a 281 .restart = omap44xx_restart,
bb256f80
AM		 282MACHINE_END
283#endif
439bf39e
S		 284
285#ifdef CONFIG_SOC_DRA7XX
58cda01e 286static const char *const dra74x_boards_compat[] __initconst = {
0e0cb99d
NM		 287 "ti,am5728",
288 "ti,am5726",
44e97ff6 289 "ti,dra742",
439bf39e
S		 290 "ti,dra7",
291 NULL,
292};
293
44e97ff6 294DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
6a3b764b
TL		 295#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
296 .dma_zone_size = SZ_2G,
297#endif
439bf39e
S		 298 .reserve = omap_reserve,
299 .smp = smp_ops(omap4_smp_ops),
ea827ad5 300 .map_io = dra7xx_map_io,
439bf39e 301 .init_early = dra7xx_init_early,
765e7a06 302 .init_late = dra7xx_init_late,
439bf39e
S		 303 .init_irq = omap_gic_of_init,
304 .init_machine = omap_generic_init,
305 .init_time = omap5_realtime_timer_init,
44e97ff6
RN		 306 .dt_compat = dra74x_boards_compat,
307 .restart = omap44xx_restart,
308MACHINE_END
309
58cda01e 310static const char *const dra72x_boards_compat[] __initconst = {
0e0cb99d
NM		 311 "ti,am5718",
312 "ti,am5716",
44e97ff6
RN		 313 "ti,dra722",
314 NULL,
315};
316
317DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)")
6a3b764b
TL		 318#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
319 .dma_zone_size = SZ_2G,
320#endif
44e97ff6 321 .reserve = omap_reserve,
ea827ad5 322 .map_io = dra7xx_map_io,
44e97ff6
RN		 323 .init_early = dra7xx_init_early,
324 .init_late = dra7xx_init_late,
325 .init_irq = omap_gic_of_init,
326 .init_machine = omap_generic_init,
327 .init_time = omap5_realtime_timer_init,
328 .dt_compat = dra72x_boards_compat,
1d597b07 329 .restart = omap44xx_restart,
439bf39e
S		 330MACHINE_END
331#endif
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